CN114999924A

Movatterモバイル変換

Info

Publication number: CN114999924A
Application number: CN202210622060.1A
Authority: CN
Inventors: 朱仲明; 吴奇斌; 吴莹莹; 周海锋; 江燕芬; 吴莉亚; 钱江云
Original assignee: Jiangsu Zunyang Electronic Technology Co ltd
Current assignee: Jiangsu Zunyang Electronic Technology Co ltd
Priority date: 2022-06-01
Filing date: 2022-06-01
Publication date: 2022-09-02
Anticipated expiration: 2042-06-01
Also published as: CN114999924B

Abstract

The invention relates to an embedded chip packaging process and an embedded chip.A chip frame is selected, a bare chip of a first chip is installed on a circuit layer, and plastic package is carried out; etching the back of the chip frame, etching the metal substrate to form an embedded area, loading a second chip into the embedded area, and carrying out back plastic package; polishing the back plastic packaging layer to expose the back of the metal substrate; cutting and separating to form the embedded chip of the invention. The invention provides a production process with mature technical route aiming at the improved embedded packaged chip structure, and can manufacture the embedded chip with high efficiency and high quality, thereby reducing the production cost, improving the heat dissipation effect of the product and improving the signal transmission efficiency.

Description

Embedded chip packaging process and embedded chip

Technical Field

The invention relates to a chip packaging structure and a process, in particular to a process for integrated embedded packaging by integrating an IC circuit chip and an RLC passive component and a corresponding chip structure, belonging to the field of chip packaging.

Background

The embedded chip package, or embedded chip package, means that in the IC circuit chip packaging process, the RLC passive components are pre-installed in the chip to realize integrated package, thereby reducing the occupied space of the chip on the PCB.

As shown in fig. 1, in the conventional embedded chip package structure, a series of exposure and development processes are performed on a metal plate to electroplate a metal layer circuit and a conductive copper pillar, and after internal packaging, plastic packaging material is ground to expose the copper pillar, which is used as a final output outer pin. And secondly, etching the metal plate, and packaging the flip chip in the inner space. However, such a structure has the following disadvantages:

1. the metal plate is exposed and developed for multiple times and electroplated with the conductive copper column, and grinding is needed after encapsulation, so that the process is relatively complex and the cost loss is large;

2. the periphery of the structure is wrapped by the plastic package material, and heat is dissipated only through the plastic package material after the structure is mounted on the plate, so that the heat dissipation effect is poor;

3. the signal is transmitted to the inner pin through the wire and then transmitted to the PCB through the conductive copper column, and the signal is transmitted slowly through a plurality of media in the period;

therefore, there is a need for improvement of an embedded chip package structure to solve the problems of poor heat dissipation of the package, slow signal transmission, and high cost consumption.

Disclosure of Invention

The invention aims to provide an embedded chip packaging process and an embedded chip, aiming at solving the problems of poor heat dissipation of a packaging body, slow signal transmission and high production cost consumption.

In order to achieve the above object, a first aspect of the present invention provides an embedded chip packaging process, including the following steps:

step A, front surface mounting and ball bonding of the metal substrate:

taking a finished product chip frame, mounting a first chip on a base island region of a circuit layer of the chip frame through an adhesive, wherein the first chip is a bare chip; then, carrying out a ball bonding process, and connecting the first chip and peripheral pins together through an internal lead;

step B, plastic package of the front side: carrying out a first plastic packaging process on a first chip mounting surface of the chip frame to form a front plastic packaging layer;

c, sticking a photoresist film again: c, pasting an exposed and developed photoresist film on the surface of the product finished in the step B;

step D, removing part of the photoresist film on the back of the chip frame: c, carrying out pattern exposure and development on the back surface of the chip frame subjected to the photoresist film pasting operation in the step C by using exposure and development equipment, and removing part of the pattern photoresist film to expose a region needing to be etched subsequently on the back surface of the chip frame;

step E, etching: d, chemically etching the region of the back surface of the chip frame, from which part of the photoresist film is removed, and etching the region into the metal substrate of the chip frame until the region is close to the surface of the front surface to form an embedded region;

step F, removing the photoresist film: washing to remove the photoresist film and expose the chip frame;

step G, SMT pasting components: mounting and mounting the components in the back etching area by an SMT process, namely mounting the second chip in the mounting area;

step H, back plastic package: carrying out plastic packaging in the etching area, and protecting the components to form a back plastic packaging layer;

then polishing is carried out, and the metal on the back surface of the chip frame is exposed;

step I, cutting and separating: and cutting and separating products, and reserving the required packaging body as a finished product, namely the embedded chip.

As a further improvement of the present invention, the finished chip frame in step a adopts the following manufacturing steps:

step 1, taking a metal substrate: taking a metal substrate for later use;

step 3, pasting a photoresist film: respectively sticking photoresist films which can be exposed and developed on the front surface and the back surface of the metal substrate;

and 4, removing part of the photoresist film on the front surface of the metal substrate: exposing and developing the front surface of the metal substrate pasted with the photoresist film in thestep 3 by using exposure and development equipment, and removing part of the photoresist film to expose the area of the front surface of the metal substrate which needs to be plated with the metal circuit layer;

step 5, electroplating a metal circuit layer: electroplating a metal circuit layer in the region of the front surface of the metal substrate with part of the photoresist film removed in thestep 4, namely forming a corresponding base island and a corresponding pin on the front surface of the metal substrate;

step 6, removing the photoresist film: removing the photoresist film on the surface of the metal substrate;

and cleaning and airing to obtain the chip frame.

Further, astep 2 is arranged between thestep 1 and thestep 3;

step 2, pre-plating a copper material on the surface of themetal substrate 1 to form a protective layer;

pre-plating a layer of material on the surface of the metal substrate to form a protective layer;

the protective layer is made of oxidation-resistant metal material;

and the photoresist film in thestep 3 is attached to the outer side of the protective layer.

As a further improvement of the present invention, the etching in step E is to design a desired shape on the photoresist film used in step C; then in step E, chemical etching is adopted to remove the metal layer in the back non-effective area;

the etching speed and depth are controlled by parameters such as the concentration of a liquid medicine, time and the like, so that the reserved front metal layer can meet the requirement of the later welding thickness;

meanwhile, the metal layer which is originally integrated is etched and disconnected through the film pasting design, and isolation of the functional output terminal is formed.

Further, after the etching in the step E is finished, electroplating is carried out;

and carrying out accurate electroplating on the etched surface, and adopting a fixed chain speed transmission mechanism to realize uniform metal coating distribution by adopting a stable current scheme so as to ensure that the electroplated surface is smooth.

As a further improvement of the present invention, in the step G, the second chip is a packaged RLC passive component;

the second chip is provided with a plurality of chips, and the models of the chips are different.

In a further improvement of the present invention, in the step H, after the back surface of the metal substrate is exposed, a semi-bright electrolytic tin plating is performed to form a plating protective film on the exposed metal region.

In a second aspect of the present invention, an embedded chip is provided, which is manufactured by the above process;

the chip comprises a chip frame, a first chip, a second chip and a plastic package layer;

the front surface of the chip frame is provided with a metal circuit layer as a first chip mounting area;

the first chip is a die; the first chip is fixed on the base island of the metal circuit layer of the chip frame through an adhesive; the first chip is connected with the outer side pins of the metal circuit layer of the chip frame through inner leads;

the back surface of the chip frame is partially etched to form a second chip mounting area; the second chip mounting area is arranged between the base island and the outer side pin of the front surface of the chip frame in a spanning mode; etching of the second chip mounting area is deep into the metal substrate of the chip frame, and the etching surface is close to the metal circuit layer on the front surface of the chip frame;

the second chip is a packaged RLC passive component; the second chip is arranged in a second chip mounting area on the back surface of the chip frame; the second chip is completely positioned in the embedded area formed by etching the second chip mounting area; the surface of the second chip does not exceed the back plane of the chip frame;

performing plastic packaging in the first chip packaging area and the second chip packaging area to form a plastic packaging layer; the outer surface of the plastic packaging layer on the second chip loading area side is polished to be not higher than the back plane of the chip frame;

and the back metal of the chip frame is exposed outside the plastic package layer.

Further, a protective film is plated on the back surface of the chip frame; and the outer surface of the plastic packaging layer at the second chip loading area side is flush with the outer surface of the back surface of the chip frame.

Compared with the prior art, the invention has the following advantages:

1. the production cost is reduced; the output pin is formed by etching the metal substrate, and a conductive copper column does not need to be electroplated, so that electroplating and grinding processes are reduced, and material cost and production process cost are reduced;

2. the heat dissipation effect is improved; the metal substrate is directly used as an output outer pin after being etched, and after the upper plate is attached, heat can be dissipated through the metal substrate, so that the heat dissipation effect is good; the metal substrate corresponding to the mounting position base island of the first chip is exposed on the back surface of the chip, so that heat can be directly dissipated, and the heat dissipation effect is obviously improved;

3. the signal transmission efficiency is improved; the outer pins are directly connected with the inner pins and the base island, so that the signal transmission speed is high.

The invention provides a production process with mature technical route aiming at the improved embedded packaged chip structure, and can manufacture the embedded chip with high efficiency and high quality, thereby reducing the production cost, improving the heat dissipation effect of the product and improving the signal transmission efficiency.

Drawings

FIG. 1 is a schematic diagram of a conventional chip structure;

FIG. 2 is a schematic diagram of a final package structure of the present invention;

FIG. 3 is a schematic structural diagram of a copper-clad metal substrate produced instep 2 according to the present invention;

FIG. 4 is a schematic structural view of the invention after a photoresist film is applied instep 3;

FIG. 5 is a schematic structural diagram of the photoresist film ofstep 4 of the present invention after removing a portion of the pattern;

FIG. 6 is a schematic diagram of the structure of the electroplated metal wiring layer ofstep 5 of the present invention;

FIG. 7 is a schematic view of the present invention instep 6 for removing all the photoresist film;

FIG. 8 is a schematic assembled structure diagram of the first chip instep 7 of the present invention;

FIG. 9 is a schematic diagram of the front side ofstep 8 after being molded according to the present invention;

FIG. 10 is a schematic structural view ofstep 9 of the present invention after the second photoresist film pasting;

FIG. 11 is a schematic structural diagram of the backside photoresist film after removing a portion of the pattern in step 10 of the present invention;

FIG. 12 is a schematic structural diagram of the metal substrate after etching in step 11 of the present invention;

FIG. 13 is a schematic diagram of the present invention in step 12 for removing all the photoresist film;

FIG. 14 is a schematic diagram of the second die after mounting at step 13 of the present invention;

fig. 15 is a schematic structural diagram of the invention after the back side molding in step 14.

Detailed Description

The invention is further described below with reference to the following figures and specific examples.

As shown in fig. 2, the final package structure of the embedded chip package structure of the present invention has a metal substrate 1 in the middle, and copper materials are pre-plated on the upper and lower layers to form a protection layer 2; the upper part of the metal substrate 1 is a first chip mounting area, and the lower part of the metal substrate 1 is a second chip mounting area; in the first chip mounting area, an electroplated metal circuit layer 3 is formed on the protective layer 2 through treatment, a base island is formed in the middle through silver plating treatment generally, the base island is used for loading a chip, and pins are formed on the outer side of the base island; fixing a first chip 5 on the base island through an adhesive 4, wherein the first chip 5 is an IC circuit chip, is a bare chip and is connected with the outer side pins through inner leads 6 by a ball bonding process; the metal substrate 1 is subjected to hollow etching according to needs, the upper protective layer 2 is reserved, and the second chip 7 is attached in the hollow etching area of the metal substrate 1 through an SMT (surface mount technology) process; finally, plastic packaging is carried out by using a plastic packaging material to form a plastic packaging layer 8.

In the second mounting area, theplastic package layer 8 is only filled in the hollow etching area, so that the bottom surface of themetal substrate 1 and the bottomsurface protection layer 2 are exposed to the outside, and heat dissipation is performed through the metal surface. Moreover, the bottomsurface protection layer 2 of themetal base 1 is directly used as an external interface, so that conductive copper columns are reduced, and the signal transmission speed is higher.

The manufacturing and production process flow of the embedded chip packaging structure of the invention is as follows:

step 1, taking ametal substrate 1

Aproper metal substrate 1 is taken, the material of themetal substrate 1 can be copper material, iron material, galvanized material, stainless steel material, aluminum material or metal material or nonmetal material which can achieve the conductive function, the thickness can be selected according to the product characteristics, and the thickness is generally 6, 8, 10 and 20 mm.

Step 2, pre-plating copper material on the surface of themetal substrate 1 to form aprotective layer 2

If thesubstrate 1 is a non-copper material, a layer of material can be pre-plated on the surface of themetal substrate 1 to form oxidation-resistant materials such as copper, silver, gold, alloy and the like, and aprotective layer 2 is formed, wherein the thickness of the protective layer is 2-10 microns, the protective layer can be thinned or thickened according to functional requirements, and the electroplating mode can be electrolytic electroplating or chemical deposition; and (5) finally obtaining a finished product, as shown in figure 3.

Aprotective layer 2 is pre-plated on the surface of asubstrate 1 which is not made of copper materials, and the purpose is to realize a bonding effective interface, protect an easily oxidized metal interface and ensure the surface smoothness.

Step 3, pasting aphotoresist film 9

Respectively attachingphotoresist films 9 which can be exposed and developed outside the front surface and the back surface of themetal substrate 1 in thestep 1 or outside the front surface and the back surfaceprotective layer 2 of themetal substrate 1 on which theprotective layer 2 is pre-plated in thestep 2, so as to manufacture a subsequent metal circuit pattern, wherein the photoresist films can be dry photoresist films or wet photoresist films; as shown in fig. 4.

Step 4, removing part of the photoresist film on the front surface of themetal substrate 1

Exposing the front surface of themetal substrate 1 which is pasted with thephotoresist film 9 in thestep 3 by using an exposure and development device in a pattern mode, developing and removing part of the photoresist film in the pattern mode to expose aregion 91 where a metal circuit layer is required to be electroplated subsequently on the front surface (including the protective layer 2) of themetal substrate 1; as shown in fig. 5.

Step 5, electroplating themetal circuit layer 3

Instep 4, themetal circuit layer 3 is electroplated in theregion 91 where part of the photoresist film is removed from the front surface of themetal substrate 1, as shown in fig. 6, after the electroplating of themetal circuit layer 3 is completed, a corresponding base island and a corresponding pin are formed on the front surface of the metal substrate.

Removing the non-functional area through an exposure and development function; then, a functional metal circuit is realized through electroplating; the material of themetal circuit layer 3 may be copper, aluminum, nickel, silver, gold, copper silver, nickel gold, nickel palladium gold, etc., and silver is generally preferred; the thickness of themetal circuit layer 3 is 5-20 microns, the electroplating thickness can be changed according to different characteristics, and the electroplating mode can be electrolytic electroplating or chemical deposition.

Step 6, removing the photoresist film

Removing thephotoresist film 9 on the surface of themetal substrate 1, wherein the method for removing thephotoresist film 9 comprises the steps of softening by using chemical liquid medicine and washing by using high-pressure water; eventually as shown in fig. 7.

Thestep 1 to thestep 6 can also purchase the finished frame meeting the design requirements according to the requirements.

Step 7, front surface mounting and ball bonding of themetal substrate 1

Mounting afirst chip 5 on the front surface of themetal substrate 1 by using an adhesive, then performing a ball bonding process, and connecting thefirst chip 5 with peripheral pins by using aninner lead 6; eventually as shown in fig. 8.

Thefirst chip 5 is a circuit control chip and a core chip.

Step 8, front surface plastic package

Performing a first plastic packaging process on themetal substrate 1 to form a frontplastic packaging layer 81, wherein the plastic packaging material is generally epoxy resin;

if the final product is a front embedded chip, the front plastic-sealedlayer 81 is cured and molded, and the surface of the epoxy resin needs to be ground to form a straight surface; if the final product is a back-embedded chip, the frontplastic package layer 81 is cured and molded without surface grinding. Eventually as shown in fig. 9.

Step 9, pasting the photoresist film again

The surface of the product completed instep 8 is then coated with an exposed and developedphotoresist film 9.

The covering region of the resistfilm 9 includes at least the back surface of the metal substrate 1 (including the back surface protective layer 2); preferably, the surface of the frontplastic package layer 81 is also covered; eventually as shown in fig. 10.

Thephotoresist film 9 used instep 9 may be identical to thephotoresist film 9 used instep 3.

Step 10, removing part of the photoresist film on the back of the metal substrate

Exposing the back surface of themetal substrate 1 which is subjected to the operation of pasting thephotoresist film 9 in thestep 9 by using an exposure and development device, developing and removing part of the patterned photoresist film to expose aregion 92 which needs to be etched in the following process on the back surface of the metal substrate; similar to step 4 above; eventually as shown in fig. 11.

The process requirements in this step 10 and the process requirements instep 4 may be completely identical.

Step 11, etching

In the step 10, aregion 92 of the back surface of the metal substrate, from which part of the photoresist film is removed, is subjected to chemical etching, and the chemical etching enters themetal substrate 1 until the vicinity of the frontsurface protection layer 2 to form an embeddedregion 71; the chemical etching also further etches away a portion of the front sideprotective layer 2 on top of the embeddedregion 71, separating the base island and lead regions (when the finished chip frame is selected, the base island and lead regions are typically already separated and may be etched only to form the embedded region 71), as shown finally in fig. 12.

The required shape is designed by adopting the photoresist film scheme, the metal layer in the back non-effective area is removed by adopting chemical etching, the etching speed and the etching depth are controlled by parameters such as the concentration of a liquid medicine, the time and the like, the requirement of the welding thickness at the back can be met by reserving the metal layer at the front, and the original integrated metal layer is etched and disconnected by film pasting design to form the isolation of a functional output terminal;

the surface after etching is accurately electroplated, and a fixed chain speed transmission mechanism is adopted to realize uniform metal coating distribution through a stable current scheme, so that the electroplated surface is smooth, and the subsequent welding operation is convenient.

Step 12 of removing the resistfilm 9

Removing thephotoresist film 9, wherein the method for removing thephotoresist film 9 is realized by softening with chemical liquid medicine and washing with high-pressure water, which is similar to thestep 6; eventually as shown in fig. 13.

Step 13, SMT component pasting

Component mounting is performed in the back-etched area by an SMT process, that is, thesecond chip 7 is mounted in the mountingarea 71.

Thesecond chip 7 is a packaged RLC passive component, which is generally thin and can be embedded in themetal substrate 1.

Common RLC passive devices mainly comprise components such as 01005/0201/0402/0806/1006/1008, and QFN packaging is adopted; if embedded in a package, the package thickness is typically at least 0.35mm thick or more; when embedded in the metal substrate, the thickness is at least 0.15 mm.

Thesecond chip 7 may be provided with a plurality of portions according to the requirement, and the types are different (such as different capacitance values, different resistance values, different inductance values, etc.).

Eventually as shown in fig. 14.

Step 14, back plastic package

Carrying out plastic packaging in the etching area, protecting the components to form a backplastic packaging layer 82, and curing and molding the plastic packaging material which can also adopt epoxy resin; then polishing is carried out, and theprotective layer 2 on the back surface of themetal substrate 1 is exposed; theback protection layer 2 corresponding to the base island region can be used for radiating thefirst chip 5; the backsurface protection layer 2 corresponding to the pin area can be used for assembling external pins of the chip. Eventually as shown in fig. 15.

When the process control is adopted, theback molding layer 82 can also be formed by injection molding in the embeddingregion 71, the plane of theprotective layer 2 lower than the back surface of themetal substrate 1 is lower, that is, after the injection molding is finished, theprotective layer 2 is directly exposed out of themolding layer 82. However, with the arrangement, the injection molding amount is small, and the connection strength is slightly poor; and when the chip is used, the integral shape of the back surface is poor, and the use strength of the chip is influenced.

Furthermore, semi-bright electrotinning can be adopted to form a plating layer protective film on the exposed copper layer region, so as to ensure the terminal to form an oxidation protection effect.

Step 15, cutting and separating

The cutting separation is performed between the products, leaving the desired package as a finished product, i.e. as shown in fig. 2.

The foregoing shows and describes the general principles, essential features, and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are given by way of illustration of the principles of the present invention, and that various changes and modifications may be made without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims

1. The embedded chip packaging process is characterized by comprising the following steps:

step A, front surface mounting and ball bonding of the metal substrate:

step D, removing part of the photoresist film on the back of the chip frame: exposing and developing the back surface of the chip frame which is subjected to the photoresist film pasting operation in the step C by using exposure and development equipment, and removing part of the photoresist film to expose a region which needs to be etched subsequently on the back surface of the chip frame;

step G, SMT paste components: mounting and mounting the components in the back etching area by an SMT process, namely mounting the second chip in the mounting area;

step H, back plastic package: carrying out plastic package on the etching area, and protecting the components to form a back plastic package layer;

polishing is carried out, and the metal on the back of the chip frame is exposed;

2. The embedded chip packaging process of claim 1, wherein the finished chip frame in the step a adopts the following manufacturing steps:

step 1, taking a metal substrate: taking a metal substrate for later use;

and 4, removing part of the photoresist film on the front surface of the metal substrate: exposing and developing the front surface of the metal substrate pasted with the photoresist film in the step 3 by using exposure and development equipment, and removing part of the photoresist film to expose the area of the front surface of the metal substrate which needs to be plated with the metal circuit layer;

step 5, electroplating a metal circuit layer: electroplating a metal circuit layer in the region of the front surface of the metal substrate with part of the photoresist film removed in the step 4, namely forming a corresponding base island and a corresponding pin on the front surface of the metal substrate;

and cleaning and airing to obtain the chip frame.

3. The embedded chip packaging process according to claim 2, wherein step 2 is provided between step 1 and step 3;

step 2, pre-plating a copper material on the surface of the metal substrate 1 to form a protective layer;

the protective layer is made of oxidation-resistant metal material;

and the photoresist film in the step 3 is attached to the outer side of the protective layer.

4. The embedded chip packaging process of claim 1, wherein the etching of step E is to design a desired shape on the photoresist film used in step C; then in step E, removing the metal layer in the back non-effective area by chemical etching;

5. The embedded chip packaging process of claim 4, wherein after the etching of step E is finished, electroplating is performed;

6. The embedded chip packaging process according to claim 1, wherein in the step G, the second chip is a packaged RLC passive component;

7. The embedded chip packaging process of claim 1, wherein in the step H, after the back surface of the metal substrate is exposed, a semi-bright electroplated tin is adopted to form a plating protective film on the exposed metal area.

8. The embedded chip is characterized by being manufactured by the embedded chip packaging process according to any 1 of claims 1-7;

performing plastic packaging in the first chip packaging area and the second chip packaging area to form a plastic packaging layer;

the outer surface of the plastic packaging layer on the second chip loading area side is polished to be not higher than the back plane of the chip frame;

9. The embedded chip of claim 1, wherein the backside of the chip frame is plated with a protective film; and the outer surface of the plastic packaging layer at the second chip loading area side is flush with the outer surface of the back surface of the chip frame.