CN114973993A - Display panel and display device - Google Patents

Abstract

The invention provides a display panel and a display device, wherein the display panel comprises a display area and a non-display area, and the display panel comprises: a first conductive layer including a plurality of gate lines arranged in a longitudinal direction and extending in a transverse direction within the display area; a second conductive layer on the first conductive layer, comprising: a plurality of data lines and a plurality of gate lines arranged on the same layer, wherein the plurality of data lines and the plurality of gate lines are arranged in the display area along the longitudinal extension and the transverse direction; the gate wires are electrically connected with the gate lines through the switching holes; the data chip on film and the grid chip on film are positioned in the non-display area and are respectively and electrically connected with the plurality of data wires and the plurality of grid wires; and a shielding wire is arranged between at least one data wire and the adjacent grid wire. The shielding routing is arranged, so that the twill Mura on the display panel can be effectively improved.

Description

Display panel and display device

Technical Field

The invention relates to the technical field of display, in particular to a display panel and a display device.

Background

With the development of the display industry, the requirement on the size of a panel is higher and higher, as shown in fig. 1, for an AMLED or AMOLED panel, a panel design with three narrow portions and one wide portion is an effective scheme for solving large-size splicing, in this scheme, since the data flip chip and the gate flip chip are located on the same side, the gate trace is inevitably converted from a longitudinal direction to a transverse direction in the display region, so that a regular switching hole inevitably exists in the design, and when the display panel is normally lit, as shown in fig. 2, due to a large lateral capacitance existing between the data line and the gate trace, the jump of the gate trace signal couples the adjacent data line signal, so that the data line voltage is abnormal, and the diagonal Mura is likely to occur.

For this twill Mura, conventional improvement methods are: (1) the distance between the grid routing and the data line is increased, but the scheme is easily limited by the arrangement space; (2) the jump amplitude of the grid line voltage is reduced, or the coupling of the lateral capacitance to the data line signal is reduced by chamfering the grid line signal, wherein the reduction of the grid line voltage can cause poor switching state of a TFT device, so that insufficient charging is caused, the brightness of a panel is reduced, and the chamfering action can provide higher requirements for the IC function of the panel and has poor effect.

Therefore, the existing methods for improving the twill Mura all have corresponding problems, and the display effect of the display panel cannot be improved on the premise of avoiding other display problems.

Disclosure of Invention

The embodiment of the invention provides a display panel and a display device, which aim to solve the problem that the voltage of a grid wire is easy to cause abnormal data line voltage in the jumping process due to the existence of lateral capacitance between the data line and the grid wire, so that diagonal Mura occurs.

The present invention provides a display panel including a display area and a non-display area located at least one side of the display area, the display panel including:

a first conductive layer including a plurality of gate lines arranged in a longitudinal direction and extending in a transverse direction within the display area;

a second conductive layer on the first conductive layer, comprising: a plurality of data lines and a plurality of gate lines arranged on the same layer, wherein the plurality of data lines and the plurality of gate lines are arranged in the display area along the longitudinal extension and the transverse direction; the gate wires are electrically connected with the gate lines through the switching holes; the data chip on film and the grid chip on film are positioned in the non-display area and are respectively and electrically connected with the plurality of data wires and the plurality of grid wires;

and a shielding wire is arranged between at least one data wire and the adjacent grid wire.

In some embodiments of the present invention, a first passivation layer is disposed on the second conductive layer, and the shielding trace is disposed on the first passivation layer.

In some embodiments of the present invention, a height of a lower edge of the shield trace is smaller than a height of an upper edge of the second conductive layer.

In some embodiments of the present invention, a height of a lower edge of the shield trace is greater than a height of a lower edge of the second conductive layer.

In some embodiments of the present invention, a width of the shield trace is smaller than a pitch between the data line and the gate trace in the second conductive layer.

In some embodiments of the present invention, further comprising a substrate base substrate and an interlayer insulating layer, the first conductive layer being on the substrate base substrate, the interlayer insulating layer being between the first conductive layer and the second conductive layer, the first conductive layer further comprising a plurality of gates of a plurality of transistors, the second conductive layer comprising a plurality of sources and a plurality of drains of a plurality of the transistors, the plurality of transistors comprising a first transistor, a second transistor and a third transistor, the first transistor being connected in series with a light emitting element between a first power supply line and a second power supply line, the second transistor being connected in series between the corresponding data line and the gate of the first transistor, the gate of the second transistor being electrically connected to the corresponding gate line, the third transistor being connected in series between the source of the first transistor electrically connected to the light emitting element and the reference power supply line, the grid electrode of the third transistor is used for loading a sensing control signal, and a capacitor is electrically connected between the grid electrode and the source electrode of the first transistor.

In some embodiments of the present invention, a second passivation layer is disposed above the shielding trace, a light shielding layer having a plurality of light shielding portions is disposed above the second passivation layer, and each of the light emitting elements is located between adjacent light shielding portions.

In some embodiments of the present invention, the shielding trace is located in the display region, and the shielding trace includes an indium tin oxide material.

In some embodiments of the present invention, the display device further includes a pixel electrode, the pixel electrode is electrically connected to the corresponding data line through a thin film transistor, and the pixel electrode and the shielding trace are disposed on the same layer.

The invention also comprises a display device comprising any of the display panels.

In the display panel and the display device provided by the embodiment of the invention, the shielding routing is arranged between the data line and the adjacent grid routing, and the arranged shielding routing can effectively reduce the lateral capacitance between the data line and the adjacent grid routing, so that the influence on the voltage of the data line is weakened in the voltage jumping process of the grid routing, the twill Mura defect of the display panel can be effectively improved, and the display effect of the display panel is improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic diagram of a prior art display panel with a design structure of three narrow and one wide;

fig. 2 is a schematic circuit diagram illustrating a gate trace and a data line in a conventional 3T1C circuit according to the present invention;

fig. 3 is a schematic top view of a display panel according to an embodiment of the present invention;

fig. 4 is a schematic cross-sectional structure diagram of a display panel according to an embodiment of the present invention;

FIG. 5 is a schematic cross-sectional view of a display panel according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of a 3T1C circuit corresponding to the display panel according to the embodiment of the present invention;

fig. 7 is a schematic cross-sectional view of a display panel according to an embodiment of the invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive step based on the embodiments of the present invention, are within the scope of protection of the present invention. Furthermore, it should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, and are not intended to limit the present invention. In the present invention, unless otherwise specified, the use of directional terms such as "upper" and "lower" generally means upper and lower in the actual use or operation of the device, particularly in the orientation of the figures of the drawings; while "inner" and "outer" are with respect to the outline of the device.

Specifically, referring to fig. 3 and 4, the display panel includes adisplay area 10 and anon-display area 20 located on at least one side of thedisplay area 10, and the display panel includes: a firstconductive layer 100 including a plurality ofgate lines 110, the plurality ofgate lines 110 being arranged in a longitudinal direction and extending in a transverse direction in thedisplay area 10; a secondconductive layer 200 on the firstconductive layer 100, comprising: a plurality ofdata lines 210 and a plurality ofgate traces 220 disposed at the same layer, wherein the plurality ofdata lines 210 and the plurality ofgate traces 220 are arranged along the longitudinal extension and the transverse direction in thedisplay region 10; thegate traces 220 are electrically connected to thegate lines 110 through vias; and a data chip on film and a gate chip on film located in thenon-display area 10 and electrically connected to the plurality ofdata lines 210 and the plurality ofgate lines 220, respectively; ashielding trace 230 is disposed between at least onedata line 210 and theadjacent gate trace 220.

As shown in fig. 3, in the display panel, there are a plurality of thedata lines 210 and thegate traces 220 arranged transversely, and a plurality of thegate lines 110 arranged longitudinally, in this embodiment, since the data chip on film (D-COF) and the gate chip on film (G-COF) are located at the same side of the display panel, so that a plurality of thegate lines 110 arranged in a longitudinal direction on the display panel and extending in a transverse direction cannot be directly connected to the gate flip-chip film, and therefore, in the present embodiment, a plurality ofgate lines 110 are electrically connected to a plurality ofgate traces 220 by providing a plurality of vias, thegate traces 220 and thedata lines 210 are located at the same layer, and a plurality of thegate traces 220 and thedata lines 210 are alternately arranged, and further electrically connected to the gate chip on film at one side of the display panel through a plurality ofgate traces 220.

It can be understood that, in the embodiment, the number of the data flip-chip films and the gate flip-chip films on the same side of the display panel is not limited to that shown in fig. 3, and in the actual application process, the number of the data flip-chip films and the gate flip-chip films corresponds to the actual requirement.

Further, since a plurality ofgate traces 220 are distributed on the display panel, and thegate traces 220 and theadjacent data lines 210 are located on the same layer, a lateral capacitance exists between thedata lines 210 and thegate traces 220, and according to the content of the background art of the present invention, the voltage of thedata lines 210 is affected by the presence of the lateral capacitance, so that the display panel is prone to have a twill Mura problem.

In order to solve the twill Mura appearing in the display panel, in this embodiment, theshielding trace 230 is disposed between thedata line 210 and theadjacent gate trace 220, and theshielding trace 230 reduces a direct area of the lateral capacitor, so that voltage interference of the lateral capacitor to thedata line 210 can be effectively reduced, thereby reducing the problem of the twill Mura appearing in the display panel and improving the display effect of the display panel.

It should be noted that, in this embodiment, as shown in fig. 3, two gate flip-chips are disposed on one side of the display panel, the gate flip-chips are disposed on two sides of the data flip-chip, and because there are two gate flip-chips, asingle gate line 110 is correspondingly connected to twogate traces 220 through a via hole, it can be understood that asingle gate line 110 is correspondingly connected to twogate traces 220, and the twogate traces 220 are connected to different positions of thegate line 110, which is beneficial for the signal of the gate flip-chip to be transmitted on thegate line 110.

Furthermore, according to the related simulation test, the result shows that the lateral capacitance can be sharply reduced by the scheme adopted in this embodiment, the voltage variation of thegate trace 220 is reduced from the original 10% to 2.1%, and further the coupling of the signal jump of thegate trace 220 to the signal of theadjacent data line 210 is reduced, so that the problem of the diagonal Mura of the display panel is significantly improved.

Optionally, afirst passivation layer 300 is disposed on the secondconductive layer 200, and theshielding trace 230 is disposed on thefirst passivation layer 300.

In this embodiment, thefirst passivation layer 300 disposed on the secondconductive layer 200 can effectively protect the secondconductive layer 200, so as to prevent the material of the secondconductive layer 200 from being corroded by water or oxygen in the air.

Optionally, the height of the lower edge of theshield trace 230 is smaller than the height of the upper edge of the secondconductive layer 200.

In this embodiment, theshielding trace 230 is used to reduce a facing area between thedata line 210 and thegate trace 220, and the height of the lower edge of theshielding trace 230 is set to be smaller than the height of the upper edge of the secondconductive layer 200, so that theshielding trace 230 can effectively occupy a space between a part of thedata line 210 and thegate trace 220, and thus, an influence of a lateral capacitance formed by thedata line 210 and thegate trace 220 on the voltage of thedata line 210 can be reduced.

Optionally, the height of the lower edge of theshield trace 230 is greater than the height of the lower edge of the secondconductive layer 200.

It can be understood that, theshielding trace 230 is disposed on thefirst passivation layer 300, and in the preparation process, since theshielding trace 230 is recessed in the deposition process, the height of the lower edge of theshielding trace 230 is smaller than the horizontal height of the side of the secondconductive layer 200 contacting with thefirst passivation layer 300, so that the lateral capacitance formed by thedata line 210 and thegate trace 220 can be reduced, and therefore, the height of the lower edge of theshielding trace 230 is generally greater than the height of the lower edge of the secondconductive layer 200.

Further, the width of theshield trace 230 is smaller than the distance between thedata line 210 and thegate trace 220 in the secondconductive layer 200.

In this embodiment, theshielding trace 230 is used to reduce a facing area between thedata line 210 and thegate trace 220, and if the width of theshielding trace 230 is greater than a distance between thedata line 210 and thegate trace 220, a part of theshielding trace 230 is disposed above thedata line 210 and thegate trace 220, which is likely to cause other display problems, and detailed description is not provided in this application.

Further, as shown in fig. 5, the display panel further includes asubstrate 400 and aninterlayer insulating layer 500, the firstconductive layer 100 is located on thesubstrate 400, theinterlayer insulating layer 500 is located between the firstconductive layer 100 and the secondconductive layer 200, the firstconductive layer 100 further includes a plurality of gates of a plurality of transistors, the secondconductive layer 200 includes a plurality of sources and a plurality of drains of the plurality of transistors, as shown in fig. 6, fig. 6 is a schematic structural diagram of a 3T1C circuit corresponding to the display panel according to an embodiment of the present invention, the plurality of transistors include a first transistor (T1), a second transistor (T2) and a third transistor (T3), the first transistor and the light emitting element are connected in series between a first power line (VDD) and a second power line (VSS), the second transistor is connected in series between the corresponding Data line (Data) and the gate of the first transistor, the gate of the second transistor is electrically connected to the corresponding gate line (Scan), the third transistor is connected in series between the source of the first transistor electrically connected to the light emitting element (LED) and the reference power line (Vref), the gate of the third transistor is used for loading a sensing control signal (sense), and a capacitor (C1) is further electrically connected between the gate and the source of the first transistor.

Optionally, as shown in fig. 7, asecond passivation layer 600 is disposed above theshielding trace 230, alight shielding layer 700 having a plurality oflight shielding portions 710 is disposed above thesecond passivation layer 600, and each light emitting element is located between adjacentlight shielding portions 710.

In this embodiment, thesecond passivation layer 600 can protect theshielding trace 230 to prevent theshielding trace 230 from being corroded by moisture and oxygen in the air, in addition, thelight shielding layer 700 is disposed above thesecond passivation layer 600, thelight shielding layer 700 has a plurality oflight shielding portions 710, the light emitting elements are located between the adjacentlight shielding portions 710, and thelight shielding portions 710 can prevent light emitted by the adjacent light emitting elements from interfering with each other, so that the display effect of the display panel is improved.

Optionally, theshielding trace 230 is located in thedisplay area 10, and theshielding trace 230 includes an indium tin oxide material.

It can be understood that the ito material is used as a common material of the metal layer of the display panel, and the ito material is used for theshielding traces 230, which is beneficial to the fabrication of the display panel.

Further, the display device further includes a pixel electrode, the pixel electrode is electrically connected to thecorresponding data line 210 through a thin film transistor, and the pixel electrode and theshielding trace 230 are disposed on the same layer.

In this embodiment, when the liquid crystal display is applied to an LCD, the structure of the LCD includes, in addition to the gate electrode connected to thegate line 110 and the drain electrode connected to thedata line 210, the pixel electrode, which is connected to the source electrode of the tft, and usually when the pixel electrode layer is prepared, the metal of other parts except the pixel electrode layer needs to be etched away, in this embodiment, the pixel electrode and theshielding trace 230 are disposed on the same layer, so that, on one hand, the originally etched redundant metal material is fully utilized and used for preparing theshielding trace 230, and the influence of the lateral capacitance existing between thedata line 210 and theadjacent gate trace 220 on the voltage of thedata line 210 can be effectively reduced, so as to improve the diagonal Mura of the display panel and improve the display effect of the display panel, and on the other hand, in the preparation process, the pixel electrode and theshielding wiring 230 are manufactured at one time, so that the process is saved, an extra mask is not required to be manufactured, and the manufacturing cost is reduced.

The invention also comprises a display device comprising any of the display panels.

It is understood that the display device includes a movable display device (e.g., a notebook computer, a mobile phone, etc.), a fixed terminal (e.g., a desktop computer, a television, etc.), a measuring device (e.g., a sports bracelet, a temperature measuring instrument, etc.), and the like.

The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for those skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims (10)

1. A display panel including a display area and a non-display area on at least one side of the display area, the display panel comprising:

a first conductive layer including a plurality of gate lines arranged in a longitudinal direction and extending in a transverse direction within the display area;

a second conductive layer on the first conductive layer, comprising: a plurality of data lines and a plurality of gate lines arranged on the same layer, wherein the plurality of data lines and the plurality of gate lines are arranged in the display area along the longitudinal extension and the transverse direction; the gate wires are electrically connected with the gate lines through the switching holes; the data chip on film and the grid chip on film are positioned in the non-display area and are respectively and electrically connected with the plurality of data wires and the plurality of grid wires;

and a shielding wire is arranged between at least one data wire and the adjacent grid wire.

2. The display panel of claim 1, wherein a first passivation layer is disposed on the second conductive layer, and wherein the shielding trace is disposed on the first passivation layer.

3. The display panel of claim 2, wherein a height of a lower edge of the shield trace is less than a height of an upper edge of the second conductive layer.

4. The display panel of claim 3, wherein a height of a lower edge of the shield trace is greater than a height of a lower edge of the second conductive layer.

5. The display panel according to claims 2 to 4, wherein the width of the shielding trace is smaller than the pitch between the data line and the gate trace in the second conductive layer.

6. The display panel according to claim 5, further comprising a substrate base substrate and an interlayer insulating layer, wherein the first conductive layer is provided on the substrate base substrate, the interlayer insulating layer is provided between the first conductive layer and the second conductive layer, the first conductive layer further comprises a plurality of gates of a plurality of transistors, the second conductive layer comprises a plurality of sources and a plurality of drains of a plurality of the transistors, the plurality of transistors comprises a first transistor, a second transistor, and a third transistor, the first transistor is connected in series with a light-emitting element between a first power supply line and a second power supply line, the second transistor is connected in series between the corresponding data line and the gate of the first transistor, the gate of the second transistor is electrically connected to the corresponding gate line, and the third transistor is connected in series between the source of the first transistor, which is electrically connected to the light-emitting element, and the reference power supply line The gate of the third transistor is used for loading a sensing control signal, and a capacitor is electrically connected between the gate and the source of the first transistor.

7. The display panel according to claim 6, wherein a second passivation layer is disposed over the shielding traces, a light shielding layer having a plurality of light shielding portions is disposed over the second passivation layer, and each of the light emitting elements is located between adjacent light shielding portions.

8. The display panel of claim 1, wherein the shield trace is located in the display area, and wherein the shield trace comprises an indium tin oxide material.

9. The display panel of claim 8, further comprising a pixel electrode electrically connected to the corresponding data line through a thin film transistor, wherein the pixel electrode and the shielding trace are disposed on the same layer.

10. A display device comprising the display panel according to any one of claims 1 to 9.

Images