CN114913823A - Pixel circuit based on double-gate transistor and driving method thereof - Google Patents

Abstract

The invention discloses a pixel circuit based on a double-gate transistor and a driving method thereof, wherein the pixel circuit based on the double-gate transistor comprises a liquid crystal pixel capacitor Cls, a transistor T1 and a double-gate transistor T2, one end of the liquid crystal pixel capacitor Cls is connected with a reference voltage of a liquid crystal screen, the other end of the liquid crystal pixel capacitor Cls is connected with a drain electrode of the double-gate transistor T2 and is coupled to a first synchronous signal Vst1, one grid electrode of the double-gate transistor T2 is connected to a second synchronous signal Vst2, the other grid electrode of the double-gate transistor T2 is coupled with a transistor T1, and the transistor T1 is connected with a grid electrode driver and a source electrode driver of the liquid crystal screen. The invention can realize the synchronous work of the liquid crystal pixels only by two transistors and one liquid crystal capacitor, and effectively improves the phenomena of color confusion and picture tearing caused by the time delay from the first line to the last line; in addition, the circuit provided by the invention has few components, controllable process and controllable cost, and has high aperture opening ratio and light transmittance due to small area, thereby having good application value.

Description

Pixel circuit based on double-gate transistor and driving method thereof

Technical Field

The invention belongs to the technical field of liquid crystal display, and particularly relates to a pixel circuit based on a double-gate transistor and a driving method thereof.

Background

The display principle of a common liquid crystal screen is as follows: after each line of thin film transistors in the display device of the liquid crystal screen are opened by the grid circuit, the source circuit is responsible for charging, in the period, the backlight source on the back of the liquid crystal screen is responsible for providing light source illumination, and each pixel of the liquid crystal is responsible for the passing of light rays and the quantity of the passing light rays, so that a color image is formed under the coordination of the color filter; it features its color filter and always bright backlight source.

With the progress of technology, the principle of time-sequential field display liquid crystal has been proposed. The basic logic is that a liquid crystal screen with single color and only gray scale control is adopted, and color display is realized by matching with backlight sources with different colors and a method of mixing colors in time. Generally, three light sources of RGB are turned on in a gapless sequence to decompose an image into three sub-pictures of red, green and blue, when a red image is output, a red light is turned on, a liquid crystal pixel controls a gray scale to allow a certain proportion of red light to pass through, when a green color is required, a green light is turned on, and a liquid crystal pixel controls a gray scale to allow a certain proportion of green light to pass through. The same is true for blue. When the action of the liquid crystal pixel and the action of the backlight source can realize a higher switching speed, for example, the liquid crystal pixel realizes the refreshing of 180Hz, the red, green and blue backlight source also realizes the refreshing coordination of 180Hz, so that each field of picture can control one color, all red, green and blue light coordination is completed for every three fields of pictures, and each three fields of pictures form a frame of color image. For a refresh rate of 180Hz, the timing matched refreshing of the light source and the liquid crystal pixel can realize a color picture of 60 Hz.

In practice, however, since the liquid crystal is turned on and off for a certain period of time, the liquid crystal is driven to display by turning on the liquid crystal pixel charging circuit for one line and one line, and then the other circuits are charged again. After the charging is finished, the liquid crystal is twisted to realize the specific execution of light passing and the like. As the resolution of the displayed image is higher and higher, the time spent in scanning from the first row to the last row is longer and longer, and the requirement on a driving circuit is higher and higher; taking 1080P as an example, 1080 line scans need to be completed in each subframe time, so each line time is short, and after all scans are completed, the backlight is turned on. It can be seen that the time left for the backlight drive to be on is very small in each sub-frame.

Such as: under 180Hz, each frame is 5.6 milliseconds; when the charging of the first line is completed and the charging is completed at the last time, if 5.4 milliseconds is needed, the time needed for people to watch the image of the first line is 5.4 milliseconds, and the last line under the picture is displayed, so that the tearing and the dislocation of the image can occur.

This problem is more serious if the refresh rate is higher, the picture backlight display color of each sub-field is different for products if field sequential display is required; ifrow 1 is displaying a certain color, such as red, then 5.4 milliseconds are needed to charge and refresh to the last row, 1080, then 0.2 milliseconds later, the first row has already started displaying the next field color, such as blue; the last row is also in red; of the scene (c). For the backlight, the display is divided into time and area for distinguishing, and this problem will cause great design difficulty and cost increase.

Disclosure of Invention

In order to solve the above problems, the present invention provides a pixel circuit based on a dual-gate transistor, which can implement the synchronous operation of liquid crystal pixels on the premise that the existing liquid crystal pixels scan the display content of an input image through the cooperation of a gate and a source, thereby effectively improving the phenomena of color confusion and image tearing caused by the time delay from the first line to the last line; in addition, the device has few electrical components, and has the effects of saving circuit area and improving aperture opening ratio.

Another object of the present invention is to provide a driving method of a pixel circuit based on a dual gate transistor.

The technical scheme adopted by the invention is as follows:

a pixel circuit based on a double-gate transistor comprises a liquid crystal pixel capacitor Cls, a transistor T1 and a double-gate transistor T2, wherein one end of the liquid crystal pixel capacitor Cls is connected with a reference voltage of a liquid crystal screen, the other end of the liquid crystal pixel capacitor Cls is connected with a drain electrode of the double-gate transistor T2, a source electrode of the double-gate transistor T2 is coupled to a first synchronous signal Vst1, one gate electrode of the double-gate transistor T2 is connected to a second synchronous signal Vst2, and the other gate electrode of the double-gate transistor T1 is coupled with the transistor T1.

Preferably, the transistor T1 is a double gate transistor.

Preferably, when the transistor T1 is a double-gate transistor, both gates of the transistor T1 are connected to Vscan.

Preferably, when the transistor T1 is a double-gate transistor, one gate of the transistor T1 is connected to Vscan, and the other gate is connected to the firstsynchronization signal Vst 1.

Preferably, when the transistor T1 is a double-gate transistor, one gate of the transistor T1 is connected to Vscan, and the other gate is connected to the other gate of the double-gate transistor T2.

Preferably, when the transistor T1 is a double-gate transistor, one gate of the transistor T1 is connected to Vscan, and the other gate is connected to one gate of the double-gate transistor T2.

Preferably, when the transistor T1 is a double-gate transistor, one gate of the transistor T1 is connected to Vscan, and the other gate is connected to the liquid crystal pixel capacitance Cls.

Preferably, each pixel is at least connected to a global common electrode line for controlling all pixels, and the global common electrode line is arranged in a manner that: arranged in a lateral gate direction, arranged in a longitudinal source direction, or arranged crosswise.

Preferably, two adjacent rows or two adjacent columns of the global common electrode line of the pixel circuit can share one electrode line with the same property, so as to reduce the occupation of the opening area.

A driving method of a pixel circuit based on a double-gate transistor applies the pixel circuit based on the double-gate transistor, and is implemented according to the following steps:

s1, charging: charging the liquid crystal pixel capacitor Cls through a high level, and presetting the liquid crystal pixel capacitor Cls to the high level;

s2, second-order programming link: discharging the liquid crystal pixel capacitor Cls to a working voltage required by the liquid crystal pixel to display an image;

s3, first order programming link: at the operating voltage of S2, the charge delivered from the external control unit is received and saved by the transistor T1 for the display of the next frame image.

Preferably, in S2, the discharging of the liquid crystal pixel capacitor Cls to the working voltage required by the liquid crystal pixel to display the image is specifically:

the first synchronization signal Vst1 and the second synchronization signal Vst2 cooperate to turn on the dual-gate transistor T2, thereby discharging the liquid crystal pixel capacitor Cls.

Preferably, the discharge time of the liquid crystal pixel capacitor Cls depends on the matching time of the high and low levels of the first synchronization signal Vst1 and the secondsynchronization signal Vst 2.

Preferably, when the liquid crystal pixel capacitor Cls is discharged, the discharge capability of the dual gate transistor T2 depends on the charge stored in S3.

Preferably, after the second order programming segment of S2, the backlight is turned on and first order programming is started simultaneously.

Preferably, after the second-order programming step of S2, the backlight is turned on, and after buffering, the first-order programming is performed, wherein the time for starting the first-order programming is correspondingly delayed but not extended to the second-order programming step of the next frame.

Preferably, in the charging link of S1, all liquid crystal pixels constituting the liquid crystal panel are preset to a high level at one time and simultaneously by a high level.

Preferably, in the second-order programming step of S2, the second-order programming of all pixels constituting the liquid crystal panel is performed simultaneously and at a time.

Preferably, the method further comprises: the backlight source of the liquid crystal display is sequentially turned on and off, and the first-order programming process is sequentially carried out in the first-order programming stage, so that the assembly line type driving logic is formed.

Preferably, when the first and second synchronization signals Vst1 and Vst2 are square waves, the operating voltage Vpx ranges from 0 ≦ Vpx ≦ VH, where VH is the voltage at which the liquid crystal pixel capacitance is preset to the highest level.

Preferably, when the first and second synchronization signals Vst1 and Vst2 are ramp waves, the dual gate transistor maintains a high level state of the liquid crystal pixel capacitance for a certain time and then turns on, discharging the liquid crystal pixel capacitance to a zero level.

Preferably, when the operating voltage is at a high level, a time for which the high level is maintained depends on the charge in the S3 and a parameter of a ramp wave.

Compared with the prior art, when the liquid crystal display panel is used, firstly, the liquid crystal pixel capacitor Cls is charged through a high level, and the liquid crystal pixel is preset to be in a high level state; programming the charges to realize discharge so that the charges reach the working voltage required by the liquid crystal pixel to display the image; finally, while maintaining the operating voltage of the liquid crystal pixel, the transistor T1 receives and saves the electric charge transmitted from the external control unit at the same time, and the electric charge is used for displaying the next frame image;

the liquid crystal pixel unit is preset to a high level and then discharged to a level required by displaying an image, so that the speed is higher than that of charging from a low level to a high level; secondly, the ghost phenomenon of the liquid crystal capacitor under a specific picture is eliminated by presetting each frame of picture to a high level; meanwhile, when the current image is displayed, the electric quantity required by the next frame of image display is programmed and charged, because the programming and charging at the moment need to be sequentially charged row by row, and the time is very long, the requirement on the driving capability of an external grid driver and a source driver is greatly reduced by the way of simultaneously storing the electric quantity data of the current image display and the next frame of image in advance, the time for displaying backlight illumination of the image is also greatly prolonged, the problem that the time from the first row to the last row is very long in the grid scanning driving mode of the liquid crystal display, the brightness is insufficient due to the illumination time of a compressed backlight source, or the backlight source time is prolonged in the traditional scanning mode continuously is solved, and the phenomena of color confusion and image tearing can be caused;

more importantly: the invention can realize the functions only by two transistors and one capacitor, has controllable volume, controllable process and controllable cost, ensures high aperture opening ratio and light transmittance due to small volume and has good application value.

Drawings

Fig. 1 is a circuit diagram of a pixel circuit based on a dual gate transistor according toembodiment 1 of the present invention;

fig. 2a is a diagram of a first connection mode of the transistor T1 when the transistor T1 is a double-gate transistor in the pixel circuit based on the double-gate transistor according toembodiment 1 of the present invention;

fig. 2b is a diagram of a second connection mode of the transistor T1 when the transistor T1 is a double-gate transistor in the pixel circuit based on the double-gate transistor according toembodiment 1 of the present invention;

fig. 2c is a diagram of a third connection mode of the transistor T1 when the transistor T1 is a double-gate transistor in the pixel circuit based on the double-gate transistor according toembodiment 1 of the present invention;

fig. 2d is a diagram of a fourth connection mode of the transistor T1 when the transistor T1 is a double-gate transistor in the pixel circuit based on the double-gate transistor according toembodiment 1 of the present invention;

fig. 2e is a diagram of a fifth connection mode of the transistor T1 when the transistor T1 is a double-gate transistor in the pixel circuit based on the double-gate transistor according toembodiment 1 of the present invention;

fig. 3a is a cross-sectional view of a dual-gate transistor T2 in a pixel circuit based on the dual-gate transistor provided inembodiment 1 of the present invention;

fig. 3b is a schematic representation of a double-gate transistor T2 in a pixel circuit based on the double-gate transistor according toembodiment 1 of the present invention;

fig. 3c is a schematic diagram of the transfer characteristic of the dual-gate transistor T2 in the pixel circuit based on the dual-gate transistor according toembodiment 1 of the present invention;

fig. 4 is a flowchart of a driving method of a dual-gate transistor based pixel circuit according toembodiment 2 of the present invention;

fig. 5a is a timing diagram of a voltage-bootstrapped digital modulation method in a driving method of a pixel circuit based on a dual-gate transistor according toembodiment 2 of the present invention;

fig. 5b is a timing diagram of an analog modulation method in the driving method of the pixel circuit based on the dual gate transistor according toembodiment 2 of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

In the description of the present invention, it is to be understood that the terms "vertical", "lateral", "longitudinal", "front", "rear", "left", "right", "upper", "lower", "horizontal", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are merely for convenience of description of the present invention, and do not mean that the device or element referred to must have a specific orientation or position, and thus, should not be construed as limiting the present invention.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; may be directly connected or indirectly connected through an intermediate. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

In the description of the present invention, it should be further noted that the bottom gate control and the top gate control in the text are opposite, and the source and the drain are also opposite; the person skilled in the art can carry out the adjustment according to conventional means;

in the description of the present invention, for different circuits, the names of the electrodes corresponding to the global voltages are different in order to take care of the habits of those skilled in the art under different driving methods and calculation methods;

in the description of the invention, the LTPS process and the expression habit are adopted, however, the method in the invention is also applicable to the liquid crystal screen produced by the technical process of adopting different liquid crystal screens such as IGZO, a-Si, OTFT and the like;

the invention is on the one hand to solve the problem under the field sequential color implementation method, on the other hand, can also be applied to the traditional liquid crystal screen that the backlight is always bright;

the field sequential display name used in the present invention is also called a time sequence method, a color sequence method, or the like in various cases.

Example 1

Embodiment 1 of the present invention provides a pixel circuit based on a dual-gate transistor, as shown in fig. 1, which includes a liquid crystal pixel capacitor Cls, a transistor T1, and a dual-gate transistor T2, wherein one end of the liquid crystal pixel capacitor Cls is connected to a reference voltage of a liquid crystal panel, and the other end is connected to a drain of the dual-gate transistor T2, a source of the dual-gate transistor T2 is coupled to a first synchronization signal Vst1, one gate of the dual-gate transistor T2 is connected to a second synchronization signal Vst2, and the other gate is coupled to the transistor T1; the gate of the transistor T1 is connected with the gate driver of the liquid crystal screen, and the source is connected with the source driver of the liquid crystal screen;

thus, with the above structure, the liquid crystal pixel capacitor Cls is charged at a high level, and the liquid crystal pixel is preset to a high level state; then the double-gate transistor T2 is conducted to program the charges to realize discharging, so that the charges reach the working voltage required by the liquid crystal pixel to display images; finally, the electric charge supplied from the external control unit is received and held by the transistor T1 for display of the next frame image while the charge voltage of the liquid crystal pixel is maintained; by the method, the phenomena of color confusion and picture tearing caused by overlong non-current frame brightness due to insufficient brightness caused by long time from the first line to the last line and the fact that the backlight source is opened when the liquid crystal pixels are not charged to current frame data under the traditional liquid crystal display grid scanning driving mode are effectively improved; more importantly: the function can be realized by only two transistors (the transistor T1 and the double-gate transistor T2) and one capacitor (the liquid crystal pixel capacitor Cls) in the embodiment, the size is controllable, the process is controllable, the cost is controllable, the aperture opening ratio and the light transmittance are high due to small size, the backlight illumination time is long, and the backlight illumination device has good application value.

In a specific embodiment:

the transistor T1 is a double-gate transistor.

For better opening effect, when the transistor T1 is a double-gate transistor, the transistor T1 is connected in five ways:

first, when the transistor T1 is a double-gate transistor, both gates of the transistor T1 are connected to Vscan, as shown in fig. 2 a;

second, when the transistor T1 is a dual gate transistor, one gate of the transistor T1 is connected to Vscan, and the other gate is connected to the first synchronization signal Vst1, as shown in fig. 2 b;

thirdly, when the transistor T1 is a double-gate transistor, one gate of the transistor T1 is connected to Vscan, and the other gate is connected to the other gate of the double-gate transistor T2, as shown in fig. 2 c;

fourth, when the transistor T1 is a dual-gate transistor, one gate of the transistor T1 is connected to Vscan, and the other gate is connected to one gate of the dual-gate transistor T2, as shown in fig. 2 d;

fifth, when the transistor T1 is a dual gate transistor, one gate of the transistor T1 is connected to Vscan, and the other gate is connected to the liquid crystal pixel capacitor Cls, as shown in fig. 2 e;

of the five connection methods, the third connection method is preferable, and this connection method has an effect of enhancing feedback, specifically:

when a higher-voltage Vdata signal needs to be transmitted, the auxiliary gate voltage is also a high-level voltage, which reduces the Vth value of the transistor T1 and improves the programming speed;

when a Vdata signal with a lower potential is transmitted, the auxiliary gate potential is a low level voltage, which makes the Vth value of the transistor T1 higher, so that the voltage programmed into the gate node of the dual-gate transistor T2 is better maintained;

here, Vscan is a gate driving voltage generated by the external gate driver, Vdata is a source driving voltage generated by the external source driver, and Vth is a threshold voltage of the transistor T1.

In a specific embodiment:

the pixel circuit further comprises at least two global common electrode lines for controlling all pixels, and the global common electrode lines are arranged in a mode that: arranged along a transverse gate direction, arranged along a longitudinal source direction, or arranged crosswise;

when the pixel circuit is arranged with the global common electrode wires, the global common electrode wires between two adjacent rows or two adjacent columns of liquid crystal pixels can be shared, so that the arrangement of one line can be reduced, and the aperture ratio of the liquid crystal screen is increased;

specifically, when there are two global common electrode lines, which are Vst1 and Vst2, because of the global circuit, two adjacent rows of scan lines or two adjacent columns of data lines can share the global circuit, so that the occupied space can be reduced, and the aperture ratio can be increased.

In order to reduce space occupation, reduce resistance-capacitance load of the whole circuit design and improve transmission capability in the specific circuit design and liquid crystal pixel design process, logic of two adjacent lines of common electrode wires is adopted;

therefore, each liquid crystal pixel applying the circuit is connected with a plurality of public global electrode wires, the electrode wires are arranged in parallel or in a crossed way in the liquid crystal screen according to lines or columns, and two adjacent lines of liquid crystal pixels, namely an upper line, a lower line, a left line and a right line, can share one same public electrode wire, so that one public electrode wire can be saved according to every two lines or every two lines, a group of electrode wires are reduced, a face machine occupied by wiring can be reduced, and the aperture opening ratio of the liquid crystal screen is increased.

More specifically, a cross-sectional view of the double-gate transistor T2 is shown in fig. 3a, wherein Glass is a liquid crystal panel Glass substrate layer; s is a transistor source; d is a transistor drain; TG is a top gate and a transistor top gate signal line; SHIELDING METAL as a protective layer, defined to act as a bottom gate; the LTPS represents a semiconductor layer under the LTPS process;

the LTPS active layer is controlled by the bottom gate insulating layer to form a first gate control, i.e., bottom gate control. And because the LTPS active layer is protected by the SiOx dielectric layer on the back, a top gate control structure can be designed to form a second gate control structure together with the LTPS active layer, namely top gate control. When the voltage of the top gate control is different, a double-threshold voltage mode can be formed, and a liquid crystal LCD display pixel circuit under two-stage programming charging logic can be formed.

More specifically, a symbolic diagram of the double-gate transistor T2 is shown in fig. 3b, wherein S is the transistor source; d is a transistor drain; TG and Shield Metal represent two gates, respectively;

more specifically, the transfer characteristic of the double-gate transistor T2 is shown in FIG. 3c, where IDS is the current between the source and the drain, and VTG-VS is the voltage between the source and the gate.

The beneficial effects of this embodiment are as follows:

firstly, all liquid crystal pixels of the liquid crystal screen can synchronously carry out normal display;

secondly, through the design of the double-gate transistor, the internal design of the liquid crystal pixel is obviously changed, the lighttight area occupied by the capacitor is saved, the aperture opening ratio is improved, and the brightness is favorably improved;

in addition, in the embodiment, the gate circuit and the source circuit are matched in the normal display stage, and data used for display is programmed in, so that a driving mode of liquid crystal screen gate scanning in a traditional mode can be adopted, and the driving mode has the advantages of long time from the first row to the last row and low requirement on driving capability;

in addition, a black field with a certain time is arranged in each frame of picture and is alternated with a light field lighted by backlight, so that the phenomenon of smear is improved, and the picture quality is improved;

through specific buffer design logic, for liquid crystal screens manufactured by different processes, due to different TFT processes and different leakage current capabilities, the buffer design logic well reduces the situations that the leakage current causes excessive capacitor voltage drop, part of programming data is inaccurate, and display is inaccurate;

in addition, the functions can be realized only by two transistors and one capacitor, the size is controllable, the process is controllable, the cost is controllable, and the aperture opening ratio and the light transmittance are high due to small size, so that the high-power-factor LED light source has good application value.

Example 2

Embodiment 2 of the present invention provides a driving method for a pixel circuit based on a dual-gate transistor, which applies the pixel circuit based on the dual-gate transistor described inembodiment 1, as shown in fig. 4, and is specifically implemented according to the following steps:

s1, presetting a charging link: charging the liquid crystal pixel capacitor Cls through a high level, and presetting the liquid crystal pixel capacitor Cls to the high level; the method specifically comprises the following steps:

inputting high level through a global common electrode wire to synchronously preset all liquid crystal pixel capacitors Cls forming the liquid crystal screen to a high level state at one time;

s2, a second-order programming link: discharging the liquid crystal pixel capacitor Cls to a working voltage required by the liquid crystal pixel to display an image; the method comprises the following specific steps:

through the cooperation of the first synchronizing signal Vst1 and the second synchronizing signal Vst2, the double-gate transistor T2 is turned on, and the liquid crystal pixel capacitor Cls is discharged;

it should be noted that: because the first synchronous signal and the second synchronous signal are global voltages shared by the whole liquid crystal screen, the second-order programming links of all pixels forming the liquid crystal screen are synchronously completed at one time;

s3, first-order programming link: at the operating voltage of S2, the transistor T1 receives and saves the electric charge transmitted from the external control unit for displaying the next frame image; the method specifically comprises the following steps:

the whole liquid crystal screen is charged from the first line to the last line in sequence, a gate driver and a source driver of the liquid crystal screen are matched with each other, and first-order programming charging is carried out on each liquid crystal pixel from the first line to the last line;

the charging data is related to the displayed image and is controlled by a source driver.

The liquid crystal pixels are sequentially turned on row by row and controlled by a gate driver.

More specifically:

in S2, when the liquid crystal pixel capacitor Cls is discharged, the discharging time depends on the time when the first and second synchronization signals Vst1 and Vst2 are shifted in high and low levels;

the first sync signal Vst1 goes high for a first time and the second sync signal Vst2 goes high for a second time, which is longer than the first time, and then the discharge is started, and the discharge time is a time difference between the second time and the first time.

When the liquid crystal pixel capacitor Cls is discharged, the discharge capability thereof depends on the charge stored in S3, that is: the more charge coupled to the gate of transistor T2, the stronger the discharge capability and the lower the voltage to which the liquid crystal pixel capacitance Cls is pulled; on the contrary, the voltage level of the liquid crystal pixel capacitor Cls is higher, and the discharge capability of the liquid crystal pixel capacitor Cls is the conduction capability of the double-gate transistor and is determined by the working characteristics of the double-threshold voltage mode.

The second-order programming link in the step S2 has two forms, which are voltage bootstrap digital programming and analog programming respectively;

in the analog programming method, when the first and second synchronization signals Vst1 and Vst2 are square waves, the range of the operating voltage Vpx is 0-V_px VH, where VH is the voltage at which the liquid crystal pixel capacitance is preset to the highest level.

In the digital programming method, when the first and second synchronization signals Vst1 and Vst2 are ramp waves, the operating voltage is high, but the time for which the operating voltage is maintained is determined by the programming parameters, which depend on the charge in S3 and the ramp wave parameters.

More specifically:

in the first-order programming link of S3, the entire lcd panel sequentially performs charging operations from the first line to the last line, the gate driver and the source driver of the lcd panel cooperate with each other, and each liquid crystal pixel is first-order programmed and charged from the first line to the last line; the charging data is related to the displayed image and is controlled by a source driver.

The method further comprises the following steps: the backlight source of the liquid crystal display is sequentially turned on and off, and the first-order programming process is sequentially carried out in the first-order programming stage, so that the pipelined driving sequential logic is formed.

In this embodiment, two types of programming links are respectively described by the following specific examples, and the voltage bootstrap type digital programming operation timing sequence is shown in fig. 5 a:

in fig. 5a, P1 pre-charge is an S1 preset charging link, in which the first synchronization signal Vst1 and the second synchronization signal Vst2 are both high level voltages, the threshold voltage of the dual gate transistor T2 is reduced after modulation, and the dual gate transistor T2 enters a conduction region, so that all pixels are set to be high level synchronously, which is prepared for a subsequent pulse width modulation process;

the P2 program is the first-order programming segment S31 of S3 in fig. 4, in which the programming signal Vdata is input to the gate node of the dual-gate transistor T2 through the transistor T1. For pixel circuits in different rows and the same column, for example, pixel circuits in the same column on two rows controlled by corresponding Vscan [1] and Vscan [2], the gates of the dual-gate transistors are programmed to Vd1 and Vd2 voltages in sequence, and have different charge levels;

the P3 display is a second-order programming segment of S2 in fig. 4, in which when the second synchronization signal Vst2 is ramped up and the rising value reaches the pre-programmed signal Vdatax, the charge on the liquid crystal pixel capacitor Cls is completely discharged, i.e., Vpx is decreased to 0.

The specific calculation method is as follows:

a threshold voltage Vth of the double-gate transistor T2 is Vth0+ k1 × Vdata + k2 × Vramp;

wherein Vth0 is the initial threshold voltage of the dual-gate transistor T2, Vdata is the source data voltage for first-order programming, Vramp is the voltage of the ramp signal line, i.e., Vst2, and k1 and k2 are coefficients;

preferably, k1 ═ 1, k2 ═ 1;

if Vramp is β t, Vth is Vth0-Vdata- β t; i.e., the Vth value of the double-gate transistor T2 is dynamically changing.

For a transistor, when its Vgs > Vth, the on-discharge condition is satisfied;

namely: vdata > Vth 0-Vdata-beta t;

namely, the conversion results in: t ═ Vth0-2 × Vdata)/β;

for better illustration, the following are exemplified:

vth0 is 1V, Vdata is-2V, β is 1V/ms, and t is 5ms, and in a specific display, when the backlight is turned on, the liquid crystal pixel is in a high-level fully-on state, and when the duration t is 5ms, the display time is 5 ms.

If Vdata is-3V, the corresponding display time becomes 7 ms.

In short, by programming different data for the first-order programming data Vdata in the first-order programming stage, different high-level on-times can be obtained, i.e., a digital programming result is realized.

Wherein Vgs is the voltage value between the source and drain of the transistor.

The first-order programming data for each pixel remains on the main gate until the next first-order programming begins.

In the digital programming method, the first-order programming phase and the light field phase do not overlap, so the overall light field time is relatively short.

As shown in FIG. 5a, due to the different data inputs of the two pixels Vdata [1] and Vdata [2], the operating voltage Vpx1 has a different duration than the duration ofVpx 2.

The timing diagram of the simulated programming method is shown in FIG. 5 b:

FIG. 5b is a circuit diagram of the analog driving pixel and the operation timing diagram, wherein the first-order programming and the second-order programming of the green G sub-frame, as well as the L phase and the K phase of the light field are illustrated by taking the red R sub-frame followed by the green G sub-frame as an example.

When the red R subframe is displayed, on one hand, the red R subframe is normally displayed, and on the other hand, the first-order programming of the green G subframe is synchronously expanded; it is worth pointing out that although the data signal of the G sub-frame has entered the top gate, i.e. the main gate, of the dual-gate transistor T2 through the transistor T1, since the voltage of the bottom gate, i.e. the auxiliary gate Vst2, of the dual-gate transistor T2 is low, the dual-gate transistor T2 is still in the higher threshold voltage Vth state, so that the first-order programming of the green G sub-frame does not affect the normal display of the red R sub-frame, and the liquid crystal pixel capacitor Cls of the pixel circuit maintains the voltage required for the display of the red R sub-frame.

As shown in FIG. 5b, the black field K frame includes two preset charging segments S1 and a second-order programming segment S2 of FIG. 4, i.e., two stages, i.e., P1 and P2 in FIG. 5 b; in the P1, i.e., the preset charge pre-charge stage, when the second synchronization signal Vst2, i.e., Vctrl in the figure, is at a high level and the first synchronization signal Vst1, i.e., Vst in the figure, is also at a high level, the operating voltage Vpx of the liquid crystal pixel capacitor Cls is synchronously at a high level VH;

then, entering a stage P2, namely a second-order programming 2nd program, the top gate and the bottom gate of the dual-gate transistor T2, namely Vst and Vctrl connected with the main gate and the auxiliary gate, are changed, so that the dual-gate transistor T2 is in a working state with a lower threshold voltage Vth, namely, an on state starts to discharge, and the discharge amount of the liquid crystal pixel capacitor Cls depends on the charge input to the main gate of the dual-gate transistor T2 through Vdata in the first-order programming in the last subframe; when the voltage Vdata is transferred to the main grid electrode of the double-grid transistor T2, the higher the voltage is, the more input charges are, the higher the conduction capability is, and the stronger the discharge capability is; the lower the voltage to which the operating voltage Vpx of the liquid crystal pixel capacitance can be discharged; otherwise, the operating voltage Vpx is discharged to a higher voltage; the top gate and the bottom gate of the double-gate transistor T2, namely Vst and Vctrl connected with the main gate and the auxiliary gate, change, and the mutual duration determines the duration of the second-order programming in the stage P2, which also affects the working voltage Vpx of the liquid crystal pixel capacitor; if the duration is long, the discharge time is long, and the working voltage Vpx is pulled down to a lower voltage level; otherwise, the voltage level is relatively high;

finally, entering the stage of light field L frame, i.e., P3, i.e., the S3 element described in fig. 4, the different backlight colors represent the different colors of the light field L frame; in the stage P3, i.e., in the light emitting display state where the backlight is turned on, Vctrl is also already at the low level, the threshold voltage Vth of the dual-gate transistor T2 becomes high and is in the off state, and the voltage Vpx of the liquid crystal pixel capacitance Cls maintains the operating voltage after the second-order programming is completed.

In the above process, the working principle and the calculation method are as follows:

where Δ T is the discharge time, i.e., the duration of the second-order programming of P2, V_H The preset voltage is preset when the liquid crystal pixel is preset to a high level, and Tf is the discharge characteristic time of a liquid crystal pixel capacitor Cls and depends on the characteristics of the liquid crystal pixel; clc is the capacitance value of the liquid crystal pixel capacitance Cls;

Tf＝C_LC *Req

wherein Req is the equivalent impedance of the drive transistor;

in the above formula, L and W are respectively the channel length and the channel width of the dual-gate transistor T2, μ is the electron mobility, CI is the capacitance of the gate dielectric layer in unit area of the TFT, Vt is the threshold voltage Vth of the TFT, and Vdata is the data voltage value input by the SOURCE DRIVER in the first-order programming phase.

Combining the above, the complete expression of Vpx is:

in the above manner, for each liquid crystal pixel capacitor, according to image data, that is, representing different liquid crystal pixel operating voltages Vpx, the voltages are constant for the same liquid crystal screen and for the same image data, and can be obtained by table lookup or other calculations; the time for second-order programming P2 can be defined according to practical situation, once the working mode is determined for the whole liquid crystal panel and all pixels, Δ T is the discharge time, i.e. the duration of the second-order programming of P2 is also constant; therefore, the first-order programming data Vdata required to be input in the first-order programming stage can be calculated in the above mode, so that image display is realized, and the simulation programming result is realized.

Wherein,

the first-order programming data for each pixel remains on the main gate until the next first-order programming begins.

After the second-order programming phase P2, a P3 phase, i.e., a light field L field, in this example, a green field G Frame, is entered, the backlight is turned on, and after a P31 buffering phase, a first-order programming P32 phase is performed, such as the S31 and S32 links illustrated in fig. 4.

As shown, different Vpx [1] and Vpx [2] are generated due to different data inputs to the two pixels Vdata [1] and Vdata [2 ]. .

The beneficial effects of this embodiment are as follows:

(1) in a conventional pixel circuit design mode and a backlight factory lighting real mode, liquid crystal pixel capacitance programming is sequentially carried out, data programming is completely finished from a first row to a last row, and the required normal time is long, so that the content displayed in the first row and the content displayed in the last row are not synchronous; particularly, under the environment of high-resolution liquid crystal display, the asynchronism is more serious;

when the field sequential method is used for displaying, and the RGB light sources are matched to realize color display, when the programming method is used for image display, the backlight source needs to be started for display until the last line of programming is finished, so that the time for actual display is extruded to be extremely short, and the brightness is very low. To improve the brightness, on the one hand, the requirement for backlight becomes abnormally high, which is likely to cause a problem of the lifetime of the display light source, etc.; on the other hand, if the programming time of the liquid crystal pixel capacitor is shortened, the requirement on the data driving capability of the display is high, and the programming of all data needs to be completed as soon as possible, so that the cost of the driving chip and the requirement on the driving capability are high, and the cost is also high.

In the present embodiment, the data programming and lighting are performed in a parallel pipeline, for example, in the process of displaying the red R subframe, the data programming operation required for the next subframe G is performed synchronously. Therefore, the effective display time is not occupied by the data writing action, so that the effective time is obviously increased, the field sequential display time is prolonged, and the driving capability requirement on a programming device is reduced;

of course, the technical solution provided in this embodiment can be used not only for a liquid crystal panel that performs display by using a field sequential method, but also for a conventional liquid crystal panel, that is, a common liquid crystal panel in the background art.

(2) The embodiment can realize the functions only by two transistors and one capacitor, has controllable volume, controllable process and controllable cost, and has good application value because the aperture opening ratio and the light transmittance are high due to small volume.

The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (21)

1. A pixel circuit based on a double-gate transistor is characterized by comprising a liquid crystal pixel capacitor Cls, a transistor T1 and a double-gate transistor T2, wherein one end of the liquid crystal pixel capacitor Cls is connected with a reference voltage of a liquid crystal screen, the other end of the liquid crystal pixel capacitor Cls is connected with a drain electrode of the double-gate transistor T2, a source electrode of the double-gate transistor T2 is coupled to a first synchronous signal Vst1, one gate electrode of the double-gate transistor T2 is connected to a second synchronous signal Vst2, and the other gate electrode of the double-gate transistor T1 is coupled with the transistor T1.

2. The dual-gate transistor-based pixel circuit of claim 1, wherein said transistor T1 is a dual-gate transistor.

3. A double gate transistor based pixel circuit as claimed in claim 2, wherein when the transistor T1 is a double gate transistor, both gates of the transistor T1 are connected to Vscan.

4. The pixel circuit of claim 2, wherein when the transistor T1 is a double-gate transistor, one gate of the transistor T1 is connected to Vscan, and the other gate is connected to a first synchronization signal Vst 1.

5. The pixel circuit of claim 2, wherein when the transistor T1 is a double-gate transistor, one gate of the transistor T1 is connected to Vscan and the other gate is connected to the other gate of the double-gate transistor T2.

6. The pixel circuit of claim 2, wherein when the transistor T1 is a double-gate transistor, one gate of the transistor T1 is connected to Vscan, and the other gate is connected to one gate of the double-gate transistor T2.

7. The dual-gate transistor-based pixel circuit of claim 2, wherein when said transistor T1 is a dual-gate transistor, one gate of said transistor T1 is connected to Vscan and the other gate is connected to the liquid crystal pixel capacitance Cls.

8. A pixel circuit based on a dual gate transistor according to any one of claims 2-7, wherein each pixel is connected to at least a first synchronization signal electrode line and a second synchronization signal electrode line, the two electrode lines are global common electrode lines for controlling all pixels, and the global common electrode lines are arranged in a manner that: arranged in a lateral gate direction, arranged in a longitudinal source direction, or arranged crosswise.

9. The pixel circuit of claim 8, wherein the global common electrode line of the pixel circuit can share one electrode line for two adjacent rows or two adjacent columns, so as to reduce the occupation of the opening area.

10. A driving method of a pixel circuit based on a double-gate transistor, which is characterized by applying any one of claims 1-9, and is implemented according to the following steps:

s1, presetting a charging link: charging the liquid crystal pixel capacitor Cls through a high level, and presetting the liquid crystal pixel capacitor Cls to the high level;

s2, second-order programming link: the liquid crystal pixel capacitor Cls discharges to the working voltage required by the liquid crystal pixel to display the image;

s3, first-order programming link: at the operating voltage of S2, the charge delivered from the external control unit is received and stored by the transistor T1 for the display of the next frame image.

11. The driving method of a pixel circuit based on a dual gate transistor as claimed in claim 10, wherein the discharging of the liquid crystal pixel capacitance Cls in S2 to the working voltage required by the liquid crystal pixel to display the image is specifically as follows:

the first synchronization signal Vst1 and the second synchronization signal Vst2 cooperate to turn on the dual-gate transistor T2, thereby discharging the liquid crystal pixel capacitor Cls.

12. The driving method of a pixel circuit based on a dual gate transistor as claimed in claim 11, wherein the discharging time of the liquid crystal pixel capacitor Cls depends on the time when the first and second synchronization signals Vst1 and Vst2 match each other.

13. The driving method of a pixel circuit based on a dual gate transistor as claimed in claim 12, wherein the discharging capability of the liquid crystal pixel capacitor Cls depends on the charge stored in S3.

14. A method for driving a pixel circuit based on a dual gate transistor according to any of claims 10-13, wherein after the second order programming segment of S2, the backlight is turned on and the first order programming is started simultaneously.

15. A driving method for a pixel circuit based on a dual gate transistor according to any one of claims 10-13, wherein after the second order programming step of S2, the backlight is turned on, and after buffering, the first order programming is performed, wherein the first order programming is not extendable to the second order programming step.

16. The driving method of a pixel circuit based on a dual gate transistor as claimed in claim 10, wherein in the charging step of S1, all liquid crystal pixels constituting the liquid crystal panel are preset to high level synchronously at one time by high level.

17. The driving method of a pixel circuit based on a dual-gate transistor according to claim 10 or 16, wherein in the second-order programming step of S2, the second-order programming of all pixels constituting the liquid crystal panel is performed simultaneously and at once.

18. A method of driving a pixel circuit based on a dual gate transistor according to claim 17, the method further comprising: the backlight source of the liquid crystal display is sequentially turned on and off, and the first-order programming process is sequentially carried out in the first-order programming stage, so that the assembly line type driving logic is formed.

19. The driving method of a pixel circuit based on a dual gate transistor as claimed in claim 11, wherein when the first and second synchronization signals Vst1 and Vst2 are square waves, the operating voltage Vpx is in the range of 0 ≦ Vpx ≦ VH, where VH is the voltage at which the liquid crystal pixel capacitance is preset to the highest level.

20. The method as claimed in claim 11 or 19, wherein when the first and second synchronization signals Vst1 and Vst2 are ramp waves, the dual gate transistor maintains a high state of the liquid crystal pixel capacitor for a certain time and then turns on to discharge the liquid crystal pixel capacitor to zero level.

21. The method of claim 20, wherein when the operating voltage is high, the time for which the high level is maintained depends on the charge in S3 and the parameters of the ramp wave.

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