CN114899238A - Horizontal enhancement mode gallium oxide metal oxide semiconductor field effect transistor and method of making the same - Google Patents
Horizontal enhancement mode gallium oxide metal oxide semiconductor field effect transistor and method of making the sameDownload PDFInfo
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Abstract
Description
Translated fromChinese技术领域technical field
本发明属于半导体器件技术领域，特别涉及一种水平增强型氧化镓金属氧化物半导体场效应晶体管，可用于功率器件和开关器件。The invention belongs to the technical field of semiconductor devices, and in particular relates to a horizontal enhancement type gallium oxide metal oxide semiconductor field effect transistor, which can be used for power devices and switching devices.
背景技术Background technique
氧化镓材料的优势在于它的极宽的禁带宽度，室温下禁带宽度大约为4.8-4.9eV，它可应用于功率器件。与其他的半导体材料Si，SiC，GaN相比，氧化镓材料禁带宽度更高，击穿场强更大，其理论击穿场强可达到8MV/cm。氧化镓材料的巴利加优值高为3444，远超过了Si，SiC，GaN等材料，说明氧化镓材料在功率器件方面的潜力更大。此外，大规模高质量的氧化镓单晶可用熔融法制成，生成成本低。在实际生产中高浓度n型的氧化镓材料可以通过掺Si或者掺Sn等杂质制备得到，但是p型氧化镓材料的制备仍然是一个巨大的难题，因此常常会用p型的氧化物例如SnO，NiO材料来代替。在众多的p型材料中，在室温下拥有3.6eV禁带宽度的NiO在功率器件和光电器件显然有着巨大的优势。这是因为NiO薄膜的性质稳定，可见光的透过率较高，是一种直接带隙的本征p型材料。由于p型NiO材料可以通过镍和一价杂质制备，因而制备流程较其他p型氧化物例如SnO材料更为简单。The advantage of gallium oxide material lies in its extremely wide band gap, which is about 4.8-4.9 eV at room temperature, and it can be used in power devices. Compared with other semiconductor materials Si, SiC and GaN, gallium oxide material has higher forbidden band width and larger breakdown field strength, and its theoretical breakdown field strength can reach 8MV/cm. The Barriga figure of merit of gallium oxide is as high as 3444, far exceeding that of Si, SiC, GaN and other materials, indicating that gallium oxide has greater potential in power devices. In addition, large-scale, high-quality gallium oxide single crystals can be fabricated by fusion methods with low production costs. In actual production, high-concentration n-type gallium oxide materials can be prepared by doping Si or Sn and other impurities, but the preparation of p-type gallium oxide materials is still a huge problem, so p-type oxides such as SnO are often used. NiO material instead. Among the many p-type materials, NiO with a band gap of 3.6 eV at room temperature obviously has huge advantages in power devices and optoelectronic devices. This is because the NiO film has stable properties, high transmittance of visible light, and is an intrinsic p-type material with a direct band gap. Since p-type NiO materials can be prepared from nickel and monovalent impurities, the preparation process is simpler than other p-type oxides such as SnO materials.
由于氧化镓材料自身材料的性质，现有技术普遍研究制作的是耗尽型MOSFET。但是耗尽型的MOSFET不能在栅压零偏时关断，这种情况有时并不符合电路的要求。为了解决这个问题，研究者使用环绕栅鳍阵列来实现氧化镓增强型MOSFET，虽然这种结构可以在VGS＝0V时，击穿电压VBK>600V，但是这种无栅的鳍沟道MOSFET导通电流仅为1mA/mm。另一种方法是通过低无意掺杂浓度或者薄沟道来实现氧化镓整个沟道的控制，然而这种方法的缺点是需要厚的栅介质才能在高压情况下工作。目前也可以通过嵌入栅的方法使得栅极零偏时部分外延层沟道耗尽来实现增强型。通过这种方法虽然可以实现漏电流近40mA/mm，且当源漏相距8um时栅压为0V时，击穿电压达到505V的效果。但该方法由于未对金属和氧化镓的外延层接触面进行优化，导致欧姆接触电阻大，大约为25Ω·mm，且在栅级干法刻蚀过程由于只使用反应离子刻蚀RIE或电感耦合等离子体ICP刻蚀并未进行刻蚀优化，会造成垂直面上有轻微的锥形形状和多余的表面态，对器件造成不利的影响。Due to the properties of the gallium oxide material itself, depletion-mode MOSFETs are generally researched and fabricated in the prior art. However, the depletion MOSFET cannot be turned off when the gate voltage is zero biased, which sometimes does not meet the requirements of the circuit. In order to solve this problem, the researchers used the surrounding gate fin array to realize the gallium oxide enhancement mode MOSFET. Although this structure can be VGS =0V, the breakdown voltage VBK >600V, but this gateless fin channel MOSFET On-current is only 1mA/mm. Another method is to achieve control of the entire channel of gallium oxide through low unintentional doping concentration or thin channel, but the disadvantage of this method is that it requires a thick gate dielectric to operate at high voltages. At present, the enhancement mode can also be realized by embedding the gate so that part of the channel of the epitaxial layer is depleted when the gate is zero biased. Through this method, the leakage current of nearly 40mA/mm can be achieved, and when the gate voltage is 0V when the source-drain distance is 8um, the breakdown voltage can reach 505V. However, this method does not optimize the contact surface between the epitaxial layer of metal and gallium oxide, resulting in a large ohmic contact resistance, about 25Ω·mm, and in the gate-level dry etching process, only reactive ion etching (RIE) or inductive coupling are used. Plasma ICP etch is not etch-optimized, resulting in slightly tapered shapes and unwanted surface states on the vertical planes, which can adversely affect the device.
发明内容SUMMARY OF THE INVENTION
本发明的目的是在于针对上述现有技术的不足，提出了一种水平增强型氧化镓MOSFET器件及其制作方法，以降低器件的额外功耗和制作成本，减小欧姆接触电阻。The purpose of the present invention is to provide a horizontal enhancement type gallium oxide MOSFET device and a manufacturing method thereof in view of the above-mentioned deficiencies of the prior art, so as to reduce the extra power consumption and manufacturing cost of the device and reduce the ohmic contact resistance.
为实现上述的目的，本发明的一种水平增强型的MOSFET，自下而上包括：衬底，缓冲层和沟道层，特征在于：沟道层中间的上部依次设有p+NiO层和p-NiO层，该p-NiO层的上表面设有栅电极，沟道层上表面的左右两侧分别为源极和漏极。In order to achieve the above-mentioned purpose, a horizontally enhanced MOSFET of the present invention includes from bottom to top: a substrate, a buffer layer and a channel layer, and is characterized in that: the upper part of the middle of the channel layer is sequentially provided with a p+NiO layer and a channel layer. A p-NiO layer, the upper surface of the p-NiO layer is provided with a gate electrode, and the left and right sides of the upper surface of the channel layer are respectively a source electrode and a drain electrode.
进一步，衬底采用掺Mg或Fe的半绝缘体的β-Ga2O3材料。Further, the substrate is a semi-insulator β-Ga2 O3 material doped with Mg or Fe.
进一步，沟道层的厚度为100nm-150nm，掺杂浓度为7*1016-5*1017cm-3。Further, the thickness of the channel layer is 100 nm-150 nm, and the doping concentration is 7*1016 -5*1017 cm-3 .
进一步，p+NiO空穴浓度为2.3*1019-3.6*1019cm-3，厚度为100-150nm。p-NiO的空穴浓度为5.1*1017-5.8*1017cm-3，厚度为30-50nm。Further, the hole concentration of p+NiO is 2.3*1019 -3.6*1019 cm-3 , and the thickness is 100-150 nm. The hole concentration of p-NiO is 5.1*1017 -5.8*1017 cm-3 , and the thickness is 30-50 nm.
为实现上述目的，本发明制作的水平增强型MOSFET的方法，其特征在于：包括如下的步骤：In order to achieve the above object, the method for the horizontal enhancement mode MOSFET made by the present invention is characterized in that: comprising the following steps:
1)将长有非故意掺杂的缓冲层的β-Ga2O3半绝缘衬底材料依次进行有机物清洗和去离子水清洗，并用高纯N2吹干；1) The β-Ga2 O3 semi-insulating substrate material with an unintentionally doped buffer layer is sequentially cleaned with organic matter and deionized water, and dried with high-purity N2 ;
2)将清洗后的样件通过分子束外延MBE方法在缓冲层上生成厚度为100nm-150nm的n型β-Ga2O3沟道层；2) generating an n-type β-Ga2 O3 channel layer with a thickness of 100nm-150nm on the buffer layer on the cleaned sample by molecular beam epitaxy MBE method;
3)在沟道层上进行光刻，并采用BCl3和Ar进行干法刻蚀，后进行光刻胶去除，形成间隔相等的隔离小块；3) photolithography is performed on the channel layer, and BCl3 and Ar are used for dry etching, and then the photoresist is removed to form isolated small blocks with equal intervals;
4)在每个隔离小块上进行光刻形成未被光刻胶保护的离子注入区域，在该注入区域进行n型离子注入，使其形成浓度为1018cm-3-1019cm-3n+区域；4) Perform photolithography on each isolation block to form an ion implantation region that is not protected by photoresist, and perform n-type ion implantation in the implantation region to form a concentration of 1018 cm-3 -1019 cm-3 n+ area;
5)通过RIE对离子注入区域进行浅刻蚀，刻蚀深度为13nm-15nm；5) Perform shallow etching on the ion implantation region by RIE, and the etching depth is 13nm-15nm;
6)对完成刻蚀后的样品进行光刻胶去除，再进行高温退火；6) Remove the photoresist from the etched sample, and then perform high temperature annealing;
7)对退火后的样品进行光刻形成源漏沉积区，在沉积区上先进行厚度为20nm-60nm的Ti金属蒸发，再进行厚度为120nm-230nm的Au金属蒸发，形成漏源电极，并退火；7) Perform photolithography on the annealed sample to form a source-drain deposition area, first perform Ti metal evaporation with a thickness of 20nm-60nm on the deposition area, and then perform Au metal evaporation with a thickness of 120nm-230nm to form drain-source electrodes, and annealing;
8)对形成漏源电极的样品进行光刻形成NiO溅射区域，并通过射频RF磁控溅射技术生成浓度不同的双层NiO薄膜，其中高浓度的NiO薄膜层的空穴浓度为2.3*1019-3.6*1019cm-3，低浓度的NiO薄膜层的空穴浓度为5.1*1017-5.8*1017cm-3；8) Perform photolithography on the sample forming the drain-source electrode to form a NiO sputtering area, and generate double-layer NiO films with different concentrations by radio frequency RF magnetron sputtering technology, wherein the hole concentration of the high-concentration NiO film layer is 2.3* 1019 -3.6*1019 cm-3 , the hole concentration of the low concentration NiO thin film layer is 5.1*1017 -5.8*1017 cm-3 ;
9)对溅射后的样品进行光刻胶去除，并在温度为300-350℃的N2气氛下进行3-5min的退火；9) The photoresist is removed from the sputtered sample, and annealing is performed for 3-5 min under a N2 atmosphere at a temperature of 300-350° C.;
10)依次用光刻、电子束蒸发和剥离工艺在低浓度的NiO薄膜层上先蒸发厚度为20-60nm的Ni，再蒸发厚度为80-200nm的Au，生成栅电极，完成器件制作。10) Evaporating Ni with a thickness of 20-60 nm on the low-concentration NiO thin film layer, and then evaporating Au with a thickness of 80-200 nm on the low-concentration NiO thin film layer by photolithography, electron beam evaporation and lift-off process in turn, to generate a gate electrode and complete the device fabrication.
本发明具有如下优点：The present invention has the following advantages:
1、本发明由于在沟道层中间的上部设有p+NiO层，使得较低浓度n型沟道层和p型高浓度的NiO层之间形成异质pn结，可通过器件沟道层耗尽降低器件的静态功耗，提高击穿电压。1. In the present invention, a p+NiO layer is provided in the upper part of the middle of the channel layer, so that a hetero pn junction is formed between the lower concentration n-type channel layer and the p-type high concentration NiO layer, which can pass through the device channel layer. Depletion reduces the static power dissipation of the device and increases the breakdown voltage.
2、本发明由于采用双层NiO薄膜层设计，且在退火工艺之后低浓度的p型NiO薄膜层空穴浓度会变得更低，导电能力变弱，使得低浓度的p型NiO薄膜层充当着栅介质层的作用，从而保证了器件的正常工作；同时由于退火工艺的作用，减少了沟道层和高浓度NiO薄膜层之间的界面态。2. Since the present invention adopts the design of double-layer NiO thin film layer, and after the annealing process, the hole concentration of the low-concentration p-type NiO thin film layer will become lower, and the electrical conductivity will become weaker, so that the low-concentration p-type NiO thin film layer acts as a The gate dielectric layer is used to ensure the normal operation of the device; at the same time, the interface state between the channel layer and the high-concentration NiO thin film layer is reduced due to the effect of the annealing process.
3、本发明由于在n型氧化镓沟道层左右两侧设有离子注入区域，且在该区域内注入离子形成高掺杂浓度区域，可在漏源极和沟道层之间形成良好的欧姆接触。3. In the present invention, since ion implantation regions are provided on the left and right sides of the n-type gallium oxide channel layer, and ions are implanted in this region to form a high doping concentration region, a good ion can be formed between the drain source electrode and the channel layer. Ohmic contact.
附图说明Description of drawings
图1是本发明的剖面结构示意图；Fig. 1 is the sectional structure schematic diagram of the present invention;
图2是本发明器件的制作流程示意图。FIG. 2 is a schematic diagram of the fabrication process of the device of the present invention.
具体实施方式Detailed ways
以下结果附图对本发明的实施例进行详细描述，但不限于此阐述的实施例。Embodiments of the present invention are described in detail with the accompanying drawings below, but are not limited to the embodiments set forth herein.
参照图1，本发明器件包括：衬底1，缓冲层2和沟道层3，p+NiO薄膜层4，p-NiO薄膜层5。其中：1 , the device of the present invention includes: a
所述衬底1采用掺Mg或Fe的半绝缘体的β-Ga2O3材料，The
所述缓冲层2为非故意掺杂β-Ga2O3材料，其位于衬底1上。The
所述沟道层的厚度为100nm-150nm，掺杂电子浓度为7*1016-5*1017cm-3，其位于缓冲层2上。The thickness of the channel layer is 100 nm-150 nm, and the doping electron concentration is 7*1016 -5*1017 cm-3 , which is located on the
所述p+NiO薄膜层4的厚度为100-150nm，空穴浓度为2.3*1019-3.6*1019cm-3，其位于沟道层3中间上部。The p+NiO
所述p-NiO薄膜层5的厚度为30-50nm，空穴浓度为5.1*1017-5.8*1017cm-3，其位于p+NiO薄膜层上。The p-NiO
所述源极6和漏极7分别位于沟道层上表面的左右两侧。The
所述栅极8位于p-NiO薄膜层上。The
参照图2，本发明制作水平增强型氧化镓MOSFET方法给出如下三种实施例：Referring to Fig. 2, the present invention provides the following three embodiments:
实施例1，制作衬底为Fe掺杂的β-Ga2O3半绝缘体衬底，氧化镓沟道层的浓度为3*1017cm-3，沟道层的厚度为150nm。p+NiO的空穴浓度为3.6*1019cm-3，p-NiO的空穴浓度为5.1*1017cm-3的氧化镓MOSFET器件。Example 1, the fabrication substrate is Fe-doped β-Ga2 O3 semi-insulator substrate, the concentration of the gallium oxide channel layer is 3*1017 cm-3 , and the thickness of the channel layer is 150 nm. The hole concentration of p+NiO is 3.6*1019 cm-3 , and the hole concentration of p-NiO is 5.1*1017 cm-3 .
步骤1，对带有非故意掺杂UID缓冲层的掺Fe氧化镓半绝缘衬底进行清洗。如图2(a)。
选有带UID缓冲层的掺Fe氧化镓半绝缘衬底，依次放在丙酮和无水乙醇溶液中超声清洗10分钟，并用等离子水清洗1分钟，最后用高纯N2吹干。A Fe-doped gallium oxide semi-insulating substrate with a UID buffer layer was selected, placed in acetone and anhydrous ethanol solutions for ultrasonic cleaning for 10 min, and plasma water for 1 min, and finally dried with high-purityN2 .
步骤2，在非故意掺杂UID的缓冲层上通过分子束外延来生长n型氧化镓沟道层。如图2(b)。
将带有缓冲层的掺Fe的半绝缘体氧化镓标准清洗完后，放入MBE生长室中，在K室中加热高纯度的7N Ga和高纯度的4N SnO2粉末以提供Ga元素和Sn元素，使用臭氧占比5％，氧气占比95％的混合气体以提供氧元素。After cleaning the Fe-doped semi-insulator gallium oxide standard with buffer layer, put it into the MBE growth chamber, and heat high-purity 7N Ga and high-purity 4N SnO2 powder in the K chamber to provide Ga element and Sn element , using a mixture of 5% ozone and 95% oxygen to provide oxygen.
对得到的Ga源设置2.1*10-4Pa压强使其进入反应腔，并向反应腔内通入流量5sccm混合气体，将衬底加热到560℃，得到厚度为150nm、电子浓度为3*1017cm-3的沟道层样品。A pressure of 2.1*10-4 Pa was set on the obtained Ga source to enter the reaction chamber, and a mixed gas with a flow rate of 5 sccm was introduced into the reaction chamber, and the substrate was heated to 560 ° C to obtain a thickness of 150 nm and an electron concentration of 3*1017 cm-3 channel layer sample.
步骤3，对沟道层进行干法刻蚀。如图2(c)。Step 3, dry etching the channel layer. As shown in Figure 2(c).
对沟道层先进行光刻，再在等离子体刻蚀机中通入流量为20sccm BCl3和流量为10sccm Ar气体，并设置反应室的压强为20mTorr，射频功率为200W的工艺条件，对沟道层进行深度为150nm的刻蚀，后进行光刻胶的去除，形成间隔相等的隔离小块。The channel layer is first photoetched, and then the flow rate of 20sccm BCl3 and the flow rate of 10sccm Ar gas are introduced into the plasma etching machine, and the pressure of the reaction chamber is set to 20mTorr and the radio frequency power is 200W. The track layer is etched with a depth of 150 nm, and then the photoresist is removed to form isolated small blocks with equal intervals.
步骤4，对离子注入区域进行离子注入。如图2(d)。
4.1)对沟道层表面重新进行光刻，形成未被光刻胶保护的离子注入区域；4.1) Re-photolithography is performed on the surface of the channel layer to form an ion implantation area that is not protected by the photoresist;
4.2)将光刻后的样品放到离子注入机中对离子注入区域进行离子注入，注入角度为7°的Si离子，注入剂量为3*1015cm-3，注入能量为10Kev，得到注入深度为70nm的样品。4.2) Put the photolithographic sample into the ion implanter and perform ion implantation in the ion implantation area. The implantation angle is 7° of Si ions, the implantation dose is 3*1015 cm-3 , the implantation energy is 10Kev, and the implantation depth is obtained. for 70nm samples.
步骤5，通过用反应离子刻蚀RIE对源漏预设区域进行浅刻蚀，如图2(e)。
将离子注入后的样品放到等离子体刻蚀机中，设置RIE腔室压力为5.0Pa，等离子体的功率为150W，使用Bcl3和Ar混合气体对离子注入区域进行刻蚀，得到刻蚀深度为15nm的样品。Put the ion-implanted sample into the plasma etcher, set the RIE chamber pressure to 5.0Pa, the plasma power to 150W, and useBcl3 and Ar mixed gas to etch the ion-implanted area to obtain the etching depth for 15nm samples.
将刻蚀后的样品进行光刻胶去除，之后在气氛条件为N2，温度1000℃情况下，退火30s。从而在离子注入区域得到掺杂浓度为5*1018cm-3的样品。The etched samples were subjected to photoresist removal, and then annealed for 30s under the condition of N2 atmosphere and temperature of 1000°C. Thus, a sample with a doping concentration of 5*1018 cm-3 is obtained in the ion implantation region.
步骤6，制作源漏电极，如图2(f)。
7.1)将退火后的样品光刻出源漏预设区域，通过电子束蒸发工艺在该区域依次淀积厚度为20nm Ti和厚度为230nm Au；7.1) The annealed sample is photoetched out of the source-drain preset area, and the thickness of 20nm Ti and the thickness of 230nm Au are sequentially deposited in this area by an electron beam evaporation process;
7.2)将淀积完的金属依次放在丙酮和无水乙醇溶液中超声清洗5分钟，并用等离子水清洗5分钟，用高纯N2吹干后形成源、漏电极；之后，在温度为470℃，氮气流速为3L/min情况下，热退火1分钟，形成良好的欧姆电阻。7.2) The deposited metal was placed in acetone and dehydrated alcohol solution for ultrasonic cleaning for 5 minutes, and was cleaned with plasma water for 5 minutes, and the source and drain electrodes were formed after drying with high-purity N; ℃, under the condition of nitrogen flow rate of 3L/min, thermal annealing is carried out for 1 minute to form a good ohmic resistance.
步骤8，制作双层p型NiO薄膜。如图2(g)。
8.1)将形成漏源电极后的样品光刻出NiO溅射区域，再选用99.99％高纯度NiO陶瓷作为靶材材料，并设置RF功率为150W，生长环境为0.6Pa Ar和O2混合气体工艺条件下，通过控制Ar/O2流速率2:1，在溅射区域溅射得到厚度为100nm，空穴浓度为3.6*1019cm-3的高浓度NiO薄膜层；8.1) The NiO sputtering area is lithographically etched out of the sample after forming the drain-source electrode, and then 99.99% high-purity NiO ceramic is used as the target material, and the RF power is set to 150W, and the growth environment is 0.6Pa Ar and O2 mixed gas process Under the conditions, by controlling the flow rate of Ar/O2 to 2:1, a high-concentration NiO thin film layer with a thickness of 100 nm and a hole concentration of 3.6*1019 cm-3 was obtained by sputtering in the sputtering area;
8.2)将RF磁控溅射生成的高浓度NiO薄膜样品，通过选用99.99％高纯度NiO陶瓷作为靶材材料，并在RF功率为150W，生长环境为0.6Pa Ar和O2混合气体的工艺条件下，控制Ar/O2流速率为20:1，在高浓度NiO薄膜层上溅射得到厚度为30nm、空穴浓度为5.1*1017cm-3的低浓度NiO薄膜层。8.2) The high-concentration NiO thin film samples generated by RF magnetron sputtering are selected by selecting 99.99% high-purity NiO ceramics as the target material, and the process conditions of the RF power is 150W and the growth environment is a mixed gas of 0.6Pa Ar and O2 . Under the control of Ar/O2 flow rate of 20:1, a low-concentration NiO thin film layer with a thickness of 30 nm and a hole concentration of 5.1*1017 cm-3 was obtained by sputtering on the high-concentration NiO thin film layer.
8.3)将溅射后的样品先进行光刻胶的去除，之后在气氛条件为N2，温度350℃情况下，退火3分钟。8.3) Remove the photoresist of the sputtered sample first, and then anneal for 3 minutes under the condition of N2 atmosphere and temperature of 350°C.
步骤9，在低浓度NiO层上淀积栅电极，如图2(h)。In step 9, a gate electrode is deposited on the low-concentration NiO layer, as shown in FIG. 2(h).
9.1)在生长低浓度p-NiO上进行光刻，得到栅极的预设区域，并在栅极的预设区域依次进行Ni、Au金属电子束蒸发，其中Ni的厚度为20nm，Au的厚度为100nm，金属淀积完成后，将其放入丙酮溶液进行剥离，形成栅电极；9.1) Perform photolithography on the growth low-concentration p-NiO to obtain a preset area of the gate, and perform Ni and Au metal electron beam evaporation in the preset area of the gate in turn, wherein the thickness of Ni is 20 nm, and the thickness of Au is 20 nm. It is 100nm, and after the metal deposition is completed, it is put into an acetone solution for stripping to form a gate electrode;
9.2)将剥离好的样品依次放到丙酮溶液，无水乙醇溶液，去离子水中超声清洗各5min，并用纯N2吹干，完成器件制作。9.2) Put the peeled samples into acetone solution, anhydrous ethanol solution, and deionized water for ultrasonic cleaning for 5 min each, and blow dry with pure N2 to complete the device fabrication.
实施例2，制作衬底为Mg掺杂的β-Ga2O3半绝缘体衬底，氧化镓沟道层的浓度为7*1016cm-3，沟道层的厚度为120nm。p+NiO的空穴浓度为2.3*1019cm-3，p-NiO的空穴浓度为5.8*1017cm-3的氧化镓MOSFET器件。In Example 2, the fabrication substrate was a Mg-doped β-Ga2 O3 semi-insulator substrate, the concentration of the gallium oxide channel layer was 7*1016 cm-3 , and the thickness of the channel layer was 120 nm. The hole concentration of p+NiO is 2.3*1019 cm-3 , and the hole concentration of p-NiO is 5.8*1017 cm-3 .
步骤一，选用带有非故意掺杂UID缓冲层的掺Mg氧化镓半绝缘衬底对其进行清洗，如图2(a)。In the first step, a Mg-doped gallium oxide semi-insulating substrate with an unintentionally doped UID buffer layer is used to clean it, as shown in Figure 2(a).
本步骤的具体实施方法与实施例1中的步骤1相同。The specific implementation method of this step is the same as that of
步骤二，在非故意掺杂UID的缓冲层上通过分子束外延来生长n型氧化镓沟道层，如图2(b)。In
将带有缓冲层的掺Mg的半绝缘体氧化镓标准清洗完后，放入MBE生长室中，在K室中加热高纯度的7N Ga和高纯度的4N SnO2粉末以提供Ga元素和Sn元素，使用臭氧占比5％，氧气占比95％的混合气体以提供氧元素；After cleaning the Mg-doped semi-insulator gallium oxide standard with buffer layer, it is put into MBE growth chamber, and high-purity 7N Ga and high-purity 4N SnO2 powder are heated in K chamber to provide Ga element and Sn element , using a mixture of 5% ozone and 95% oxygen to provide oxygen;
对得到的Ga源设置2.1*10-4Pa压强使其进入反应腔，并向反应腔内通入流量5sccm混合气体，加热其衬底温度为700℃，得到厚度为120nm和电子浓度为7*1016cm-3的沟道层样品。Set a pressure of 2.1*10-4 Pa on the obtained Ga source to make it enter the reaction chamber, pass a mixed gas of 5 sccm into the reaction chamber, and heat the substrate to a temperature of 700 °C to obtain a thickness of 120 nm and an electron concentration of 7* 1016 cm-3 of the channel layer sample.
步骤三，对沟道层上进行干法刻蚀。如图2(c)。Step 3, dry etching is performed on the channel layer. As shown in Figure 2(c).
对沟道层先进行光刻，再设置反应室的压强为20mTorr，射频功率为200W的工艺条件下在等离子体刻蚀机中通入流量为20sccm BCl3和流量为10sccm Ar气体，对沟道层进行深度为200nm的刻蚀，后进行光刻胶的去除，形成间隔相等的隔离小块。The channel layer is first photoetched, and then the pressure of the reaction chamber is set to 20mTorr, and the radio frequency power is 200W under the process conditions of a plasma etching machine with a flow rate of 20sccm BCl3 and a flow rate of 10sccm Ar gas. The layer is etched with a depth of 200 nm, and then the photoresist is removed to form isolated small blocks with equal intervals.
步骤四，对离子注入区域进行离子注入。如图2(d)。
对沟道层表面重新进行光刻，形成未被光刻胶保护的离子注入区域，再将其放到离子注入机中按照注入角度为6°的Si离子，注入剂量为1*1015cm-3，注入能量为8Kev的工艺条件对离子注入区域进行深度为60nm的离子注入。Re-lithography the surface of the channel layer to form an ion implantation area that is not protected by the photoresist, and then put it into the ion implanter according to the Si ion implantation angle of 6°, and the implantation dose is 1*1015 cm- 3. The ion implantation region is ion implanted with a depth of 60 nm under the process conditions of the implantation energy of 8Kev.
步骤五，通过用反应离子刻蚀RIE对源漏预设区域进行浅刻蚀，如图2(e)。
将离子注入后的样品放到等离子体刻蚀机中，设置RIE腔室压力为5.0Pa，等离子体的功率为100W，使用Bcl3和Ar混合气体对离子注入区域进行深度为13nm的刻蚀。Put the ion-implanted sample into the plasma etcher, set the RIE chamber pressure to 5.0Pa, the plasma power to 100W, and use Bcl3 and Ar mixed gas to etch the ion-implanted region to a depth of 13nm.
将刻蚀后的样品进行光刻胶去除，之后在气氛条件为N2，温度900℃情况下，退火30s。从而在离子注入区域得到掺杂浓度为1018cm-3的样品。The etched samples were subjected to photoresist removal, and then annealed for 30s under the condition of N2 atmosphere and temperature of 900°C. Thus, a sample with a doping concentration of 1018 cm-3 is obtained in the ion implanted region.
步骤六，制作源漏电极，如图2(f)。In
7.1)在退火后的样品上光刻出源漏预设区域，通过电子束蒸发工艺在该区域依次淀积厚度为60nm的Ti和厚度为120nm的Au；7.1) On the annealed sample, a source-drain preset region is photolithographically formed, and Ti with a thickness of 60 nm and Au with a thickness of 120 nm are sequentially deposited in this region by an electron beam evaporation process;
7.2)将淀积完的金属的样品依次放在丙酮和无水乙醇溶液中超声清洗5分钟，并用等离子水清洗5分钟，用高纯N2吹干后形成源、漏电极；再在温度为470℃，氮气流速为3L/min情况下，热退火1分钟，形成良好的欧姆电阻。7.2) The deposited metal samples were placed in acetone and anhydrous ethanol solution for ultrasonic cleaning for 5 minutes, and cleaned with plasma water for5 minutes, and dried with high-purity N to form source and drain electrodes; At 470°C, under the condition of nitrogen flow rate of 3L/min, thermal annealing was performed for 1 minute to form a good ohmic resistance.
步骤七，制作双层p型NiO薄膜。如图2(g)。Step 7, fabricating a double-layer p-type NiO thin film. As shown in Figure 2(g).
8.1)在形成漏源电极后的样品上光刻出NiO溅射区域，再选用99.99％高纯度NiO陶瓷作为靶材材料，并设置RF功率为100W，生长环境为0.6Pa Ar和O2混合气体工艺条件，控制Ar/O2流速率2:1，在溅射区域溅射得到厚度为120nm，空穴浓度为2.3*1019cm-3的高浓度NiO薄膜层；8.1) The NiO sputtering area is etched on the sample after forming the drain-source electrode, and then 99.99% high-purity NiO ceramic is selected as the target material, and the RF power is set to 100W, and the growth environment is a mixed gas of 0.6Pa Ar and O2 Process conditions, control the flow rate of Ar/O2 to 2:1, and sputter in the sputtering area to obtain a high-concentration NiO thin film layer with a thickness of 120 nm and a hole concentration of 2.3*1019 cm-3 ;
8.2)将RF磁控溅射生成的高浓度NiO薄膜样品，通过选用99.99％高纯度NiO陶瓷作为靶材材料，并在RF功率为100W，生长环境为0.6Pa Ar和O2混合气体的工艺条件下，控制Ar/O2流速率为20:1，在高浓度NiO薄膜层上溅射得到厚度为40nm、空穴浓度为5.8*1017cm-3的低浓度NiO薄膜层。8.2) The high-concentration NiO thin film samples generated by RF magnetron sputtering were selected by selecting 99.99% high-purity NiO ceramics as the target material, and the RF power was 100W and the growth environment was 0.6Pa Ar and O2 mixed gas process conditions Under the control of Ar/O2 flow rate of 20:1, a low-concentration NiO thin film layer with a thickness of 40 nm and a hole concentration of 5.8*1017 cm-3 was obtained by sputtering on the high-concentration NiO thin film layer.
8.3)将溅射后的样品先进行光刻胶的去除，之后在气氛条件为N2，温度340℃情况下，退火4分钟。8.3) Remove the photoresist of the sputtered sample, and then anneal for 4 minutes under the condition of N2 atmosphere and temperature of 340°C.
步骤八，在低浓度NiO层上淀积栅电极，如图2(h)。In the eighth step, a gate electrode is deposited on the low concentration NiO layer, as shown in FIG. 2(h).
9.1)对低浓度NiO薄膜层上进行光刻，得到栅极的预设区域，并在栅极的预设区域依次进行Ni、Au金属电子束蒸发，其中Ni的厚度为60nm，Au的厚度为120nm，金属淀积完成后，将其放入丙酮溶液进行剥离，形成栅电极；9.1) Perform photolithography on the low-concentration NiO thin film layer to obtain a preset area of the gate, and sequentially perform Ni and Au metal electron beam evaporation in the preset area of the gate, wherein the thickness of Ni is 60 nm, and the thickness of Au is 120nm, after the metal deposition is completed, put it into an acetone solution for stripping to form a gate electrode;
9.2)将剥离好的样品依次放到丙酮溶液，无水乙醇溶液，去离子水中超声清洗各5min，并用纯N2吹干，完成器件制作。9.2) Put the peeled samples into acetone solution, anhydrous ethanol solution, and deionized water for ultrasonic cleaning for 5 min each, and blow dry with pure N2 to complete the device fabrication.
实施例3，制作衬底为Fe掺杂的β-Ga2O3半绝缘体衬底，氧化镓沟道层的浓度为5*1017cm-3，沟道层的厚度为100nm。p+NiO的空穴浓度为3*1019cm-3，p-NiO的空穴浓度为5.3*1017cm-3的氧化镓MOSFET器件。In Example 3, the fabrication substrate was a Fe-doped β-Ga2 O3 semi-insulator substrate, the concentration of the gallium oxide channel layer was 5*1017 cm-3 , and the thickness of the channel layer was 100 nm. The hole concentration of p+NiO is 3*1019 cm-3 , and the hole concentration of p-NiO is 5.3*1017 cm-3 .
步骤A，选用带有非故意掺杂UID缓冲层的掺Fe氧化镓半绝缘衬底进行清洗，如图2(a)。In step A, a Fe-doped gallium oxide semi-insulating substrate with an unintentionally doped UID buffer layer is selected for cleaning, as shown in Figure 2(a).
本步骤的具体实施方法与实施例1中的步骤1相同。The specific implementation method of this step is the same as that of
步骤B，在非故意掺杂UID的缓冲层上通过分子束外延来生长n型氧化镓沟道层，如图2(b)。In step B, an n-type gallium oxide channel layer is grown by molecular beam epitaxy on the buffer layer unintentionally doped with UID, as shown in FIG. 2( b ).
B1)将带有缓冲层的掺Fe的半绝缘体氧化镓标准清洗完后，放入MBE生长室中，在K室中加热高纯度的7N Ga和高纯度的4N SnO2粉末以提供Ga元素和Sn元素，使用臭氧占比5％，氧气占比95％的混合气体以提供氧元素。B1) After cleaning the Fe-doped semi-insulator gallium oxide standard with buffer layer, put it into the MBE growth chamber, and heat high-purity 7N Ga and high-purity 4N SnO2 powder in the K chamber to provide Ga element and For Sn element, a mixed gas of 5% ozone and 95% oxygen is used to provide oxygen element.
B2)对得到的Ga源设置2.1*10-4Pa压强使其进入反应腔，并向反应腔内通入流速5sccm混合气体，将衬底加热到600℃，得到厚度为100nm、电子浓度为5*1017cm-3的沟道层样品。B2) Set a pressure of 2.1*10-4 Pa on the obtained Ga source to make it enter the reaction chamber, pass a mixed gas with a flow rate of 5 sccm into the reaction chamber, and heat the substrate to 600° C. to obtain a thickness of 100 nm and an electron concentration of 5 *1017 cm-3 channel layer sample.
步骤C，对沟道层进行干法刻蚀。如图2(c)。In step C, dry etching is performed on the channel layer. As shown in Figure 2(c).
对沟道层先进行光刻，再在等离子体刻蚀机中通入流量为20sccm BCl3和流量为10sccm Ar气体，并设置反应室的压强为20mTorr，射频功率为200W的工艺条件，对沟道层进行深度为170nm的刻蚀，后进行光刻胶的去除，形成间隔相等的隔离小块。The channel layer is first photoetched, and then the flow rate of 20sccm BCl3 and the flow rate of 10sccm Ar gas are introduced into the plasma etching machine, and the pressure of the reaction chamber is set to 20mTorr and the radio frequency power is 200W. The track layer is etched with a depth of 170 nm, and then the photoresist is removed to form isolated small blocks with equal intervals.
步骤D，对离子注入区域进行离子注入。如图2(d)。In step D, ion implantation is performed on the ion implantation region. As shown in Figure 2(d).
D1)对沟道层表面重新进行光刻，形成未被光刻胶保护的离子注入区域；D1) Re-photolithography is performed on the surface of the channel layer to form an ion implantation region that is not protected by the photoresist;
D2)将光刻后的样品放到离子注入机中对离子注入区域进行离子注入，注入角度为9°的Si离子，注入剂量为5*1015cm-3，注入能量为12Kev，得到注入深度为50nm的样品。D2) Put the photolithographic sample into the ion implanter to perform ion implantation in the ion implantation area, the implantation angle is 9° of Si ions, the implantation dose is 5*1015 cm-3 , the implantation energy is 12Kev, and the implantation depth is obtained. for 50nm samples.
步骤E，通过用反应离子刻蚀RIE对源漏预设区域进行浅刻蚀，如图2(e)。Step E, performing shallow etching on the source and drain preset regions by using reactive ion etching (RIE), as shown in FIG. 2(e).
E1)将离子注入后的样品放到等离子体刻蚀机中，设置RIE腔室压力为5.0Pa，等离子体的功率为120W，使用Bcl3和Ar混合气体对离子注入区域进行刻蚀，得到刻蚀深度为14nm的样品。E1) Put the ion implanted sample into the plasma etcher, set the RIE chamber pressure to 5.0Pa, the plasma power to 120W, and useBcl3 and Ar mixed gas to etch the ion implantation area to obtain the etching Samples with an etch depth of 14 nm.
E2)将刻蚀后的样品进行光刻胶去除，之后在气氛条件为N2，温度1100℃情况下，退火30s。从而在离子注入区域得到掺杂浓度为1019cm-3的样品。E2) The etched sample is subjected to photoresist removal, and then annealed for 30s under the condition of N2 atmosphere and temperature of 1100°C. Thus, a sample with a doping concentration of 1019 cm-3 is obtained in the ion implanted region.
步骤F，制作源漏电极，如图2(f)。In step F, source-drain electrodes are fabricated, as shown in FIG. 2(f).
F1)在退火后的样品上光刻出源漏预设区域，通过电子束蒸发工艺在该区域依次淀积厚度为40nmTi和厚度为150nm Au；F1) Photolithography the source-drain preset region on the annealed sample, and deposit 40nm Ti and 150nm Au in this region in turn by an electron beam evaporation process;
F2)将淀积完的金属依次放在丙酮和无水乙醇溶液中超声清洗5分钟，并用等离子水清洗5分钟，再用高纯N2吹干后形成源、漏电极；之后，在温度为470℃，氮气流速为3L/min情况下，热退火1分钟，形成良好的欧姆电阻。F2) Place the deposited metal in acetone and absolute ethanol solution for ultrasonic cleaning for 5 minutes, and clean with plasma water for 5 minutes, and then dry with high- purity N to form source and drain electrodes; after that, at a temperature of At 470°C, under the condition of nitrogen flow rate of 3L/min, thermal annealing was performed for 1 minute to form a good ohmic resistance.
步骤G，制作双层p型NiO薄膜。如图2(g)。In step G, a double-layer p-type NiO thin film is fabricated. As shown in Figure 2(g).
G1)将形成漏源电极后的样品光刻出NiO溅射区域，再选用99.99％高纯度NiO陶瓷作为靶材材料，并设置RF功率为120W，生长环境为0.6Pa Ar和O2混合气体工艺条件下，通过控制Ar/O2流速率2:1，在溅射区域溅射得到厚度为150nm，空穴浓度为3*1019cm-3的高浓度NiO薄膜层；G1) The NiO sputtering area is lithographically etched out of the sample after forming the drain-source electrode, and 99.99% high-purity NiO ceramic is used as the target material, and the RF power is set to 120W, and the growth environment is 0.6Pa Ar and O2 mixed gas process Under the conditions, by controlling the flow rate of Ar/O2 to 2:1, a high-concentration NiO thin film layer with a thickness of 150 nm and a hole concentration of 3*1019 cm-3 was obtained by sputtering in the sputtering area;
G2)将RF磁控溅射生成的高浓度NiO薄膜样品，通过选用99.99％高纯度NiO陶瓷作为靶材材料，并在RF功率为120W，生长环境为0.6Pa Ar和O2混合气体的工艺条件下，控制Ar/O2流速率为20:1，在高浓度NiO薄膜层上溅射得到厚度为50nm、空穴浓度为5.3*1017cm-3的低浓度NiO薄膜层。G2) The high-concentration NiO thin film samples generated by RF magnetron sputtering were selected by selecting 99.99% high-purity NiO ceramics as the target material, and the RF power was 120W and the growth environment was 0.6Pa Ar and O2 mixed gas process conditions Under the control of Ar/O2 flow rate of 20:1, a low-concentration NiO thin film layer with a thickness of 50 nm and a hole concentration of 5.3*1017 cm-3 was obtained by sputtering on the high-concentration NiO thin film layer.
G3)将溅射后的样品先进行光刻胶的去除，之后在气氛条件为N2，温度330℃情况下，退火5分钟。G3) The photoresist of the sputtered sample is removed first, and then annealed for 5 minutes under the condition of N2 atmosphere and temperature of 330°C.
步骤H，在低浓度NiO层上淀积栅电极，如图2(h)。In step H, a gate electrode is deposited on the low-concentration NiO layer, as shown in FIG. 2(h).
H1)在生长低浓度p-NiO上进行光刻，得到栅极的预设区域，并在栅极的预设区域依次进行Ni、Au金属电子束蒸发，得到厚度为40nm的Ni和厚度为150nm的Au；H1) Perform photolithography on the growing low-concentration p-NiO to obtain a preset area of the gate, and sequentially perform Ni and Au metal electron beam evaporation in the preset area of the gate to obtain Ni with a thickness of 40 nm and a thickness of 150 nm. Au;
H2)栅极金属淀积完成后，将其放入丙酮溶液进行剥离，形成栅电极；H2) After the gate metal deposition is completed, put it into an acetone solution for stripping to form a gate electrode;
H3)将剥离好的样品依次放到丙酮溶液，无水乙醇溶液，去离子水中超声清洗各5min，并用纯N2吹干，完成器件制作。H3) Put the peeled samples into acetone solution, absolute ethanol solution, and deionized water for ultrasonic cleaning for 5 min each, and blow dry with pure N2 to complete the device fabrication.
以上描述仅是本发明的三个具体实例，并不构成对本发明的任何限制，显然对于本领域的专业人士来说，在了解了本发明的内容和原理后，都可能在不背离本发明原理、结构的情况下，进行形式和细节上的各种参数修正和改变，但是这些基于本发明思想修正和改变仍在本发明的权利要求保护范围之内。The above descriptions are only three specific examples of the present invention, and do not constitute any limitation to the present invention. Obviously, for professionals in the field, after understanding the content and principles of the present invention, they may not deviate from the principles of the present invention. , in the case of the structure, various parameter corrections and changes in form and details are carried out, but these corrections and changes based on the idea of the present invention are still within the scope of protection of the claims of the present invention.
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