技术领域Technical field
本申请涉及测时和深度测量技术领域，尤其涉及一种时间测量电路、时间测量方法、时间测量芯片、时间测量模组和电子设备。The present application relates to the technical fields of time measurement and depth measurement, and in particular to a time measurement circuit, a time measurement method, a time measurement chip, a time measurement module and an electronic device.
背景技术Background technique
TDC(Time-to-Digital Converter，时间数字转换器)是一种将时间间隔转换为数字量输出的器件，广泛使用于需要高精度时间测量的测距传感领域，如照相对焦、物体识别、增强现实(AR)、三维建模、实景导航等。传统的TDC由多相位环形振荡器(multi-phasering oscillator)及D触发器组成，通过模拟方法进行设计。TDC (Time-to-Digital Converter) is a device that converts time intervals into digital output. It is widely used in ranging sensing fields that require high-precision time measurement, such as photo focusing, object recognition, Augmented reality (AR), 3D modeling, real-life navigation, etc. The traditional TDC consists of a multi-phase ring oscillator and a D flip-flop, and is designed through simulation methods.
然而，采用传统模拟方法设计时通常使用高频时钟PLL和环形振荡器产生多种相位的时钟作为TDC的精度测量单位，当精度要求越高，就需要越高的PLL时钟，使得设计难度增加，并且时钟频率提高将导致电路功耗增加。这种模拟方法还存在易受外界干扰、控制复杂、面积功耗大等技术问题，难以在集成电路上迅速实现。However, when designing using traditional analog methods, high-frequency clock PLL and ring oscillator are usually used to generate clocks with multiple phases as the accuracy measurement unit of TDC. When the accuracy requirements are higher, a higher PLL clock is required, making the design more difficult. And increasing the clock frequency will lead to increased circuit power consumption. This simulation method also has technical problems such as being susceptible to external interference, complex control, and large area and power consumption, making it difficult to quickly implement on integrated circuits.
发明内容Contents of the invention
有鉴于此，本申请实施例提供了一种时间测量电路、方法、芯片、模组和设备，用以取代传统模拟方法并实现高精度时间长度测量精度。In view of this, embodiments of the present application provide a time measurement circuit, method, chip, module, and device to replace the traditional analog method and achieve high-precision time length measurement accuracy.
第一方面，本申请实施例提供了一种时间测量电路，所述电路包括：In a first aspect, embodiments of the present application provide a time measurement circuit, which includes:
信号选择输出模块，用于接收第一信号、第二信号和参考时钟信号，并选择输出测量信号，其中，所述测量信号为所述第一信号、所述第二信号、所述参考时钟信号以及调整后的参考时钟信号中的一种；A signal selection output module, configured to receive a first signal, a second signal and a reference clock signal, and select and output a measurement signal, where the measurement signal is the first signal, the second signal, and the reference clock signal. and one of the adjusted reference clock signals;
时间测量模块，用于校准时间测量精度，并测量所述第一信号和所述第二信号之间的时间间隔。A time measurement module, used to calibrate time measurement accuracy and measure the time interval between the first signal and the second signal.
第二方面，本申请实施例还提供一种基于前述的时间测量电路的时间测量方法，所述方法包括：In a second aspect, embodiments of the present application also provide a time measurement method based on the aforementioned time measurement circuit. The method includes:
S1：获取所述时间测量电路的测量精度；S1: Obtain the measurement accuracy of the time measurement circuit;
S2：根据所述测量精度，获取第一信号上升沿和第一信号上升沿之后首个参考时钟上升沿之间的时间间隔，记为第一时间间隔；S2: According to the measurement accuracy, obtain the time interval between the rising edge of the first signal and the rising edge of the first reference clock after the rising edge of the first signal, and record it as the first time interval;
S3：根据所述测量精度，获取第二信号上升沿和第二信号上升沿之后首个参考时钟上升沿之间的时间间隔，记为第二时间间隔；S3: According to the measurement accuracy, obtain the time interval between the rising edge of the second signal and the rising edge of the first reference clock after the rising edge of the second signal, and record it as the second time interval;
S4：获取所述第一信号上升沿之后首个参考时钟上升沿和所述第二信号上升沿之后首个参考时钟上升沿之间的参考时钟周期个数；S4: Obtain the number of reference clock cycles between the first reference clock rising edge after the first signal rising edge and the first reference clock rising edge after the second signal rising edge;
S5：根据所述第一时间间隔、第二时间间隔和所述参考时钟周期个数，获取所述第一信号和所述第二信号之间的时间间隔。S5: Obtain the time interval between the first signal and the second signal according to the first time interval, the second time interval and the number of reference clock cycles.
第三方面，本申请实施例提供了一种时间测量芯片，所述时间测量芯片包括：In a third aspect, embodiments of the present application provide a time measurement chip. The time measurement chip includes:
如第一方面任一项所述的时间测量电路；以及A time measurement circuit as described in any one of the first aspects; and
模数转换电路，用于模拟信号转换为数字信号并输入到所述时间测量电路。An analog-to-digital conversion circuit is used to convert analog signals into digital signals and input them to the time measurement circuit.
第四方面，本申请实施例提供了一种时间测量模组，所述模组包括：In the fourth aspect, embodiments of the present application provide a time measurement module, which includes:
发射器，用于发射检测信号；Transmitter, used to transmit detection signals;
接收器，用于接收所述检测信号对应的反射信号；A receiver configured to receive the reflected signal corresponding to the detection signal;
如第三方面所述的时间测量芯片，所述时间测量芯片与所述发射器和所述接收器连接，用于测量所述发射器发射的检测信号和所述接收器接收到所述检测信号对应的反射信号的时间间隔。The time measurement chip according to the third aspect, the time measurement chip is connected to the transmitter and the receiver, and is used to measure the detection signal transmitted by the transmitter and the detection signal received by the receiver. The corresponding time interval of the reflected signal.
第五方面，本申请实施例提供了一种电子设备，所述电子设备包括如第四方面所述的时间测量模组。所述电子设备是智能手机、无人机、可移动机器人、智能电视机、AR/VR设备、3D深度测量设备中任一种、两种或多种。In a fifth aspect, embodiments of the present application provide an electronic device, which includes the time measurement module described in the fourth aspect. The electronic device is any one, two or more of smartphones, drones, mobile robots, smart TVs, AR/VR equipment, and 3D depth measurement equipment.
综上所述，本申请的有益效果如下：To sum up, the beneficial effects of this application are as follows:
本申请实施例的时间测量电路通过信号选择输出模块和时间测量模块实现了时间测量精度的校准和测量信号的时间测量。在时钟频率提升空间有限的条件下，可以快速实现皮秒以下的高精度时间测量，在目前普遍的工艺下，可实现约30ps的测量精度。The time measurement circuit in the embodiment of the present application realizes the calibration of time measurement accuracy and the time measurement of the measurement signal through the signal selection output module and the time measurement module. Under the condition that the clock frequency improvement space is limited, high-precision time measurement below picoseconds can be quickly achieved. Under the current common technology, a measurement accuracy of about 30ps can be achieved.
附图说明Description of the drawings
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例中所需要使用的附图作简单地介绍，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图，这些均在本申请的保护范围内。In order to explain the technical solutions of the embodiments of the present application more clearly, the drawings required to be used in the embodiments of the present application will be briefly introduced below. For those of ordinary skill in the art, without exerting creative efforts, they can also Other drawings can be obtained based on these drawings, which are within the protection scope of this application.
图1是本申请实施例中时间测量电路的结构示意图。Figure 1 is a schematic structural diagram of a time measurement circuit in an embodiment of the present application.
图2是本申请实施例中信号选择输出模块的示意图。Figure 2 is a schematic diagram of the signal selection output module in the embodiment of the present application.
图3是本申请实施例中信号选择输出模块的另一示意图。Figure 3 is another schematic diagram of the signal selection output module in the embodiment of the present application.
图4是本申请实施例中时间测量模块的示意图。Figure 4 is a schematic diagram of the time measurement module in the embodiment of the present application.
图5是本申请实施例中时间测量电路的另一种结构示意图。FIG. 5 is another structural schematic diagram of a time measurement circuit in an embodiment of the present application.
图6是本申请实施例中时间测量电路的一种示意图。Figure 6 is a schematic diagram of a time measurement circuit in an embodiment of the present application.
图7是本申请实施例中时间测量电路的另一种示意图。FIG. 7 is another schematic diagram of the time measurement circuit in the embodiment of the present application.
图8是本申请实施例中时间测量方法的流程示意图。Figure 8 is a schematic flowchart of a time measurement method in an embodiment of the present application.
图9是本申请实施例中时间测量方法中获取第一信号和第二信号时间间隔的波形示意图。Figure 9 is a schematic waveform diagram of obtaining the time interval between the first signal and the second signal in the time measurement method in the embodiment of the present application.
图10是本申请实施例中时间测量方法中获取时间测量精度的波形示意图。Figure 10 is a schematic waveform diagram for obtaining time measurement accuracy in the time measurement method in the embodiment of the present application.
图11是本申请实施例中时间测量方法中获取第一信号上升沿与锁存第一信号上升沿之间时间间隔的波形示意图。FIG. 11 is a schematic waveform diagram of the time interval between acquiring the rising edge of the first signal and latching the rising edge of the first signal in the time measurement method in the embodiment of the present application.
图12是本申请实施例的时间测量芯片的结构示意图。Figure 12 is a schematic structural diagram of a time measurement chip according to an embodiment of the present application.
图13是本申请实施例的时间测量模组的结构示意图。Figure 13 is a schematic structural diagram of a time measurement module according to an embodiment of the present application.
具体实施方式Detailed ways
下面将详细描述本申请的各个方面的特征和示例性实施例，为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细描述。应理解，此处所描述的具体实施例仅被配置为解释本申请，并不被配置为限定本申请。对于本领域技术人员来说，本申请可以在不需要这些具体细节中的一些细节的情况下实施。下面对实施例的描述仅仅是为了通过示出本申请的示例来提供对本申请更好的理解。Features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions, and advantages of the present application clearer, the present application will be described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof.
需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that these entities or operations are mutually exclusive. any such actual relationship or sequence exists between them. Furthermore, the terms "comprises," "comprises," or any other variations thereof are intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also those not expressly listed other elements, or elements inherent to the process, method, article or equipment. Without further limitation, an element defined by the statement "comprising..." does not exclude the presence of additional identical elements in a process, method, article, or device that includes the stated element.
实施例一Embodiment 1
请参见图1，图1是本申请实施例中时间测量电路的结构示意图。如图1所示，本申请实施例提供了一种时间测量电路10，该时间测量电路10包括：信号选择输出模块11和时间测量模块12。Please refer to Figure 1, which is a schematic structural diagram of a time measurement circuit in an embodiment of the present application. As shown in FIG. 1 , an embodiment of the present application provides a time measurement circuit 10 . The time measurement circuit 10 includes: a signal selection output module 11 and a time measurement module 12 .
信号选择输出模块11，用于接收第一信号、第二信号和参考时钟信号，并选择输出的测量信号，其中，测量信号为第一信号、第二信号、参考时钟信号以及调整后的参考时钟信号中的一种。第一信号、第二信号可以是如低电平-高电平的上升沿信号，也可以是如低电平-高电平-低电平的脉冲信号。在一些实施例中，第一信号为TOF(Time Of Flight，飞行时间)测距模组发射端发出的经过模数转换后的Start信号，第二信号为TOF测距模组接收端接收的经过模数转换后的Stop信号。可选地，在其他一些实施例中，第一信号也可以为上述Stop信号，第二信号也可以为上述Start信号，本申请对此不作具体限定。参考时钟信号可以是多相位环形振荡器产生的高频脉冲信号，也可以是其它信号，本申请对此不作限定。信号选择输出模块11的接收端将接收第一信号、第二信号和参考时钟信号，并且选择第一信号、第二信号、参考时钟信号或者经过调整后的参考时钟信号中的任一种信号输出至时间测量模块12。The signal selection output module 11 is used to receive the first signal, the second signal and the reference clock signal, and select the output measurement signal, where the measurement signal is the first signal, the second signal, the reference clock signal and the adjusted reference clock. A type of signal. The first signal and the second signal may be a rising edge signal such as low level-high level, or may be a pulse signal such as low level-high level-low level. In some embodiments, the first signal is an analog-to-digital converted Start signal sent by the TOF (Time Of Flight) ranging module transmitter, and the second signal is the process received by the TOF ranging module receiving end. Stop signal after analog-to-digital conversion. Optionally, in some other embodiments, the first signal may also be the above-mentioned Stop signal, and the second signal may also be the above-mentioned Start signal, which is not specifically limited in this application. The reference clock signal may be a high-frequency pulse signal generated by a multi-phase ring oscillator or other signals, which is not limited in this application. The receiving end of the signal selection output module 11 will receive the first signal, the second signal and the reference clock signal, and select any one of the first signal, the second signal, the reference clock signal or the adjusted reference clock signal to output. to time measurement module 12.
时间测量模块12，用于校准时间测量精度，并测量所述第一信号和所述第二信号之间的时间间隔。当时间测量模块12接收到的信号为参考时钟信号或者是调整后的参考时钟信号时，则进行时间测量精度测量或校准；当接收到的信号先是第一信号再是第二信号时，或者先是第二信号再是第一信号时，则进行第一信号和第二信号之间时间间隔的测量。本申请可以在测量之前的空闲状态下实时进行校准分辨率(测量精度)，减少不同环境温度等带来的误差影响。The time measurement module 12 is used to calibrate the time measurement accuracy and measure the time interval between the first signal and the second signal. When the signal received by the time measurement module 12 is a reference clock signal or an adjusted reference clock signal, time measurement accuracy measurement or calibration is performed; when the received signal is first the first signal and then the second signal, or first When the second signal is the first signal, the time interval between the first signal and the second signal is measured. This application can calibrate the resolution (measurement accuracy) in real time in the idle state before measurement, reducing the impact of errors caused by different ambient temperatures.
在一个实施例中，如图2所示，信号选择输出模块11包括：第一选择单元111和第二选择单元112，其中，第一选择单元111例如为逻辑电路中的两输入或门，当然也可以是其它具有信号选择输入功能的电路，第一选择单元111的两个输入端分别用于接收第一信号和第二信号，第一选择单元111的输出端用于连接第二选择单元112的输入端。In one embodiment, as shown in FIG. 2 , the signal selection output module 11 includes: a first selection unit 111 and a second selection unit 112 , where the first selection unit 111 is, for example, a two-input OR gate in a logic circuit. Of course, It can also be another circuit with a signal selection input function. The two input terminals of the first selection unit 111 are used to receive the first signal and the second signal respectively, and the output terminal of the first selection unit 111 is used to connect to the second selection unit 112. input terminal.
第二选择单元112例如为逻辑电路中的两输入或门，当然也可以是其它具有信号选择输入功能的电路，第二选择单元112的一个输入端连接第一选择单元111的输出端，第二选择单元112的另一个输入端接收参考时钟信号，第二选择单元112的输出端连接延时链的第一延时单元(I1)的输入端。The second selection unit 112 is, for example, a two-input OR gate in a logic circuit. Of course, it can also be another circuit with a signal selection input function. One input end of the second selection unit 112 is connected to the output end of the first selection unit 111. The other input terminal of the selection unit 112 receives the reference clock signal, and the output terminal of the second selection unit 112 is connected to the input terminal of the first delay unit (I1) of the delay chain.
在一些实施例中，如图3所示，信号选择输出模块11包括：第一选择单元111、第二选择单元112、正负脉冲发生单元114和调度单元113。其中，第一选择单元111和第二选择单元112请参见前面对图2的描述，在此不再赘述。不同之处在于，正负脉冲发生单元114的输入端接收参考时钟信号，正负脉冲发生单元114的输出端连接第二选择单元112的其中一个输入端。正负脉冲发生单元114用于将参考时钟信号调整为正单周期时钟信号或负单周期时钟信号。本申请通过同时实时地使用正单周期时钟信号(正脉冲信号)和负单周期时钟信号(负脉冲信号)对反相器延时链进行校准，以计算出单个反相器的延时值相对于单个参考时钟信号周期的比例，减少单独使用正脉冲或者负脉冲电路响应误差累积的影响。In some embodiments, as shown in FIG. 3 , the signal selection output module 11 includes: a first selection unit 111 , a second selection unit 112 , a positive and negative pulse generating unit 114 and a scheduling unit 113 . For the first selection unit 111 and the second selection unit 112, please refer to the previous description of FIG. 2 and will not be described again here. The difference is that the input terminal of the positive and negative pulse generating unit 114 receives the reference clock signal, and the output terminal of the positive and negative pulse generating unit 114 is connected to one of the input terminals of the second selection unit 112 . The positive and negative pulse generating unit 114 is used to adjust the reference clock signal into a positive single-cycle clock signal or a negative single-cycle clock signal. This application calibrates the inverter delay chain by simultaneously using a positive single-cycle clock signal (positive pulse signal) and a negative single-cycle clock signal (negative pulse signal) in real time to calculate the relative delay value of a single inverter. The ratio to the period of a single reference clock signal reduces the impact of accumulated response errors using positive or negative pulse circuits alone.
所述调度单元113用于控制所述正负脉冲发生单元114将输入的所述参考时钟信号调整为所述正单周期时钟信号或所述负单周期时钟信号。将正单周期时钟信号和负单周期时钟信号循环若干次输入到时间测量模块12中，可以对时间测量精度进行校准，获得更精确的时间测量精度，提高测量信号时间测量结果的准确性。The scheduling unit 113 is used to control the positive and negative pulse generating unit 114 to adjust the input reference clock signal to the positive single-cycle clock signal or the negative single-cycle clock signal. By inputting the positive single-cycle clock signal and the negative single-cycle clock signal into the time measurement module 12 several times, the time measurement accuracy can be calibrated, a more accurate time measurement accuracy can be obtained, and the accuracy of the measurement signal time measurement results can be improved.
在一个实施例中，如图4所示，时间测量模块12包括延时链121和锁存模块122，其中，延时链121用于从所述信号选择输出模块11接收所述测量信号，延时链121包括n个延时单元(I1-In)，延时链121的第一延时单元I1与信号选择输出模块11的输出端相连，并将测量信号的上升沿从第一延时单元I1顺序传递至延时链121的第n延时单元In，其中n为大于2的正整数；In one embodiment, as shown in Figure 4, the time measurement module 12 includes a delay chain 121 and a latch module 122, wherein the delay chain 121 is used to receive the measurement signal from the signal selection output module 11, and the delay chain 121 is used to receive the measurement signal from the signal selection output module 11. The time chain 121 includes n delay units (I1 -In). The first delay unit I1 of the delay chain 121 is connected to the output end of the signal selection output module 11 and transfers the rising edge of the measurement signal from the first delay unit I 1 to the output terminal of the signal selection output module 11 . The time unit I1 is sequentially transferred to the nth delay unit In of the delay chain 121, where n is a positive integer greater than 2;
锁存模块122则用于锁存延时链121的输出信号，锁存模块122包括n个锁存单元(D1-Dn)，其中，n个锁存单元(D1-Dn)均包括两个输入端，每一锁存单元的一个输入端与一个延时单元的输出端相连，另一个输入端则用于接收参考时钟信号。The latch module 122 is used to latch the output signal of the delay chain 121. The latch module 122 includes n latch units (D1-Dn), wherein each of the n latch units (D1-Dn) includes two inputs. terminal, one input terminal of each latch unit is connected to the output terminal of a delay unit, and the other input terminal is used to receive the reference clock signal.
采用延时链121和锁存模块122进行时间测量的原理是使被测信号(上升沿信号)通过延时链121进行传输，在被测信号的上升沿之后的第一个参考时钟信号的上升沿触发锁存模块122锁存延时链121的状态值，获取延时链121的输出信号可以得到被测信号与所述被测信号信上升沿之后的第一个参考时钟信号的上升沿之间的时间差值，每一个延时单元之间的信号延迟时间就是测量的分辨率。The principle of using the delay chain 121 and the latch module 122 for time measurement is to transmit the measured signal (rising edge signal) through the delay chain 121. The rising edge of the first reference clock signal after the rising edge of the measured signal The edge trigger latch module 122 latches the state value of the delay chain 121. Obtaining the output signal of the delay chain 121 can obtain the rising edge of the measured signal and the first reference clock signal after the rising edge of the measured signal signal. The time difference between them, the signal delay time between each delay unit is the measurement resolution.
在一个实施例中，延时链121包括若干延时单元，延时单元优选为反相器。目前反相器的制造工艺可以做到40nm级别，在此制造工艺下反相器的延迟最小可以达到30ps左右，因为整个时间测量电路的分辨率(精度)取决于延时单元的延时，因此使用反相器可以使时间测量的精度达到30ps左右。在一些实施例中，也可以选用Buffer单元，不过因为Buffer单元对信号上升沿或下降沿有不同的响应延时，由此影响测量结果，而选用反相器则可以避免这个问题。In one embodiment, the delay chain 121 includes several delay units, and the delay units are preferably inverters. The current manufacturing process of the inverter can reach the 40nm level. Under this manufacturing process, the minimum delay of the inverter can reach about 30ps, because the resolution (accuracy) of the entire time measurement circuit depends on the delay of the delay unit, so Using an inverter can make the time measurement accuracy reach about 30ps. In some embodiments, a Buffer unit can also be selected. However, the Buffer unit has different response delays to the rising or falling edges of the signal, thus affecting the measurement results. This problem can be avoided by using an inverter.
在一个实施例中，锁存模块122中的锁存单元为D触发器，D触发器的一个输入端连接延时单元的输出端，另一个输入端接收参考时钟信号，并被配置为在一个预设的参考时钟信号上升沿的时候锁存延时单元的状态值，或者根据这些延时单元的状态值就可以得知沿延时链传递的测量信号与预设的参考时钟信号上升沿之间的时间延时。In one embodiment, the latch unit in the latch module 122 is a D flip-flop. One input terminal of the D flip-flop is connected to the output terminal of the delay unit, and the other input terminal receives the reference clock signal and is configured to operate on a The state value of the delay unit is latched at the rising edge of the preset reference clock signal, or based on the state values of these delay units, the relationship between the measurement signal transmitted along the delay chain and the rising edge of the preset reference clock signal can be known. time delay between.
在一个实施例中，如图5所示，时间测量电路10还包括译码模块13，译码模块13与时间测量模块12中的锁存模块122相连，用于将锁存模块122的输出转换为便于读取的二进制数据。In one embodiment, as shown in Figure 5, the time measurement circuit 10 also includes a decoding module 13. The decoding module 13 is connected to the latch module 122 in the time measurement module 12 and is used to convert the output of the latch module 122. Binary data for easy reading.
优选地，时间测量电路10的结构示意图如图6所示，信号选择输出模块11中的第一选择单元111的两个输入端分别接收第一信号和第二信号，第一选择单元111的输出端连接第二选择单元112的输入端；第二选择单元112的一个输入端连接第一选择单元111的输出端，第二选择单元112的另一个输入端接收参考时钟信号，第二选择单元112的输出端连接延时链121的第一延时单元I1的输入端。延时链121包括了n个延时单元(I1-In)，同样，锁存模块122包括了n个锁存单元(D1-Dn)，延时链121中每一个延时单元的输出端都与锁存模块122中的一个锁存单元的一个输入端相连，锁存模块122中每一个锁存单元的输出端都连接到译码模块13中。Preferably, the structural schematic diagram of the time measurement circuit 10 is shown in Figure 6. The two input terminals of the first selection unit 111 in the signal selection output module 11 receive the first signal and the second signal respectively, and the output of the first selection unit 111 The terminal is connected to the input terminal of the second selection unit 112; one input terminal of the second selection unit 112 is connected to the output terminal of the first selection unit 111, and the other input terminal of the second selection unit 112 receives the reference clock signal. The second selection unit 112 The output terminal of is connected to the input terminal of the first delay unit I1 of the delay chain 121 . The delay chain 121 includes n delay units (I1 -In ). Similarly, the latch module 122 includes n latch units (D1 -Dn ). Each delay unit in the delay chain 121 The output terminals are connected to an input terminal of a latch unit in the latch module 122 , and the output terminal of each latch unit in the latch module 122 is connected to the decoding module 13 .
优选地，时间测量电路10的结构示意图如图7所示，信号选择输出模块11中的第一选择单元111的两个输入端分别接收第一信号和第二信号，第一选择单元111的输出端连接第二选择单元112的一个输入端；正负脉冲发生单元114的输入端接收参考时钟信号，正负脉冲发生单元114的输出端连接第二选择单元112的另一个输入端；第二选择单元112的输出端连接延时链121的第一延时单元I1的输入端。延时链121包括了n个延时单元，同样，锁存模块122包括了n个锁存单元，延时链121中每一个延时单元的输出端都与锁存模块122中的一个D触发器的一个输入端相连，锁存模块122中每一个锁存单元的输出端都连接到译码模块13中。Preferably, the structural schematic diagram of the time measurement circuit 10 is shown in Figure 7. The two input terminals of the first selection unit 111 in the signal selection output module 11 receive the first signal and the second signal respectively, and the output of the first selection unit 111 terminal is connected to one input terminal of the second selection unit 112; the input terminal of the positive and negative pulse generating unit 114 receives the reference clock signal, and the output terminal of the positive and negative pulse generating unit 114 is connected to the other input terminal of the second selection unit 112; the second selection The output terminal of the unit 112 is connected to the input terminal of the first delay unit I1 of the delay chain 121 . The delay chain 121 includes n delay units. Similarly, the latch module 122 includes n latch units. The output end of each delay unit in the delay chain 121 is triggered by a D in the latch module 122. One input end of the latch unit is connected to the latch module 122 , and the output end of each latch unit in the latch module 122 is connected to the decoding module 13 .
此外需要说明的是，在本申请实施例中对n的取值可以根据对时间测量模块12的测量精度需求而定，在此不做具体限定。In addition, it should be noted that in the embodiment of the present application, the value of n can be determined according to the measurement accuracy requirements of the time measurement module 12, and is not specifically limited here.
另外，时间测量电路10可以是专用的集成电路，该电路10例如可以集成在现场可编程门阵列(FPGA)芯片中，也可以集成在专用集成电路(ASIC)芯片中，本申请实施例对此不做具体限定。In addition, the time measurement circuit 10 may be a dedicated integrated circuit. For example, the circuit 10 may be integrated in a field programmable gate array (FPGA) chip or an application specific integrated circuit (ASIC) chip. This is the case in the embodiment of the present application. No specific restrictions are made.
上文结合图1至图7，详细描述了本申请的时间测量电路的实施例，下面结合图8、图9和图10，详细描述基于上述时间测量电路，提出的一种时间测量方法的实施例。应理解，本申请的方法实施例的描述与装置实施例的描述相互对应，因此，未详细描述的部分可以参见前面时间测量电路的实施例。The embodiments of the time measurement circuit of the present application are described in detail above with reference to Figures 1 to 7. The implementation of a time measurement method proposed based on the above time measurement circuit is described in detail below with reference to Figures 8, 9 and 10. example. It should be understood that the description of the method embodiments of the present application corresponds to the description of the device embodiments. Therefore, for parts not described in detail, reference can be made to the previous embodiments of the time measurement circuit.
实施例二Embodiment 2
请参阅图8为本申请实施例提供的时间测量方法流程示意图，所述方法基于上述时间测量电路来实现，包括以下步骤：Please refer to Figure 8 for a schematic flow chart of a time measurement method provided by an embodiment of the present application. The method is implemented based on the above time measurement circuit and includes the following steps:
S1：获取时间测量电路的测量精度；S1: Obtain the measurement accuracy of the time measurement circuit;
S2：根据所述测量精度，获取第一信号上升沿和第一信号上升沿之后的首个参考时钟信号的上升沿之间的时间间隔，记为第一时间间隔；S2: According to the measurement accuracy, obtain the time interval between the rising edge of the first signal and the rising edge of the first reference clock signal after the rising edge of the first signal, and record it as the first time interval;
S3：根据所述测量精度，获取第二信号上升沿和第二信号上升沿之后的首个参考时钟信号的上升沿之间的时间间隔，记为第二时间间隔，同时获取第一信号上升沿之后的首个参考时钟信号的上升沿和第二信号上升沿之后的首个参考时钟信号的上升沿之间的参考时钟周期个数；S3: According to the measurement accuracy, obtain the time interval between the rising edge of the second signal and the rising edge of the first reference clock signal after the rising edge of the second signal, record it as the second time interval, and obtain the rising edge of the first signal at the same time The number of reference clock cycles between the rising edge of the first subsequent reference clock signal and the rising edge of the first reference clock signal following the rising edge of the second signal;
S4：根据所述第一时间间隔、第二时间间隔和所述参考时钟周期个数，获取所述第一信号和第二信号之间的时间间隔。S4: Obtain the time interval between the first signal and the second signal according to the first time interval, the second time interval and the number of reference clock cycles.
采用本申请实施例进行第一信号和第二信号之间间隔时间的测量原理如图9所示，第一信号和第二信号之间的延时时间可以用以下公式(1)计算：The principle of measuring the interval time between the first signal and the second signal using the embodiment of the present application is shown in Figure 9. The delay time between the first signal and the second signal can be calculated using the following formula (1):
△T＝N×Tclk+△Ta-△Tb (1)△T＝N×Tclk+△Ta-△Tb (1)
上述公式(1)中，△T为第一信号上升沿和第二信号上升沿之间的时间差，Tclk为参考时钟信号的时钟周期，N为第一信号和第二信号之间相差的参考时钟信号的周期个数，△Ta为第一信号上升沿与第一信号上升沿之后的第一个参考时钟信号上升沿之间的时间差，△Tb为第二信号上升沿与第二信号上升沿之后的第一个参考时钟上升沿之间的时间差。In the above formula (1), △T is the time difference between the rising edge of the first signal and the rising edge of the second signal, Tclk is the clock period of the reference clock signal, and N is the reference clock difference between the first signal and the second signal. The number of cycles of the signal, △Ta is the time difference between the rising edge of the first signal and the rising edge of the first reference clock signal after the rising edge of the first signal, △Tb is the rising edge of the second signal and after the rising edge of the second signal The time difference between the rising edges of the first reference clock.
在一个实施例中，采用如图6所述的时间测量电路进行第一信号和第二信号之间延时时间的测量。因为时间测量电路测量精度(即测量分辨率)取决于延时单元的延时大小，记一个延时单元的延时大小为单位延时Tinv，计算△T之前，首先计算Tinv的大小。如图6中信号选择输出模块11选择将参考时钟信号输入至延时链121中，同时在锁存模块122中输入所述参考时钟信号，如图10所示，参考时钟信号的第一个时钟上升沿从延时链中第一延时单元顺序传递至所述延时链的第n延时单元，每传递过一个延时单元第一个时钟上升沿相应产生一个单位延时。锁存模块122则在输入的参考时钟信号的第二个时钟上升沿到来时锁存相应延时单元的状态值，通过译码模块13获取在一个时钟周期内第一个时钟上升沿经延时链顺序传递对应产生的单位延时个数K，记为时钟周期模值计数，其中K为大于0的整数，那么得出以下公式(2)In one embodiment, the time measurement circuit as shown in Figure 6 is used to measure the delay time between the first signal and the second signal. Because the measurement accuracy (i.e., measurement resolution) of the time measurement circuit depends on the delay size of the delay unit, the delay size of a delay unit is recorded as the unit delay Tinv. Before calculating △T, first calculate the size of Tinv. As shown in Figure 6, the signal selection output module 11 selects to input the reference clock signal into the delay chain 121, and at the same time inputs the reference clock signal into the latch module 122. As shown in Figure 10, the first clock of the reference clock signal The rising edge is sequentially transmitted from the first delay unit in the delay chain to the nth delay unit of the delay chain. Each time a rising edge of the first clock is passed through a delay unit, a unit delay is generated accordingly. The latch module 122 latches the status value of the corresponding delay unit when the second clock rising edge of the input reference clock signal arrives, and obtains the delayed first clock rising edge in one clock cycle through the decoding module 13 The number of unit delays K corresponding to chain sequential transmission is recorded as the clock cycle modulus count, where K is an integer greater than 0, then the following formula (2) is obtained
在一些实施例中，将参考时钟信号的第i个上升沿输入到延时链中，锁存单元在参考时钟信号的第j个上升沿到来时锁存延时单元的状态值，其中，i和j均为大于等于1的自然数。通过译码模块13获取一个时钟周期内参考时钟信号第i个上升沿对应产生的单位延时个数K’，其中K’为大于0的整数，那么得出公式(2’)如下：In some embodiments, the i-th rising edge of the reference clock signal is input into the delay chain, and the latch unit latches the state value of the delay unit when the j-th rising edge of the reference clock signal arrives, where, i and j are both natural numbers greater than or equal to 1. The number of unit delays K’ generated corresponding to the i-th rising edge of the reference clock signal in one clock cycle is obtained through the decoding module 13, where K’ is an integer greater than 0, then the formula (2’) is obtained as follows:
获取到Tinv之后，再分别获取△Ta和△Tb的值。After obtaining Tinv, obtain the values of △Ta and △Tb respectively.
在测量△Ta时信号选择输出模块11输出第一信号至延时链121的输入端，锁存模块122接入参考时钟信号，如图11所示，在第一信号上升沿之后的第一个参考时钟信号上升沿(锁存上升沿)到来时锁存延时链121状态值，通过译码模块13得到第一信号上升沿到第一信号上升沿之后的第一个参考时钟信号上升沿之间的单位延时个数A。When measuring ΔTa, the signal selection output module 11 outputs the first signal to the input end of the delay chain 121, and the latch module 122 accesses the reference clock signal. As shown in Figure 11, the first signal after the rising edge of the first signal When the rising edge of the reference clock signal (latch rising edge) arrives, the status value of the latch delay chain 121 is obtained, and the value between the first rising edge of the signal and the first rising edge of the reference clock signal after the first rising edge is obtained through the decoding module 13 The number of unit delays between A.
根据公式(2)可以得到下面的公式(3)：According to formula (2), the following formula (3) can be obtained:
同样的，在测量△Tb时，信号选择输出模块11输出第二信号至延时链121的输入端，锁存模块122接入参考时钟信号，并在第二信号上升沿之后的第一个参考时钟信号上升沿时锁存延时链121状态值，通过译码模块13得到第二信号上升沿到第二信号上升沿之后的第一个参考时钟信号上升沿之间的单位延时个数B。Similarly, when measuring ΔTb, the signal selection output module 11 outputs the second signal to the input end of the delay chain 121, the latch module 122 accesses the reference clock signal, and the first reference signal after the rising edge of the second signal The delay chain 121 status value is latched at the rising edge of the clock signal, and the unit delay number B between the rising edge of the second signal and the rising edge of the first reference clock signal after the rising edge of the second signal is obtained through the decoding module 13 .
根据公式(2)可以得到下面的公式(4)：According to formula (2), the following formula (4) can be obtained:
此外，在测量△Tb时，可以得到第一信号和第二信号之间的间隔时间包括的整数个时钟周期计数N，根据公式(1)(2)(3)(4)可得下面的公式(5)：In addition, when measuring △Tb, the integer clock cycle count N included in the interval between the first signal and the second signal can be obtained. According to the formula (1) (2) (3) (4), the following formula can be obtained (5):
参考时钟信号可以是一正脉冲信号或者是一负脉冲信号，需要指出的是，由于制备工艺或环境因素的影响每个延时单元不可避免会有响应误差，为了减小单独使用同一正脉冲信号或负脉冲信号时响应误差累积的影响，如图7所示的本申请的另一个实施例通过正负脉冲发生单元114将参考时钟信号调整为正单周期时钟信号或负单周期时钟信号，并循环若干次使用所述正单周期时钟信号和负正周期时钟信号对时间测量电路的分辨率进行校准。具体的校准过程如下：The reference clock signal can be a positive pulse signal or a negative pulse signal. It should be pointed out that due to the influence of the preparation process or environmental factors, each delay unit will inevitably have a response error. In order to reduce the risk of using the same positive pulse signal alone, Or the influence of response error accumulation when there is a negative pulse signal. As shown in FIG. 7, another embodiment of the present application adjusts the reference clock signal to a positive single-cycle clock signal or a negative single-cycle clock signal through the positive and negative pulse generating unit 114, and The positive single-cycle clock signal and the negative positive-cycle clock signal are used in several cycles to calibrate the resolution of the time measurement circuit. The specific calibration process is as follows:
S101：输入正单周期时钟信号，获取正单周期时钟信号的第一时钟周期模值计数Np；S101: Input a positive single-cycle clock signal, and obtain the modulus count Np of the first clock cycle of the positive single-cycle clock signal;
S102：输入负单周期时钟信号，获取负单周期时钟信号的第一时钟周期模值计数Nn；S102: Input a negative single-cycle clock signal, and obtain the first clock cycle modulus count Nn of the negative single-cycle clock signal;
S103：输入正单周期时钟信号，获取正单周期时钟信号的第二时钟周期模值计数Np’；S103: Input a positive single-cycle clock signal and obtain the second clock cycle modulus count Np’ of the positive single-cycle clock signal;
S104：输入负单周期时钟信号，获取负单周期时钟信号的第二时钟周期模值计数Nn’；S104: Input a negative single-cycle clock signal and obtain the second clock cycle modulus count Nn’ of the negative single-cycle clock signal;
S105：当Np＝Np’且Nn＝Nn’时，校准过程结束；S105: When Np=Np’ and Nn=Nn’, the calibration process ends;
当Np≠Np’或Nn≠Nn’时，再次执行步骤S101–步骤S104，直到Np＝Np’且Nn＝Nn’时，校准过程结束；When Np≠Np’ or Nn≠Nn’, perform steps S101 to S104 again until Np=Np’ and Nn=Nn’, the calibration process ends;
当Np≠Np’或Nn≠Nn’时，且执行步骤S101-步骤S104的次数等于预设次数时，同样结束校准过程，以免进入校准过程耗时太长。优选地，预设次数值为8。When Np ≠ Np’ or Nn ≠ Nn’, and the number of times steps S101 to S104 are performed is equal to the preset number of times, the calibration process is also ended to avoid entering the calibration process which takes too long. Preferably, the preset number value is 8.
校准过程结束后，计算K的值，即：After the calibration process is completed, calculate the value of K, namely:
因为Tinv＝Tclk/K，可以得到校准后的测量精度Tinv为：Because Tinv=Tclk/K, the calibrated measurement accuracy Tinv can be obtained as:
在测量△Ta时信号选择输出模块11输出第一信号至延时链121的输入端，锁存模块122接入参考时钟信号，并在第一信号上升沿之后的第一个参考时钟上升沿到来时锁存延时链121状态值，通过译码模块13得到第一信号上升沿到第一信号上升沿之后的第一个参考时钟上升沿之间的单位延时个数A，如图10所示。When measuring ΔTa, the signal selection output module 11 outputs the first signal to the input end of the delay chain 121, the latch module 122 receives the reference clock signal, and the first rising edge of the reference clock after the rising edge of the first signal arrives. When the delay chain 121 status value is latched, the unit delay number A between the rising edge of the first signal and the rising edge of the first reference clock after the rising edge of the first signal is obtained through the decoding module 13, as shown in Figure 10 Show.
根据公式(7)可以得到公式(8)：According to formula (7), formula (8) can be obtained:
同样的，在测量△Tb时，信号选择输出模块11输出第二信号至延时链121的输入端，锁存模块122接入参考时钟信号，并在第二信号上升沿之后的第一个参考时钟上升沿到来时锁存延时链121状态值，通过译码模块13得到第二信号上升沿到第二信号上升沿之后的第一个参考时钟上升沿之间的单位延时个数B。Similarly, when measuring ΔTb, the signal selection output module 11 outputs the second signal to the input end of the delay chain 121, the latch module 122 accesses the reference clock signal, and the first reference signal after the rising edge of the second signal When the rising edge of the clock arrives, the state value of the delay chain 121 is latched, and the unit delay number B between the rising edge of the second signal and the rising edge of the first reference clock after the rising edge of the second signal is obtained through the decoding module 13 .
根据公式(2)可以得到，According to formula (2), we can get,
此外，在测量△Tb时，可以得到第一信号和第二信号之间的间隔时间包括的整数个时钟周期计数N，根据公式(1)(6)(8)(9)可得：In addition, when measuring ΔTb, the integer clock cycle count N included in the interval between the first signal and the second signal can be obtained, according to formula (1) (6) (8) (9):
综上所述，本申请实施例的时间测量电路通过信号选择输出模块11和时间测量模块12实现了时间测量精度的校准和测量信号的时间测量。本申请的实施例一方面通过在延时链121中输入参考时钟信号获取时间测量精度，进一步的，通过正负脉冲发生单元114生成正单周期时钟信号和负单周期时钟信号对时间测量精度进行校准，获取更为准确的时间测量结果。时间测量精度的校准可以在在测量第一信号和第二信号的时间测量之前的空闲状态下进行，即可以提高测量的精度又可以减少不同环境温度等带来的误差影响。另一方面，时间测量电路10通过选取适量的延时单元(I1-In)组成延时链121，以避免用参考时钟信号时间周期整数计数无法覆盖测量时间范围从而造成误差较大的问题。进一步的，通过选用延迟值小的反相器作为延迟单元，使用足够数量的延迟单元，可以对应降低参考时钟信号的频率，达到降低功耗的目的。通过选用反相器而不是Buffer单元以减少由于Buffer单元对信号上升沿和下降沿不同的响应延迟带来的影响，快速实现皮秒级的高精度时间测量，在目前的制造工艺下可以实现30ps左右的测量精度。To sum up, the time measurement circuit of the embodiment of the present application realizes the calibration of time measurement accuracy and the time measurement of the measurement signal through the signal selection output module 11 and the time measurement module 12 . In the embodiment of the present application, on the one hand, the time measurement accuracy is obtained by inputting a reference clock signal into the delay chain 121. Furthermore, the time measurement accuracy is improved by generating a positive single-cycle clock signal and a negative single-cycle clock signal through the positive and negative pulse generating unit 114. Calibrate to obtain more accurate time measurement results. The calibration of the time measurement accuracy can be performed in an idle state before measuring the time of the first signal and the second signal, which can improve the accuracy of the measurement and reduce the impact of errors caused by different ambient temperatures. On the other hand, the time measurement circuit 10 selects an appropriate amount of delay units (I1 -In) to form the delay chain 121 to avoid the problem that the integer count of the time period of the reference clock signal cannot cover the measurement time range, thereby causing a large error. Furthermore, by selecting an inverter with a small delay value as the delay unit and using a sufficient number of delay units, the frequency of the reference clock signal can be correspondingly reduced to achieve the purpose of reducing power consumption. By choosing an inverter instead of a Buffer unit to reduce the impact of the Buffer unit's different response delays to the rising and falling edges of the signal, high-precision time measurement at the picosecond level can be quickly achieved, and 30ps can be achieved under the current manufacturing process. The measurement accuracy is around.
实施例三Embodiment 3
本申请实施例还提供了一种时间测量芯片30。如图12所示，该时间测量芯片30包括上文描述的时间测量电路10以及一模数转换电路31，该模数转换电路用于将芯片接收到的模拟信号转换为数字信号，并输入到时间测量电路10中进行时间测量。关于时间测量电路10的详细描述请参见前面实施例1和2，在此不再赘述。The embodiment of the present application also provides a time measurement chip 30. As shown in Figure 12, the time measurement chip 30 includes the time measurement circuit 10 described above and an analog-to-digital conversion circuit 31. The analog-to-digital conversion circuit is used to convert the analog signal received by the chip into a digital signal and input it to Time measurement is performed in the time measurement circuit 10 . For detailed description of the time measurement circuit 10, please refer to the previous embodiments 1 and 2, and will not be described again here.
实施例四Embodiment 4
本申请实施例还提供一种时间测量模组40。如图13所示，该时间测量模组40包括发射器41、接收器42以及如图13所示的时间测量芯片30。发射器41用于发射检测信号，所述检测信号例如为红外或近红外光信号，或者其它可见光信号。接收器42接收所述检测信号对应的反射信号，反射信号为模拟信号。时间测量芯片30与发射器41和接收器42相连，从发射器41和接收器42接收模拟信号，然后时间测量芯片30将其转换为数字信号，由时间测量电路10测量出发射器41发射的检测信号与接收器42接收到检测信号对应的反射信号的时间间隔，然后根据时间间隔获得目标物的距离。关于时间测量芯片30的描述具体请参见实施例三，在此不再赘述。The embodiment of the present application also provides a time measurement module 40. As shown in FIG. 13 , the time measurement module 40 includes a transmitter 41 , a receiver 42 and a time measurement chip 30 as shown in FIG. 13 . The transmitter 41 is used to transmit a detection signal, which is, for example, an infrared or near-infrared light signal, or other visible light signal. The receiver 42 receives the reflected signal corresponding to the detection signal, and the reflected signal is an analog signal. The time measurement chip 30 is connected to the transmitter 41 and the receiver 42, receives the analog signal from the transmitter 41 and the receiver 42, and then the time measurement chip 30 converts it into a digital signal, and the time measurement circuit 10 measures the signal emitted by the transmitter 41. The time interval between the detection signal and the reflected signal corresponding to the detection signal is received by the receiver 42, and then the distance of the target is obtained based on the time interval. For a detailed description of the time measurement chip 30, please refer to Embodiment 3, which will not be described again here.
实施例五Embodiment 5
本申请实施例还提供一种电子设备，该电子设备包括如实施例四所描述的时间测量模组40。该电子设备可以是智能手机、无人机、可移动机器人、智能电视机、AR/VR、3D深度测量设备等，通过本申请的飞行时间测量模组40，可以实现对目标物体的深度信息的精准测量。An embodiment of the present application also provides an electronic device, which includes the time measurement module 40 described in Embodiment 4. The electronic device can be a smartphone, a drone, a mobile robot, a smart TV, an AR/VR, a 3D depth measurement device, etc. Through the flight time measurement module 40 of the present application, the depth information of the target object can be obtained. Precise measurements.
综上所述，本申请实施例提供的时间测量电路、时间测量方法、时间测量芯片、时间测量模组和电子设备，在时钟频率提升空间有限的现有技术条件下，可以实现皮秒以下的高精度时间测量，在目前普遍的工艺下，可实现30ps左右的测量精度。To sum up, the time measurement circuit, time measurement method, time measurement chip, time measurement module and electronic device provided by the embodiments of the present application can achieve sub-picosecond clock speeds under existing technical conditions with limited room for clock frequency improvement. High-precision time measurement can achieve a measurement accuracy of about 30ps under the current common technology.
需要明确的是，本申请并不局限于上文所描述并在图中示出的特定配置和处理。为了简明起见，这里省略了对已知方法的详细描述。在上述实施例中，描述和示出了若干具体的步骤作为示例。但是，本申请的方法过程并不限于所描述和示出的具体步骤，本领域的技术人员可以在领会本申请的精神后，作出各种改变、修改和添加，或者改变步骤之间的顺序。To be clear, this application is not limited to the specific configurations and processes described above and illustrated in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present application is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications and additions, or change the order between steps after understanding the spirit of the present application.
以上所述的结构框图中所示的功能块可以实现为硬件、软件、固件或者它们的组合。当以硬件方式实现时，其可以例如是电子电路、专用集成电路(ASIC)、适当的固件、插件、功能卡等等。当以软件方式实现时，本申请的元素是被用于执行所需任务的程序或者代码段。程序或者代码段可以存储在机器可读介质中，或者通过载波中携带的数据信号在传输介质或者通信链路上传送。“机器可读介质”可以包括能够存储或传输信息的任何介质。机器可读介质的例子包括电子电路、半导体存储器设备、ROM、闪存、可擦除ROM(EROM)、软盘、CD-ROM、光盘、硬盘、光纤介质、射频(RF)链路，等等。代码段可以经由诸如因特网、内联网等的计算机网络被下载。The functional blocks shown in the above structural block diagram can be implemented as hardware, software, firmware or a combination thereof. When implemented in hardware, it may be, for example, an electronic circuit, an application specific integrated circuit (ASIC), appropriate firmware, a plug-in, a function card, or the like. When implemented in software, elements of the application are programs or code segments that are used to perform the required tasks. The program or code segments may be stored in a machine-readable medium or transmitted over a transmission medium or communications link via a data signal carried in a carrier wave. "Machine-readable medium" may include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links, and the like. Code segments may be downloaded via computer networks such as the Internet, intranets, and the like.
还需要说明的是，本申请中提及的示例性实施例，基于一系列的步骤或者装置描述一些方法或系统。但是，本申请不局限于上述步骤的顺序，也就是说，可以按照实施例中提及的顺序执行步骤，也可以不同于实施例中的顺序，或者若干步骤同时执行。It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, the present application is not limited to the order of the above steps. That is to say, the steps may be performed in the order mentioned in the embodiment, or may be different from the order in the embodiment, or several steps may be performed simultaneously.
以上所述，仅为本申请的具体实施方式，所属领域的技术人员可以清楚地了解到，为了描述的方便和简洁，上述描述的系统、模块和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。应理解，本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到各种等效的修改或替换，这些修改或替换都应涵盖在本申请的保护范围之内。The above are only specific implementation modes of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the above-described systems, modules and units can be referred to the foregoing method embodiments. The corresponding process will not be described again here. It should be understood that the protection scope of the present application is not limited thereto. Any person familiar with the technical field can easily think of various equivalent modifications or substitutions within the technical scope disclosed in the present application, and these modifications or substitutions should be covered. within the protection scope of this application.
| Application Number | Priority Date | Filing Date | Title |
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| CN2021105077781 | 2021-05-10 | ||
| CN202110507778 | 2021-05-10 |
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| CN202210497618.8AActiveCN114779607B (en) | 2021-05-10 | 2022-05-09 | Time measurement circuit, time measurement method, time measurement chip, time measurement module and electronic equipment |
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