CN114756496A - Data reading method and system of EEPROM chip, air conditioner and storage medium - Google Patents
Data reading method and system of EEPROM chip, air conditioner and storage mediumDownload PDFInfo
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- CN114756496A CN114756496ACN202210238205.8ACN202210238205ACN114756496ACN 114756496 ACN114756496 ACN 114756496ACN 202210238205 ACN202210238205 ACN 202210238205ACN 114756496 ACN114756496 ACN 114756496A
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F24—HEATING; RANGES; VENTILATING
- F24F—AIR-CONDITIONING; AIR-HUMIDIFICATION; VENTILATION; USE OF AIR CURRENTS FOR SCREENING
- F24F11/00—Control or safety arrangements
- F24F11/88—Electrical aspects, e.g. circuits
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
Description
Technical Field
The present disclosure relates to the field of Inter-Integrated Circuit (IIC) communication technologies, and in particular, to a data reading method and system for an EEPROM chip, an air conditioner, and a storage medium.
Background
EEPROM (electrically erasable programmable read only memory) chips are used in many fields, such as electronic product fields of air conditioners, automobiles, and the like, and other fields of storage, transportation, and the like. At present, most variable frequency air conditioners are provided with EEPROM chips, and the EEPROM chips (called E side for short) store the operation parameter data of an air conditioner controller.
The EEPROM chip is generally electrically connected to an IIC host device (such as an MCU) through an IIC bus, and the IIC host device establishes communication with the EEPROM chip through the IIC bus to read data of the EEPROM chip, but when the IIC bus is in an abnormal communication, data of the EEPROM chip read by the IIC host device may be erroneous.
Disclosure of Invention
The embodiment of the application provides a data reading method and system of an EEPROM chip, an air conditioner and a storage medium, and the data reading accuracy of the EEPROM chip can be improved.
The embodiment of the application provides a data reading method of an EEPROM chip, which comprises the following steps:
the IIC bus is controlled to read data of the EEPROM chip at a first transmission rate to obtain first data;
judging whether the first data is correct or not;
and if the data of the EEPROM chip is wrong, controlling the IIC bus to read the data of the EEPROM chip by adopting a second transmission rate to obtain second data, wherein the second transmission rate is greater than the first transmission rate.
Optionally, the step of determining whether the first data is correct includes:
processing the first data to obtain a first check code;
comparing the first check code with a target check code pre-stored in the EEPROM chip;
If the first check code is the same as the target check code, judging that the first data is correct;
and if the first check code is different from the target check code, judging that the first data is wrong.
Optionally, if the data of the EEPROM chip is read by controlling the IIC bus at a second transmission rate to obtain second data, where the transmission rate of the second transmission rate is greater than the transmission rate of the first transmission rate, and then the method includes:
judging whether the second data is correct or not;
if the voltage is wrong, setting the transmission rate of the IIC bus to be more than 100Kbit/s and less than or equal to 400Kbit/s, and setting the ratio of the high level to the low level of the serial clock line in the IIC bus to be Tlow/Thigh-2, wherein Tlow represents the duration of the low level, and Thigh represents the duration of the high level;
and reading the data of the EEPROM chip through the set IIC bus to obtain third data.
Optionally, after reading the data of the EEPROM chip through the set IIC bus to obtain third data, the method further includes:
judging whether the third data is correct or not;
if the voltage is wrong, the transmission speed of the IIC bus is set to be larger than 100Kbit/s and smaller than or equal to 400Kbit/s, and the ratio of the high level to the low level of the serial clock line is set to be Tlow/Thigh which is 16/9;
And reading the data of the EEPROM chip through the set IIC bus to obtain fourth data.
Optionally, reading the data of the EEPROM chip through the set IIC bus to obtain fourth data includes:
judging whether the fourth data is correct or not;
and if the fourth data is wrong, determining the IIC bus communication fault.
Optionally, if the error occurs, reading the data of the EEPROM chip through the IIC bus at a second transmission rate to obtain second data, where the transmission rate of the second transmission rate is greater than the transmission rate of the first transmission rate, and then:
judging whether the second data is correct or not;
if the serial clock line is wrong, setting the transmission rate of the IIC bus to be more than 100Kbit/s and less than or equal to 400Kbit/s, and setting the high-low level ratio of the serial clock line to be Tlow/Thigh-2;
and reading the data of the EEPROM chip through the set IIC bus to obtain fourth data.
Optionally, if the error occurs, controlling the IIC bus to read the data of the EEPROM chip at a second transmission rate to obtain second data, where the transmission rate of the second transmission rate is greater than the transmission rate of the first transmission rate, and then the method includes:
Judging whether the second data is correct or not;
if the serial clock line is wrong, setting the transmission rate of the IIC bus to be more than 100Kbit/s and less than or equal to 400Kbit/s, and setting the high-low level ratio of the serial clock line to be Tlow/Thigh to be 16/9;
reading the data of the EEPROM chip through the set IIC bus to obtain fourth data;
judging whether the fourth data is correct or not;
if the serial clock line is wrong, setting the transmission rate of the IIC bus to be more than 100Kbit/s and less than or equal to 400Kbit/s, and setting the high-low level ratio of the serial clock line to be Tlow/Thigh-2;
and reading the data of the EEPROM chip through the set IIC bus to obtain third data.
Optionally, the transmission rate of the first transmission rate is equal to or less than 100Kbit/s, and the transmission rate of the second transmission rate is equal to or greater than 3.4 Mbit/s.
The embodiment of the present application provides a data reading system of an EEPROM chip, including:
the IIC bus comprises a serial clock line and a serial data line;
the IIC master equipment comprises a first serial clock interface and a first serial data interface, wherein the first serial clock interface is connected with one end of the serial clock line, and the first serial data interface is connected with one end of the serial data line;
The EEPROM chip comprises a second serial clock interface and a second serial data interface, the second serial clock interface is connected with the other end of the serial clock line, and the second serial data interface is connected with one end of the serial data line;
the IIC master device reads the data of the EEPROM chip according to the data reading method of the EEPROM chip.
The embodiment of the application provides an air conditioner, which comprises the data reading system of the EEPROM chip.
The embodiment of the application provides a computer-readable storage medium, on which a computer program is stored, and the computer program, when executed by a processor, implements the data reading method of the EEPROM chip as described above.
According to the embodiment of the application, when the data reading of the EEPROM chip is abnormal, the data reading of the EEPROM chip is carried out again in a mode of switching the transmission rate of the IIC bus, and the accuracy of reading the data of the EEPROM chip is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings used in the description of the embodiments will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
Fig. 1 is a first flowchart illustrating a data reading method of an EEPROM chip according to an embodiment of the present disclosure.
Fig. 2 is a data reading system of an EEPROM chip according to an embodiment of the present application.
Fig. 3 is a schematic flowchart of a data reading method of an EEPROM chip according to an embodiment of the present disclosure.
Fig. 4 is a third schematic flow chart illustrating a data reading method of an EEPROM chip according to an embodiment of the present application.
Fig. 5 is a fourth flowchart illustrating a data reading method of an EEPROM chip according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Generally, an outdoor unit control unit of an air conditioner generally adopts a mode of combining an IIC main device and an EEPROM chip, wherein a general control code is stored in the IIC main device, and differentiated control parameters are stored in the EEPROM chip, so as to realize compatibility of a main control logic to various system models. However, in the practical application process, the IIC bus has a long circuit in the circuit board layout, which may cause distortion of the transmitted waveform, such as long time of the front and rear edges, and cause errors in the read data, thereby causing data reading failure of the EEPROM chip and causing the air conditioner to fail to operate normally.
Based on this, an embodiment of the present application provides a data reading method for an EEPROM chip, as shown in fig. 1, and fig. 1 is a first flowchart of the data reading method for the EEPROM chip provided in the embodiment of the present application. The method comprises the following steps:
and 110, controlling the IIC bus to read the data of the EEPROM chip by adopting a first transmission rate to obtain first data.
The execution main body of the embodiment of the present application may be an IIC main device, the IIC main device is a Micro Control Unit (MCU) having an IIC communication function, and the IIC main device and the EEPROM chip may be connected by IIC bus communication. The IIC master device may have an IIC communication interface, such as shown in fig. 2, where fig. 2 is a data reading system of an EEPROM chip provided in this embodiment, and the data reading system 20 includes an IIC bus, an IIC master device, and an EEPROM chip. The IIC main device and the EEPROM chip are connected with each other through an IIC bus. For example, the IIC master device may include a first serial clock interface and a first serial data interface. The IIC bus may include a Serial Clock Line (SCL) and a serial data interface (SDA), one end of the serial Clock Line being connected to the first serial Clock interface, and one end of the serial data Line being connected to the first serial data interface. The EEPROM chip comprises a second serial clock interface and a second serial data interface, the second serial clock interface is connected with the other end of the serial clock line, and the second serial data interface is connected with the other end of the serial data line. The IIC master device may perform Data communication with the EEPROM chip through a Serial Data Address (SDA) of the IIC bus based on a clock signal generated by an SCL of the IIC bus.
The IIC master device can control the IIC bus to read data of the EEPROM chip by adopting the first transmission speed so as to obtain first data.
And 120, judging whether the first data is correct or not.
And after reading the first data from the EEPROM chip, the IIC main device judges the first data and judges whether the first data read by the IIC main device is correct or not. Wherein, the following method can be adopted for judgment:
processing the first data to obtain a first check code;
comparing the first check code with a target check code pre-stored in the EEPROM chip;
if the first check code is the same as the target check code, judging that the first data is correct;
and if the first check code is different from the target check code, judging that the first data is wrong.
The IIC master device may process the first data according to a preset rule to obtain the first check code, where the preset rule may be a preset rule, for example, add or multiply a parameter of the first data. The EEPROM chip can calculate the data stored in the EEPROM chip in advance according to preset rules to obtain a target check code, and the target check code can check the data read by the IIC host device. And after the IIC main equipment calculates the first check code, the first check code is compared with the target check code, whether the first check code is the same as the target check code or not is determined, if the first check code is the same as the target check code, the first data is judged to be correct, and if the first check code is different from the target check code, the first data is judged to be wrong.
And 130, if the data are wrong, controlling the IIC bus to read the data of the EEPROM chip by adopting a second transmission rate to obtain second data, wherein the transmission rate of the second transmission rate is greater than that of the first transmission rate.
When the first data is judged to be wrong, the IIC master device can control the IIC bus to switch the transmission mode, and the data of the EEPROM chip are read at a second transmission rate to obtain second data, wherein the second transmission rate is greater than the first transmission rate.
Illustratively, the first transmission rate may be 100Kbit/s, the second transmission rate may be 3.4Mbit/s, and the data of the EEPROM chip is read again to obtain the second data. If the read second data is normal, the air conditioner may be operated normally. The first transmission rate is not limited to 100Kbit/s, but may be other rates lower than 100 Kbit/s. The second transmission rate is not limited to 3.4Mbit/s but may be other rates higher than 3.4 Mbit/s.
It can be understood that, in the embodiment of the application, when the data reading of the EEPROM chip is abnormal, the data reading of the EEPROM chip is performed again by switching the transmission rate of the IIC bus, so that the accuracy of reading the data of the EEPROM chip is improved.
As shown in fig. 3, fig. 3 is a schematic flowchart of a data reading method of an EEPROM chip according to an embodiment of the present disclosure. When the IIC bus adopts the second transmission rate and still cannot correctly read the data of the EEPROM chip, the following steps can be executed:
and 140, judging whether the second data is correct.
In the embodiment of the present application, the second data is determined in the same manner as in the embodiment of the present application. For example, the IIC master device may process the second data according to a preset rule to obtain the second check code, where the preset rule may be a preset rule, such as performing an addition operation or a multiplication operation on a parameter of the second data. And after the IIC main equipment calculates the second check code, comparing the second check code with the target check code of the EEPROM chip to determine whether the second check code is the same as the target check code, if so, judging that the second data is correct, and if not, judging that the second data is wrong.
150, if the error occurs, the transmission rate of the IIC bus is set to be more than 100Kbit/s and less than or equal to 400Kbit/s, and the high-low level ratio of the serial clock line in the IIC bus is set to be Tlow/Thigh＝2，TlowIndicating the duration of the low level, ThighIndicating the duration of the high level.
When the second data error is judged, the IIC master device can change the transmission rate of the IIC bus and the ratio of the high level and the low level of the serial clock line in the IIC bus. For example, the transmission rate of the IIC bus may be set to be one of more than 100Kbit/s and less than or equal to 400Kbit/s, such as setting the transmission rate of the IIC bus to be 400Kbit/s, and setting the ratio of the high level to the low level of the serial clock line in the IIC bus to be Tlow/Thigh＝2，TlowIndicating the duration of the low level, ThighIndicating the duration of the high level. When the serial clock line is at a high level, the IIC master device performs data acquisition based on the serial data line, and when the serial clock line is at a low level, the serial data line prepares the next data to be acquired, and the IIC master device suspends data acquisition, so that the data acquisition interval of the IIC master device to the EEPROM chip can be modified by modifying the ratio of the high level to the low level of the serial clock line.
It can be understood that when the waveform transmitted by the IIC bus is distorted, if the data of the EEPROM chip is still read at the originally set transmission rate and the IIC communication interval, a data reading error may occur. According to the embodiment of the application, when correct data cannot be read after the data of the EEPROM chip is read by switching the second transmission rate, the data of the EEPROM chip is read again by changing the transmission rate and the high-low level ratio of the IIC bus.
And 160, reading the data of the EEPROM chip through the set IIC bus to obtain third data.
And after the IIC bus is set, the IIC master device establishes communication with the EEPROM chip through the set IIC bus and reads data of the EEPROM chip to obtain third data. The IIC main equipment and the EEPROM chip establish communication through a serial clock line of the IIC bus. The EEPROM chip stores the optimal operation parameters of the air conditioner, and the operation according to the optimal operation parameters can ensure that the air conditioning unit operates in the optimal state. When the data of the EEPROM chip is successfully read, the air conditioning unit is directly controlled to operate based on the read data, so that the IIC main equipment can finish reading the data of the EEPROM chip at the fastest speed in a normal state and can enter normal operation as soon as possible.
As shown in fig. 4, fig. 4 is a third flowchart illustrating a data reading method of an EEPROM chip according to an embodiment of the present application. Wherein, after "160, reading the data of the EEPROM chip through the set IIC bus to obtain third data", the method further includes:
and 170, judging whether the third data is correct.
In the embodiment of the present application, the third data is determined in the same manner as in the embodiment of the present application. For example, the IIC master may process the third data according to a preset rule to obtain the third check code, where the preset rule may be a preset rule, such as adding or multiplying a parameter of the third data. And after the IIC main equipment calculates the third check code, the third check code is compared with the target check code of the EEPROM chip, whether the third check code is the same as the target check code or not is determined, if the third check code is the same as the target check code, the third data is determined to be correct, and if the third check code is different from the target check code, the third data is determined to be wrong.
180, if the error occurs, the transmission rate of the IIC bus is set to be more than 100Kbit/s and less than or equal to 400Kbit/s, and the high-low level ratio of the serial clock line is set to be Tlow/Thigh＝16/9，TlowIndicating the duration of the low level, ThighIndicating the duration of the high level.
When the third data error is judged, the IIC master device can change the transmission rate of the IIC bus and the ratio of the high level to the low level of the serial clock line in the IIC bus. Illustratively, the transmission rate of the IIC bus may be set to be one of more than 100Kbit/s and less than or equal to 400Kbit/s, such as setting the transmission rate of the IIC bus to be 400Kbit/s, and setting the ratio of the high level to the low level of the serial clock line in the IIC bus to be Tlow/Thigh＝16/9，TlowIndicating the duration of the low level, ThighIndicating the duration of the high level. When the serial clock line of the IIC bus is at a high level, the IIC master device performs data acquisition based on the serial data lineIf the serial clock line is at a low level, the serial data line prepares the next data to be acquired, and the IIC master device suspends data acquisition, so that the data acquisition interval of the IIC master device to the EEPROM chip can be modified by modifying the ratio of the high level to the low level of the serial clock line.
It can be understood that when the waveform transmitted by the IIC bus is distorted, if the data of the EEPROM chip is still read at the originally set transmission rate and the IIC communication interval, a data reading error may occur. According to the embodiment of the application, when correct data cannot be read after the data of the EEPROM chip is read by modifying the transmission rate and the duty ratio of high and low levels, the data of the EEPROM chip is read again by changing the duty ratio of high and low levels.
And 190, reading the data of the EEPROM chip through the set IIC bus to obtain fourth data.
And after the IIC bus is set, the IIC master device establishes communication with the EEPROM chip through the set IIC bus and reads data of the EEPROM chip to obtain fourth data.
Wherein, after reading the data of the EEPROM chip through the set IIC bus to obtain the fourth data, "190 further includes:
judging whether the fourth data is correct or not;
and if the fourth data is wrong, determining the IIC bus communication fault.
In the embodiment of the present application, the fourth data is determined in the same manner as in the embodiment of the present application. For example, the IIC master may process the fourth data according to a preset rule to obtain the third check code, where the preset rule may be a preset rule, such as adding or multiplying a parameter of the fourth data. And after the IIC main equipment calculates the fourth check code, the fourth check code is compared with the target check code of the EEPROM chip, whether the fourth check code is the same as the target check code or not is determined, if the fourth check code is the same as the target check code, the fourth data is determined to be correct, and if the fourth check code is different from the target check code, the fourth data is determined to be wrong. If the result of the judgment is that the fourth data is correct, the communication of the IIC bus can be recovered to be normal by modifying the transmission parameter of the IIC bus, so that the data reading of the EEPROM chip is correct. If the fourth data is wrong, the transmission rate and the duty ratio of high and low levels of the IIC bus are modified, so that the IIC communication can not be recovered to be normal, and the IIC bus communication fault can be judged at the moment.
It can be understood that the reason for the IIC bus communication fault may be due to waveform transmission distortion, and if the waveform transmission can be made normal by modifying the transmission rate and the duty ratio of the high and low levels of the IIC bus, the problem of the IIC bus communication fault due to waveform transmission distortion can be solved.
It should be noted that, in the embodiment of the above application, the process of acquiring the third data and the process of acquiring the fourth data may be exchanged. Exemplarily, as shown in fig. 5, fig. 5 is a fourth flowchart illustrating a data reading method of an EEPROM chip according to an embodiment of the present invention. At "130, if there is an error, controlling the IIC bus to read the data of the EEPROM chip using a second transmission rate to obtain second data, where the transmission rate of the second transmission rate is greater than the transmission rate of the first transmission rate" may include:
240, judging whether the second data is correct or not;
250, if the error occurs, the transmission rate of the IIC bus is set to be more than 100Kbit/s and less than or equal to 400Kbit/s, and the high-low level ratio of the serial clock line is set to be Tlow/Thigh＝16/9，TlowIndicating the duration of the low level, ThighIndicates the duration of the high level;
260, reading the data of the EEPROM chip through the set IIC bus to obtain fourth data;
270, judging whether the fourth data is correct or not;
280, if the error occurs, the transmission rate of the IIC bus is set to be more than 100Kbit/s and less than or equal to 400Kbit/s, and the high-low level ratio of the serial clock line is set to be Tlow/Thigh＝2，TlowIndicating the duration of the low level, ThighIndicates the duration of the high level;
290, reading the data of the EEPROM chip through the set IIC bus to obtain third data.
For the detailed description of the above steps, reference may be made to the related description of the above application embodiments, which is not repeated herein.
It can be understood that, when the IIC master device reads data by using the parameters set by the IIC bus, it may switch to another parameter setting until the reading is successful, and record the data reading mode at this time as the default mode for reading data by the EEPROM chip next time.
With reference to fig. 2, the present embodiment provides a data reading system for an EEPROM chip, which includes an IIC bus, an IIC host device, and an EEPROM chip. The IIC bus comprises a serial clock line and a serial data line; the IIC master equipment comprises a first serial clock interface and a first serial data interface, wherein the first serial clock interface is connected with one end of the serial clock line, and the first serial data interface is connected with one end of the serial data line; the EEPROM chip comprises a second serial clock interface and a second serial data interface, the second serial clock interface is connected with the other end of the serial clock line, and the second serial data interface is connected with one end of the serial data line. And the IIC main equipment reads the data of the EEPROM chip according to any one of the data reading methods of the EEPROM chip. Such as: the IIC bus is controlled to read the data of the EEPROM chip by adopting a first transmission rate to obtain first data; judging whether the first data is correct or not; and if the data of the EEPROM chip is wrong, controlling the IIC bus to read the data of the EEPROM chip by adopting a second transmission rate to obtain second data, wherein the second transmission rate is greater than the first transmission rate.
The EEPROM chip can also comprise a resistor R, a power interface VCC, a write protection interface WP, a device address output interface A0, a device address output interface A1, a device address output interface A2 and a power ground interface GND. One end of the resistor R is connected with the power interface VCC, the other end of the resistor R is connected with the write protection interface WP, and one end of the resistor R, which is connected with the power interface VCC, is also connected with the power supply VCC. The device address output interface A0, the device address output interface A1, the device address output interface A2 and the power ground interface GND are connected with each other and then grounded.
The embodiment of the application also provides an air conditioner, which comprises the data reading system of the EEPROM chip. Such as: the system comprises an IIC bus, an IIC main device and an EEPROM chip. The IIC bus comprises a serial clock line and a serial data line; the IIC master equipment comprises a first serial clock interface and a first serial data interface, wherein the first serial clock interface is connected with one end of the serial clock line, and the first serial data interface is connected with one end of the serial data line; the EEPROM chip comprises a second serial clock interface and a second serial data interface, the second serial clock interface is connected with the other end of the serial clock line, and the second serial data interface is connected with one end of the serial data line; and the IIC main equipment reads the data of the EEPROM chip according to the data reading method of the EEPROM chip of any application embodiment. Such as: the IIC bus is controlled to read the data of the EEPROM chip by adopting a first transmission rate to obtain first data; judging whether the first data is correct or not; and if the data of the EEPROM chip is wrong, controlling the IIC bus to read the data of the EEPROM chip by adopting a second transmission rate to obtain second data, wherein the second transmission rate is greater than the first transmission rate.
The embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the computer program implements the data reading method of the EEPROM chip described above. Such as: the IIC bus is controlled to read data of the EEPROM chip at a first transmission rate to obtain first data; judging whether the first data is correct or not; and if the data of the EEPROM chip is wrong, controlling the IIC bus to read the data of the EEPROM chip by adopting a second transmission rate to obtain second data, wherein the second transmission rate is greater than the first transmission rate.
In the embodiment of the present application, the storage medium may be a magnetic disk, an optical disk, a Read Only Memory (ROM), a Random Access Memory (RAM), or the like.
The data reading method and system of the EEPROM chip, the air conditioner, and the storage medium provided in the embodiments of the present application are described in detail above. The principles and implementations of the present application are described herein using specific examples, which are presented only to aid in understanding the present application. Meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (11)
1. A data reading method of an EEPROM chip is characterized by comprising the following steps:
the IIC bus is controlled to read data of the EEPROM chip at a first transmission rate to obtain first data;
judging whether the first data is correct or not;
and if the data of the EEPROM chip is wrong, controlling the IIC bus to read the data of the EEPROM chip by adopting a second transmission rate to obtain second data, wherein the second transmission rate is greater than the first transmission rate.
2. The method for reading data from the EEPROM chip of claim 1, wherein the step of determining whether the first data is correct comprises:
processing the first data to obtain a first check code;
comparing the first check code with a target check code pre-stored in the EEPROM chip;
if the first check code is the same as the target check code, judging that the first data is correct;
and if the first check code is different from the target check code, judging that the first data is wrong.
3. The method as claimed in claim 1 or 2, wherein if there is an error, controlling the IIC bus to read the data of the EEPROM chip at a second transmission rate to obtain a second data, wherein the second transmission rate is greater than the first transmission rate, and then:
Judging whether the second data is correct or not;
if the voltage is wrong, the transmission speed of the IIC bus is set to be larger than 100Kbit/s and smaller than or equal to 400Kbit/s, and the high-low level ratio of the serial clock line in the IIC bus is set to be Tlow/Thigh＝2，TlowIndicating the duration of the low level, ThighIndicates the duration of the high level;
and reading the data of the EEPROM chip through the set IIC bus to obtain third data.
4. The method for reading the data of the EEPROM chip according to claim 3, wherein after reading the data of the EEPROM chip through the set IIC bus to obtain third data, the method further comprises:
judging whether the third data is correct or not;
if the error occurs, the transmission rate of the IIC bus is set to be more than 100Kbit/s and less than or equal to 400Kbit/s, and the high-low level ratio of the serial clock line is set to be Tlow/Thigh＝16/9，TlowIndicating the duration of the low level, ThighIndicates the duration of the high level;
and reading the data of the EEPROM chip through the set IIC bus to obtain fourth data.
5. The data reading method of the EEPROM chip as claimed in claim 4, wherein after reading the data of the EEPROM chip through the set IIC bus to obtain the fourth data, the method comprises:
Judging whether the fourth data is correct or not;
and if the fourth data is wrong, determining the IIC bus communication fault.
6. The method as claimed in claim 1 or 2, wherein if there is an error, reading the data of the EEPROM chip through the IIC bus at a second transmission rate to obtain a second data, the second transmission rate being greater than the first transmission rate, and then:
judging whether the second data is correct or not;
if the voltage is wrong, the transmission speed of the IIC bus is set to be larger than 100Kbit/s and smaller than or equal to 400Kbit/s, and the high-low level ratio of the serial clock line is set to be Tlow/Thigh＝2，TlowIndicating the duration of the low level, ThighIndicates the duration of the high level;
and reading the data of the EEPROM chip through the set IIC bus to obtain fourth data.
7. The method as claimed in claim 1 or 2, wherein if there is an error, controlling the IIC bus to read the data of the EEPROM chip at a second transmission rate to obtain a second data, wherein the second transmission rate is greater than the first transmission rate, and then:
Judging whether the second data is correct or not;
if the voltage is wrong, the transmission speed of the IIC bus is set to be larger than 100Kbit/s and smaller than or equal to 400Kbit/s, and the high-low level ratio of the serial clock line is set to be Tlow/Thigh＝16/9，TlowIndicating the duration of the low level, ThighIndicates the duration of the high level;
reading the data of the EEPROM chip through the set IIC bus to obtain fourth data;
judging whether the fourth data is correct or not;
if the error occurs, the transmission rate of the IIC bus is set to be more than 100Kbit/s and less than or equal to 400Kbit/s, and the high-low level ratio of the serial clock line is set to be Tlow/Thigh＝2，TlowIndicating the duration of the low level, ThighIndicates the duration of the high level;
and reading the data of the EEPROM chip through the set IIC bus to obtain third data.
8. The data reading method of the EEPROM chip of claim 1, wherein the transmission rate of the first transmission rate is equal to or less than 100Kbit/s, and the transmission rate of the second transmission rate is equal to or more than 3.4 Mbit/s.
9. A data reading system for an EEPROM chip, comprising:
the IIC bus comprises a serial clock line and a serial data line;
the IIC master equipment comprises a first serial clock interface and a first serial data interface, wherein the first serial clock interface is connected with one end of the serial clock line, and the first serial data interface is connected with one end of the serial data line;
The EEPROM chip comprises a second serial clock interface and a second serial data interface, the second serial clock interface is connected with the other end of the serial clock line, and the second serial data interface is connected with one end of the serial data line;
the IIC master reads data of the EEPROM chip according to the data reading method of the EEPROM chip of any one of claims 1 to 8.
10. An air conditioner characterized by comprising a data reading system of the EEPROM chip of claim 9.
11. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out a data reading method of an EEPROM chip as claimed in any one of claims 1 to 8.
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| CN202210238205.8ACN114756496B (en) | 2022-03-11 | 2022-03-11 | Data reading method and system of EEPROM chip, air conditioner and storage medium |
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| CN111578489A (en)* | 2020-05-12 | 2020-08-25 | 珠海拓芯科技有限公司 | EEPROM chip data reading method, control system, air conditioner and storage medium |
| CN113849355A (en)* | 2021-08-30 | 2021-12-28 | 苏州浪潮智能科技有限公司 | I2C rate adaptive adjustment method, system, terminal and storage medium |
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| US20020174311A1 (en)* | 2001-04-24 | 2002-11-21 | Ware Frederick A. | Method and apparatus for coordinating memory operations among diversely-located memory components |
| CN109358981A (en)* | 2018-09-25 | 2019-02-19 | 珠海市杰理科技股份有限公司 | Memory read error correction method, system, computer device and storage medium |
| CN111578489A (en)* | 2020-05-12 | 2020-08-25 | 珠海拓芯科技有限公司 | EEPROM chip data reading method, control system, air conditioner and storage medium |
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