CN114755908A - Time interval measuring system and method based on delay link - Google Patents
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Abstract
Translated fromChinese
Description
Translated fromChinese技术领域technical field
本发明涉及激光雷达测距技术领域，具体而言，涉及一种基于延时链路的时间间隔测量系统及方法。The present invention relates to the technical field of laser radar ranging, and in particular, to a time interval measurement system and method based on a delay link.
背景技术Background technique
激光雷达是以发射激光束探测目标的位置、速度等特征量的雷达系统，由激光发射机、光学接收机和信息处理系统等组成。其工作原理是向目标发射激光束，然后将接收到的从目标反射回来的信号与发射信号进行比较，作适当处理后，就可获得目标的有关信息，如目标距离、方位、高度、速度、姿态以及形状等参数。Lidar is a radar system that emits a laser beam to detect the position, speed and other characteristic quantities of a target, and consists of a laser transmitter, an optical receiver, and an information processing system. Its working principle is to emit a laser beam to the target, and then compare the received signal reflected from the target with the transmitted signal, and after proper processing, the relevant information of the target can be obtained, such as target distance, azimuth, altitude, speed, Pose and shape parameters.
而激光雷达测距精度要求为厘米级，转换为时间间隔为皮秒ps级，传统时钟计数的方法很难达到该精度。导致激光雷达出现微小时间间隔误差，影响测量的精度。The LiDAR ranging accuracy is required to be at the centimeter level, and the time interval is converted into a picosecond ps level. It is difficult for the traditional clock counting method to achieve this accuracy. This leads to a small time interval error in the lidar, which affects the accuracy of the measurement.
发明内容SUMMARY OF THE INVENTION
本发明的目的在于提供一种基于延时链路的时间间隔测量系统及方法，其能够测距工作时出现的微小时间间隔准确性的问题，提高测量的精度。The purpose of the present invention is to provide a time interval measurement system and method based on a time delay link, which can solve the problem of the accuracy of the small time interval that occurs during the ranging operation, and improve the measurement accuracy.
本发明的实施例通过以下技术方案实现：Embodiments of the present invention are realized through the following technical solutions:
一方面，提供一种基于延时链路的时间间隔测量系统，包括FPGA芯片以及时间数字转换器，所述FPGA芯片与所述时间数字转换器连接，所述时间数字转换器包括第一加法器、第二加法器、减法器以及多个第一时间间隔测量通道以及多个第二时间间隔测量通道，多个所述第一时间间隔测量通道的输出端分别与所述第一加法器的输入端连接，多个所述第二时间间隔测量通道的输出端分别与所述第二加法器的输入端连接，所述第一加法器与第二加法器的输出端连接所述减法器的输入端。In one aspect, a time interval measurement system based on a delay link is provided, comprising an FPGA chip and a time-to-digital converter, the FPGA chip is connected to the time-to-digital converter, and the time-to-digital converter includes a first adder , a second adder, a subtractor, a plurality of first time interval measurement channels and a plurality of second time interval measurement channels, the outputs of the plurality of first time interval measurement channels are respectively connected with the input of the first adder The output ends of the second time interval measurement channels are respectively connected to the input ends of the second adder, and the output ends of the first adder and the second adder are connected to the input end of the subtractor. end.
优选地，所述第一时间间隔测量通道与所述第二时间间隔测量通道结构相同，包括依次连接的进位链模块、延时链模块、编码器模块以及查找表模块；其中，Preferably, the first time interval measurement channel has the same structure as the second time interval measurement channel, including a carry chain module, a delay chain module, an encoder module and a lookup table module connected in sequence; wherein,
所述进位链模块用于将为输入的Hit信号分配数值，使得Hit信号输入所述延时链模块时具有两个跳变沿；The carry chain module is used for assigning a numerical value to the input Hit signal, so that the Hit signal has two transition edges when it is input to the delay chain module;
所述延时链模块用于测量时间间隔的细时间并向所述编码器模块输出细时间测量结果；The delay chain module is used to measure the fine time of the time interval and output the fine time measurement result to the encoder module;
所述编码器模块用于对细时间测量结果进行编码，得到细时间编码结果；The encoder module is used for encoding the fine-time measurement result to obtain the fine-time encoding result;
所述查找表模块用于对细时间编码结果进行校正，得到校正细时间结果。The look-up table module is used for correcting the fine time coding result to obtain the corrected fine time result.
优选地，所述延时链模块由127位加法器构成。Preferably, the delay chain module consists of a 127-bit adder.
优选地，所述查找表模块包括两个RAM存储器。Preferably, the look-up table module includes two RAM memories.
第二方面，提供一种基于延时链路的时间间隔测量方法，包括如下步骤：In a second aspect, a time interval measurement method based on a delay link is provided, including the following steps:
S1.获取输入的Hit信号，其中Hit信号包括start信号以及stop信号；S1. Obtain the input Hit signal, wherein the Hit signal includes a start signal and a stop signal;
S2.将start信号分别输入多个第一时间间隔测量通道中，获取多个第一通道时间测量结果；将stop信号分别输入多个第二时间间隔测量通道中，获取多个第二通道时间测量结果；S2. Input the start signal into multiple first time interval measurement channels respectively to obtain multiple first channel time measurement results; respectively input the stop signal into multiple second time interval measurement channels to obtain multiple second channel time measurements result;
S3.将多个第一通道时间测量结果输入第一加法器中进行累加得到第一累加结果，并对第一累加结果进行移位；将多个第二通道时间测量结果输入第二加法器中进行累加得到第二累加结果，并对第二累加结果进行移位；S3. Input multiple first channel time measurement results into the first adder for accumulation to obtain the first accumulated result, and shift the first accumulated result; input multiple second channel time measurement results into the second adder Accumulate to obtain the second accumulation result, and shift the second accumulation result;
S4.将移位处理后的第一累加结果以及第二累加结果输入减法器中相减，得到时间间隔测量结果。S4. Input the shifted first accumulation result and the second accumulation result into a subtractor for subtraction to obtain a time interval measurement result.
优选地，所述获取第一通道时间测量结果的方法与获取第二通道时间测量结果的方法相同，具体包括如下步骤：Preferably, the method for obtaining the time measurement result of the first channel is the same as the method for obtaining the time measurement result of the second channel, and specifically includes the following steps:
A.Hit信号输入进位链模块，进位链模块为Hit信号分配数值，使得Hit信号输入延时链模块时具有两个跳变沿；A. The Hit signal is input to the carry chain module, and the carry chain module assigns a value to the Hit signal, so that the Hit signal has two transition edges when it is input to the delay chain module;
B.Hit信号输入延时链模块，并在延时链模块上进行传播，延时链模块计算传播过程中的细时间测量结果，细时间测量结果分为两路输出，一路被粗时钟寄存器采样寄存，另一路进入编码器模块进行编码；B. The Hit signal is input to the delay chain module and propagated on the delay chain module. The delay chain module calculates the fine time measurement results during the propagation process. The fine time measurement results are divided into two outputs, and one is sampled by the coarse clock register Register, and the other way enters the encoder module for encoding;
C.编码器对细时间测量结果编码，编码获得细时间编码结果；C. The encoder encodes the fine-time measurement result, and the encoding obtains the fine-time encoding result;
D.细时间编码结果进入查找表模块进行校正，校正获得校正细时间结果；D. The fine time coding result enters the lookup table module for correction, and the correction obtains the correction fine time result;
E.将校正细时间结果与粗时间相加得到第一通道时间测量结果或第二通道时间测量结果。E. Add the corrected fine time result and the coarse time to obtain the first channel time measurement result or the second channel time measurement result.
优选地，所述查找表模块的校正过程为：Preferably, the correction process of the look-up table module is:
A.建立编码细时间结果与测试次数的频次表；A. Establish a frequency table of coding fine time results and test times;
B.判断测试次数是否到达预设值；若到达，则将频次表的各项数据依次累加求和，获取编码细时间结果的积分表；B. Determine whether the number of tests has reached the preset value; if it does, the data of the frequency table will be accumulated and summed in turn to obtain the integral table of the encoded fine-time results;
C.查询积分表，得到校正细时间结果。C. Query the integral table to get the correction time result.
本发明实施例的技术方案至少具有如下优点和有益效果：The technical solutions of the embodiments of the present invention have at least the following advantages and beneficial effects:
本申请基于FPGA的延时链路来获得时间间隔的细时间值，解决测距工作时出现的微小时间间隔准确性的问题，提高测量的精度；The application obtains the fine time value of the time interval based on the delay link of the FPGA, solves the problem of the accuracy of the small time interval in the ranging work, and improves the measurement accuracy;
本发明设计合理、结构简单，实用性强。The invention has reasonable design, simple structure and strong practicability.
附图说明Description of drawings
图1为本发明实施例1提供的基于延时链路的时间间隔测量方法的流程示意图；1 is a schematic flowchart of a method for measuring a time interval based on a delay link according to Embodiment 1 of the present invention;
图2为本发明实施例1提供的时间数字转换器的结构示意图；2 is a schematic structural diagram of a time-to-digital converter provided in Embodiment 1 of the present invention;
图3为本发明实施例1提供的第一时间间隔测量通道的结构示意图。FIG. 3 is a schematic structural diagram of a first time interval measurement channel provided in Embodiment 1 of the present invention.
具体实施方式Detailed ways
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。通常在此处附图中描述和示出的本发明实施例的组件可以以各种不同的配置来布置和设计。In order to make the purposes, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments These are some embodiments of the present invention, but not all embodiments. The components of the embodiments of the invention generally described and illustrated in the drawings herein may be arranged and designed in a variety of different configurations.
实施例1Example 1
在距离测量领域，从原理上讲激光雷达是通过发射激光信号，然后接收从目标反射回来的回波信号，与发射信号进行比较，以获得目标的距离信息。即测量发射的激光脉冲到目标和返回到接收器的传播时间t。由于激光是以光速c传播的，光速是已知的并且受环境影响小，所以与目标的距离可以从时间间隔计算出来。In the field of distance measurement, in principle, lidar transmits a laser signal, then receives the echo signal reflected from the target, and compares it with the transmitted signal to obtain the distance information of the target. That is, the propagation time t of the emitted laser pulse to the target and back to the receiver is measured. Since the laser travels at the speed of light c, the speed of light is known and is less affected by the environment, so the distance to the target can be calculated from the time interval.
激光雷达设备测距精度要求为厘米级，转换为时间间隔为ps级，传统时钟计数的方法很难达到该精度。于是，本申请提出采用基于可编程逻辑器(FPGA)的时间间隔测量的方法，利用芯片内部延迟链来获得时间间隔的细时间值。时间间隔测量值的计算方法为粗时间值加上细时间值。The ranging accuracy of lidar equipment is required to be centimeter-level, and the time interval is converted to ps-level, which is difficult to achieve by traditional clock counting methods. Therefore, the present application proposes to use a programmable logic device (FPGA)-based time interval measurement method to obtain the fine time value of the time interval by using the delay chain inside the chip. The time interval measurement is calculated as the coarse time value plus the fine time value.
激光器发射脉冲激光到目标，同时产生一个发送事件的启动信号(start信号)到时间数字转换器，代表激光脉冲飞行的起始时间。发射的激光脉冲遇到目标会产生回波，从目标反射回来的激光脉冲经接收器接收，由光电探测器转换为电信号。该信号经放大，并转换为逻辑电平信号，即停止(stop)信号。需要测量启动和停止信号之间的时间间隔并将其转换为距离结果。The laser emits pulsed laser light to the target, and at the same time generates a start signal (start signal) that sends an event to the time-to-digital converter, representing the start time of the laser pulse flight. The emitted laser pulse will generate an echo when it encounters the target. The laser pulse reflected from the target is received by the receiver and converted into an electrical signal by the photodetector. This signal is amplified and converted to a logic level signal, a stop signal. The time interval between start and stop signals needs to be measured and converted into a distance result.
所以，本申请提供一种基于延时链路的时间间隔测量系统，以此来解决上述问题，如图2所示，一种基于延时链路的时间间隔测量系统包括FPGA芯片以及时间数字转换器，所述FPGA芯片与所述时间数字转换器连接，所述时间数字转换器包括第一加法器、第二加法器、减法器以及多个第一时间间隔测量通道以及多个第二时间间隔测量通道，多个所述第一时间间隔测量通道的输出端分别与所述第一加法器的输入端连接，多个所述第二时间间隔测量通道的输出端分别与所述第二加法器的输入端连接，所述第一加法器与第二加法器的输出端连接所述减法器的输入端。在本实施例中，第一时间间隔测量通道为4个，第二时间间隔测量通道为4个。Therefore, the present application provides a time interval measurement system based on a delay link to solve the above problems. As shown in FIG. 2 , a time interval measurement system based on a delay link includes an FPGA chip and a time-to-digital converter. The FPGA chip is connected to the time-to-digital converter, and the time-to-digital converter includes a first adder, a second adder, a subtractor, a plurality of first time interval measurement channels and a plurality of second time intervals measurement channels, the output ends of the plurality of first time interval measurement channels are respectively connected with the input ends of the first adder, and the output ends of the plurality of second time interval measurement channels are respectively connected with the second adder The input end of the first adder and the output end of the second adder are connected to the input end of the subtractor. In this embodiment, there are four first time interval measurement channels, and four second time interval measurement channels.
所述第一时间间隔测量通道用于测量start信号，所述第二时间间隔测量通道用于测量stop信号。本申请设计多个第一时间间隔测量通道以及多个第二时间间隔测量通道，进行多次测量start信号以及stop信号，其目的在于求取多个通道的平均测量结果，从而提高测量结果的精度。The first time interval measurement channel is used to measure the start signal, and the second time interval measurement channel is used to measure the stop signal. The present application designs a plurality of first time interval measurement channels and a plurality of second time interval measurement channels to measure the start signal and the stop signal multiple times, the purpose of which is to obtain the average measurement result of the plurality of channels, thereby improving the accuracy of the measurement result .
所述第一时间间隔测量通道与所述第二时间间隔测量通道结构相同，如图3所示，包括依次连接的进位链模块、延时链模块、编码器模块以及查找表模块；其中，The first time interval measurement channel has the same structure as the second time interval measurement channel, as shown in FIG. 3 , including a carry chain module, a delay chain module, an encoder module and a look-up table module connected in sequence; wherein,
所述进位链模块用于将为输入的Hit信号分配数值，使得Hit信号输入所述延时链模块时具有两个跳变沿；在本申请中，Hit信号为start信号或stop信号。The carry chain module is configured to assign a numerical value to the input Hit signal, so that the Hit signal has two transition edges when input to the delay chain module; in this application, the Hit signal is a start signal or a stop signal.
在FPGA芯片的延时链路中，会出现突发的大延时单元，对测量精度造成较大的影响，所述本申请设计了进位链模块，进位链模块将输入的Hit信号设置固定数值，使Hit信号具有两个固定距离的跳变沿，且使得两个跳变沿不会同时处于一个大的延时单元中，降低大延时单元对测量精度的影响。In the delay link of the FPGA chip, a sudden large delay unit will appear, which has a great impact on the measurement accuracy. The present application designs a carry chain module, and the carry chain module sets the input Hit signal to a fixed value , so that the Hit signal has two transition edges with a fixed distance, and the two transition edges will not be in a large delay unit at the same time, thereby reducing the influence of the large delay unit on the measurement accuracy.
所述延时链模块用于测量时间间隔的细时间并向所述编码器模块输出细时间测量结果。The delay chain module is used to measure the fine time of the time interval and output the fine time measurement result to the encoder module.
在本实施例中，延时链模块由127位加法器构成，随着Hit波形在延时链上传播以及时间的推移，加法器输出波形，并持续向左移动，由粗时钟寄存器采样寄存，并得到细时间测量结果，细时间测量结果128位数，例如“......000111000111000......”。In this embodiment, the delay chain module is composed of a 127-bit adder. With the propagation of the Hit waveform on the delay chain and the passage of time, the adder outputs the waveform and continues to move to the left, which is sampled and registered by the coarse clock register. And get the fine time measurement result, the fine time measurement result has 128 digits, such as "...000111000111000...".
所述编码器模块用于对细时间测量结果进行编码，得到细时间编码结果。因为细时间测量结果为128位数，处理起来不方便，所以需要对细时间测量结果进行编码，编码为能够反映127级延时大小的8位数据。得到细时间编码结果。The encoder module is used for encoding the fine-time measurement result to obtain the fine-time encoding result. Because the fine time measurement result is 128 digits, it is inconvenient to process, so the fine time measurement result needs to be encoded into 8-bit data that can reflect the size of the 127-level delay. Get the fine time coding result.
所述查找表模块用于对细时间编码结果进行校正，得到校正细时间结果。因为延时链的延时单元值不均匀以及温度对延时值的影响，使得得到的细时间编码结果不够精准，需要通过查找表模块对细时间编码结果进行校正。其校正方法为：建立细时间编码结果与测试次数的频次表。当测试次数达到指定值时，将频次表各项数据依次累加求和，得到细时间编码结果的积分表。通过查询积分表，可以直接得到校正细时间结果。The look-up table module is used for correcting the fine time coding result to obtain the corrected fine time result. Due to the uneven value of the delay unit of the delay chain and the influence of temperature on the delay value, the obtained fine time coding result is not accurate enough, and the fine time coding result needs to be corrected by the lookup table module. The correction method is as follows: establishing a frequency table of fine time coding results and testing times. When the number of tests reaches the specified value, the data of the frequency table are accumulated and summed in turn to obtain the integral table of the fine time coding results. By querying the integral table, the calibration fine time result can be obtained directly.
且为了实现线性操作，在本实施例中，所述查找表模块包括两个RAM存储器。建表与查表的过程分别在2个RAM存储器内存中同时进行。当第1个RAM存储器正在进行建表时，第2个RAM存储器已经建好的表进行查询。当第1个RAM存储器建表完成时，进行切换，第1个RAM存储器进行查询，第2个RAM存储器内存进行建表，如此循环。And in order to realize linear operation, in this embodiment, the look-up table module includes two RAM memories. The process of table building and table lookup is carried out simultaneously in two RAM memory memories. When the first RAM memory is building a table, the second RAM memory has already built a table for query. When the first RAM memory table building is completed, the switch is performed, the first RAM memory memory is queried, and the second RAM memory memory is used for table building, and so on.
如图1所示，第二方面，提供一种基于延时链路的时间间隔测量方法，包括如下步骤：As shown in FIG. 1 , in a second aspect, a time interval measurement method based on a delay link is provided, including the following steps:
S1.获取输入的Hit信号，其中Hit信号包括start信号以及stop信号。S1. Obtain the input Hit signal, wherein the Hit signal includes a start signal and a stop signal.
S2.将start信号分别输入多个第一时间间隔测量通道中，获取多个第一通道时间测量结果；将stop信号分别输入多个第二时间间隔测量通道中，获取多个第二通道时间测量结果。S2. Input the start signal into multiple first time interval measurement channels respectively to obtain multiple first channel time measurement results; respectively input the stop signal into multiple second time interval measurement channels to obtain multiple second channel time measurements result.
所述获取第一通道时间测量结果的方法与获取第二通道时间测量结果的方法相同，具体包括如下步骤：The method for obtaining the time measurement result of the first channel is the same as the method for obtaining the time measurement result of the second channel, and specifically includes the following steps:
A.Hit信号输入进位链模块，进位链模块为Hit信号分配数值，使得Hit信号输入延时链模块时具有两个跳变沿。A. The Hit signal is input to the carry chain module, and the carry chain module assigns a numerical value to the Hit signal, so that the Hit signal has two transition edges when it is input to the delay chain module.
B.Hit信号输入延时链模块，并在延时链模块上进行传播，延时链模块计算传播过程中的细时间测量结果，细时间测量结果分为两路输出，一路被粗时钟寄存器采样寄存，另一路进入编码器模块进行编码。B. The Hit signal is input to the delay chain module and propagated on the delay chain module. The delay chain module calculates the fine time measurement results during the propagation process. The fine time measurement results are divided into two outputs, and one is sampled by the coarse clock register Register, and the other way enters the encoder module for encoding.
C.编码器对细时间测量结果编码，编码获得细时间编码结果；C. The encoder encodes the fine-time measurement result, and the encoding obtains the fine-time encoding result;
因为输入的细时间测量结果是128位，太宽，不方便处理，需要进行编码到8位的细时间编码结果，具体编码方法如下：Because the input fine time measurement result is 128 bits, which is too wide and inconvenient to handle, it is necessary to encode the fine time encoding result of 8 bits. The specific encoding method is as follows:
输入细时间测量结果分3路，第1路不作处理，第2路左移1位，按位取反，第3路左移2位，按位取反。然后这三路按位与得到一个新的128位数据。这样做的效果是，例如原数据是这样的“......000111000111000......”，经处理后，得到这样的“......000001000001000......”。1的位置就反映了细时间的信息。The input fine time measurement result is divided into 3 channels, the first channel is not processed, the second channel is shifted to the left by 1 bit, and the bit is inverted. The third channel is shifted to the left by 2 bits, and the bit is inverted. Then the three-way bitwise AND gets a new 128-bit data. The effect of this is that, for example, the original data is like this "...000111000111000...", after processing, we get this "... . The position of 1 reflects the information of the fine time.
得到新128位数据后，分为16组，每组8位，分别进入8-4编码器进行编码。得到细时间编码结果。编码器输出信号Tn表示输入数据中1的存在的位置，输出信号Detectn表示输入数据是否有1存在。其8-4编码器的的映射关系如表1所示：After getting the new 128-bit data, it is divided into 16 groups, each group of 8 bits, respectively enters the 8-4 encoder for encoding. Get the fine time coding result. The encoder output signal Tn indicates the position where 1 exists in the input data, and the output signal Detectn indicates whether there is a 1 in the input data. The mapping relationship of its 8-4 encoder is shown in Table 1:
表1：8-4编码器输入输出关系Table 1: 8-4 encoder input and output relationship
D.细时间编码结果进入查找表模块进行校正，校正获得校正细时间结果；D. The fine time coding result enters the lookup table module for correction, and the correction obtains the correction fine time result;
所述查找表模块的校正流程具体为：从某一个时刻开始，RAM1刚好开始建表，RAM2开始进行查询。The specific correction flow of the lookup table module is as follows: starting from a certain moment, RAM1 just starts to build a table, and RAM2 starts to query.
RAM2进行查询时，RAM2的建表已经完成，只要delaychain bin作为RAM2的地址信号给出，即输出校正细时间结果。When RAM2 is inquiring, the table building of RAM2 has been completed. As long as the delaychain bin is given as the address signal of RAM2, the result of correcting the fine time is output.
当RAM2开始查询时，与之同时，RAM1开始进行建表。首先，RAM1进行初始化，把之前的表内容全部清0。然后，当delachain bin到来时，作为RAM1的地址信号，进行地址次数统计。当delachain bin到来32768次后，频次表建立完成，接下来建立积分表。积分表建立过程是：把频次表内容按地址依次读出累加，再把每一次的累加结果按地址写入表中。例如，I0＝N0，I1＝N0+N1，I2＝N0+N1+N2，......When RAM2 starts to query, at the same time, RAM1 starts to build the table. First, RAM1 is initialized, and all the previous table contents are cleared to 0. Then, when the delachain bin arrives, it is used as the address signal of RAM1 to count the number of addresses. When the delachain bin arrives 32768 times, the frequency table is established, and then the score table is established. The establishment process of the integral table is: read and accumulate the contents of the frequency table according to the address in turn, and then write the accumulated result of each time into the table according to the address. For example, I0=N0, I1=N0+N1, I2=N0+N1+N2, …
查表得到的测量结果是经过转处理后的结果。首先，1个Hit信号经过进位链模块变成2个跳变沿，所以delachain bin应除以2。其次，经过32768次的Hit信号，建立频次表，然后得到积分表，每个地址的积分结果应除以128才是校正细时间结果。The measurement result obtained by looking up the table is the result after conversion. First, 1 Hit signal becomes 2 transition edges through the carry chain module, so the delachain bin should be divided by 2. Secondly, after 32768 Hit signals, the frequency table is established, and then the integration table is obtained. The integration result of each address should be divided by 128 to be the result of correcting the fine time.
E.将校正细时间结果与粗时间相加得到第一通道时间测量结果或第二通道时间测量结果。粗时间为现有技术，在本申请中不作详细描述。E. Add the corrected fine time result and the coarse time to obtain the first channel time measurement result or the second channel time measurement result. Coarse time is in the prior art and will not be described in detail in this application.
S3.将多个第一通道时间测量结果输入第一加法器中进行累加得到第一累加结果，并对第一累加结果进行移位；将多个第二通道时间测量结果输入第二加法器中进行累加得到第二累加结果，并对第二累加结果进行移位；根据第一时间间隔测量通道的个数对第一累加结果进行移位，根据第二时间间隔测量通道的个数对第二累加结果进行移位。则，在本实施例中，需要将第一累加结果以及第二累加结果分别右移两位，相当于除以4。S3. Input multiple first channel time measurement results into the first adder for accumulation to obtain the first accumulated result, and shift the first accumulated result; input multiple second channel time measurement results into the second adder Perform accumulation to obtain the second accumulation result, and shift the second accumulation result; shift the first accumulation result according to the number of measurement channels in the first time interval, and shift the second accumulation result according to the number of measurement channels in the second time interval. The accumulated result is shifted. Then, in this embodiment, the first accumulation result and the second accumulation result need to be shifted to the right by two bits respectively, which is equivalent to dividing by 4.
S4.将移位处理后的第一累加结果以及第二累加结果输入减法器中相减，得到时间间隔测量结果，相减则表明为计算的是start信号与stop信号之间的时间间隔。S4. Input the shifted first accumulation result and the second accumulation result into the subtractor for subtraction to obtain a time interval measurement result, and the subtraction indicates that the time interval between the start signal and the stop signal is calculated.
以上仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。The above are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.
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| CN109407500A (en)* | 2018-11-22 | 2019-03-01 | 深圳天眼激光科技有限公司 | Time interval measuring method based on FPGA |
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