Disclosure of Invention
The invention aims at providing a fan-out type double-sided packaging structure, a preparation method and a preparation method of the fan-out type double-sided packaging structure, which can alleviate the problem of plastic package warpage and layering, and can greatly improve wiring density, chip wiring integration and further improve the number of stacked chips.
Embodiments of the invention may be implemented as follows:
in a first aspect, the present invention provides a fan-out type double-sided package structure, including:
A first carrier plate;
The first chip is attached to one side surface of the first carrier plate;
The first plastic package body is arranged on the first carrier plate and coated outside the first chip;
the second carrier plate is attached to the surface of the other side of the first carrier plate;
the second chip is attached to one side surface of the second carrier plate;
The second plastic package body is arranged on the second carrier plate and is coated outside the second chip;
the wiring combination layer is arranged on one side of the second plastic package body, which is far away from the second carrier plate;
and a packaging device attached to the other side surface of the second carrier plate;
The first carrier plate is provided with a yielding groove which penetrates through the second carrier plate, the third chip is arranged in the yielding groove, the first carrier plate is internally provided with a first wiring layer, the second carrier plate is internally provided with a second wiring layer, the first wiring layer is electrically connected with the second wiring layer, the first chip is electrically connected with the first wiring layer, the second chip is electrically connected with the second wiring layer, and the wiring combination layer is electrically connected with the second wiring layer.
In an alternative embodiment, the packaging device includes a third chip, the third chip is attached to a surface of the second carrier plate, which is far away from the second chip, and the third chip is electrically connected with the second wiring layer.
In an optional embodiment, the fan-out type double-sided package structure further includes a third plastic package body, the third plastic package body is disposed on a side surface of the second carrier plate away from the wiring combination layer, and is located in the abdication groove, and the third plastic package body is wrapped outside the third chip.
In an optional embodiment, a conductive post is further disposed in the second plastic package, one end of the conductive post extends to the second carrier plate and is electrically connected to the second wiring layer, and the other end of the conductive post extends to the wiring combination layer and is electrically connected to the wiring combination layer.
In an alternative embodiment, the first chip is flip-chip mounted on the first carrier, a first conductive bump is disposed on the first chip, a first bonding pad is disposed on a surface of a side, away from the second carrier, of the first carrier, the first bonding pad is electrically connected with the first wiring layer, and the first conductive bump is bonded on the first bonding pad.
In an alternative embodiment, the second chip is flip-chip mounted on the second carrier, a second conductive bump is disposed on the second chip, a second bonding pad is disposed on a surface of a side, away from the first carrier, of the second carrier, the second bonding pad is electrically connected to the second wiring layer, and the second conductive bump is bonded on the second bonding pad.
In an optional embodiment, the third chip is flip-chip mounted on the second carrier, a third conductive bump is disposed on the third chip, a third bonding pad is disposed on a surface of a side, away from the second plastic package, of the second carrier, the third bonding pad is electrically connected with the second wiring layer, and the third conductive bump is bonded on the third bonding pad.
In an alternative embodiment, the wiring combination layer includes a first dielectric layer, a first metal layer, a second dielectric layer, a second metal layer and a first solder ball, where the first dielectric layer covers the surface of the second plastic package body, the first metal layer is disposed in the first dielectric layer and electrically connected with the conductive post, the second dielectric layer covers the surface of the first dielectric layer, the second metal layer is disposed in the second dielectric layer and electrically connected with the first metal layer, and the first solder ball is disposed on a side, away from the second plastic package body, of the second dielectric layer and electrically connected with the second metal layer.
In an alternative embodiment, the second chips are multiple, each second chip is provided with a second conductive bump, at least one second chip is being mounted on the second carrier board, so that the corresponding second conductive bump is bonded on the first dielectric layer, a third wiring layer is further arranged in the first dielectric layer, a conductive layer is further arranged in the second dielectric layer, a second solder ball is further arranged on the second dielectric layer, the third wiring layer is electrically connected with the second conductive bump bonded on the first dielectric layer, the conductive layer is electrically connected with the third wiring layer, the second solder ball is electrically connected with the conductive layer, and the third wiring layer is electrically isolated from the first metal layer, so that the third wiring layer is independently wired in the first dielectric layer.
In an optional embodiment, the packaging device includes a first heat dissipating block, the first heat dissipating block is attached to the second carrier, the first plastic package body is wrapped around the first heat dissipating block, and a side, away from the second carrier, of the first heat dissipating block is exposed to the first plastic package body.
In an optional embodiment, a second heat dissipation block is further arranged on the second carrier plate, the second heat dissipation block is attached to a side surface of the second carrier plate away from the first carrier plate, the second plastic package body is coated outside the second heat dissipation block, and the second heat dissipation block and the packaging device are correspondingly arranged on two side surfaces of the second carrier plate.
In a second aspect, the present invention provides a method for preparing a fan-out type double-sided package structure, which is used for preparing the fan-out type double-sided package structure according to any one of the foregoing embodiments, where the preparation method includes:
a first chip is attached to one side surface of a first carrier plate;
forming a first plastic package body coated outside the first chip on the first carrier plate;
attaching a second carrier plate to the other side surface of the first carrier plate;
slotting on the first plastic package body and the first carrier plate to form a yielding slot and exposing the second carrier plate;
Mounting and packaging devices in the abdication grooves;
Forming a third plastic package body which covers the packaging device in the abdication groove;
Attaching a second chip on the second carrier plate;
forming a second plastic package body coated outside the second chip on the second carrier plate;
forming a wiring combination layer on the second plastic package body;
The first carrier plate is internally provided with a first wiring layer, the second carrier plate is internally provided with a second wiring layer, the first wiring layer is electrically connected with the second wiring layer, the first chip is electrically connected with the first wiring layer, the second chip is electrically connected with the second wiring layer, and the wiring combination layer is electrically connected with the second wiring layer.
In a third aspect, the present invention provides a method for preparing a fan-out type double-sided package structure, which is used for preparing the fan-out type double-sided package structure according to any one of the foregoing embodiments, the method comprising:
attaching a second carrier plate to one side surface of the first carrier plate;
Slotting on the first carrier plate to form a yielding slot and exposing the second carrier plate;
attaching a first chip on the first carrier plate;
Mounting packaging devices on the second carrier plate in the abdication groove;
forming a first plastic package body which is coated outside the first chip and the packaging device simultaneously in the first carrier plate and the abdication groove;
A second chip is attached to one side, far away from the first chip, of the second carrier plate;
forming a second plastic package body coated outside the second chip on the second carrier plate;
forming a wiring combination layer on one side of the second plastic package body away from the second carrier plate;
the first carrier plate is internally provided with a first wiring layer, the second carrier plate is internally provided with a second wiring layer, the first wiring layer is electrically connected with the second wiring layer, the first chip is electrically connected with the first wiring layer, the second chip is electrically connected with the second wiring layer, and the wiring combination layer is electrically connected with the second wiring layer.
The beneficial effects of the embodiment of the invention include, for example:
The embodiment of the invention provides a fan-out type double-sided packaging structure, which is characterized in that a first carrier plate and a second carrier plate are mutually attached, a first chip is attached to the first carrier plate, a second chip and packaging devices are attached to the second carrier plate, so that the double-sided fan-out type packaging structure is realized, meanwhile, a first wiring layer is arranged in the first carrier plate, a second wiring layer is arranged in the second carrier plate, and double-sided packaging is realized through the two carrier plates, so that the wiring density is greatly improved, the wiring requirement of higher density is realized, and the number of stacked chips is promoted. Meanwhile, plastic package is respectively realized through the two carrier plates, so that a better supporting effect can be achieved, and the problem of plastic package warping can be relieved, so that the layering problem is relieved. Compared with the prior art, the method can alleviate the problem of plastic package warpage and layering, can greatly improve wiring density, improves chip wiring integration level, and further improves the number of stacked chips.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that like reference numerals and letters refer to like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
In the description of the present invention, it should be noted that, if the terms "upper", "lower", "inner", "outer", and the like indicate an azimuth or a positional relationship based on the azimuth or the positional relationship shown in the drawings, or the azimuth or the positional relationship in which the inventive product is conventionally put in use, it is merely for convenience of describing the present invention and simplifying the description, and it is not indicated or implied that the apparatus or element referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus it should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, if any, are used merely for distinguishing between descriptions and not for indicating or implying a relative importance.
As disclosed in the background art, the existing double-sided packaging structure generally adopts the same substrate to perform double-sided packaging, but the wiring density of a single substrate is limited, so that the wiring requirement of higher concentration cannot be realized. Meanwhile, the single substrate is weaker in support, and for the case of double-sided plastic packaging, the problem of warpage easily occurs due to different materials of different packaging bodies, so that the problem of delamination between the plastic packaging body and the surface of a chip and the problem of delamination between the plastic packaging body and the substrate are easily caused, and the quality of a device is affected. In addition, the existing double-sided packaging structure cannot realize reverse placement of chips on the same side, so that the mounting mode of the chips and the wiring mode of a circuit layer are greatly limited, and the wiring flexibility is low.
In order to solve the above-mentioned problems, the present invention provides a novel fan-out type double-sided package structure and a method for manufacturing the same, and it should be noted that the features in the embodiments of the present invention may be combined with each other without collision.
First embodiment
Referring to fig. 1, the present embodiment provides a fan-out type dual-sided package structure 100, which can alleviate the warpage problem and delamination problem of plastic package, and can greatly improve the wiring density, so as to improve the chip wiring integration level and further improve the stacking number of chips.
The fan-out type double-sided package structure 100 provided in this embodiment includes a first carrier 110, a first chip 120, a first plastic package 121, a second carrier 130, a second chip 140, a second plastic package 141, a wiring combination layer 150 and a package device, wherein the first chip 120 is mounted on one side surface of the first carrier 110, the first plastic package 121 is disposed on the first carrier 110 and is covered outside the first chip 120, the second carrier 130 is bonded on the other side surface of the first carrier 110, the second chip 140 is bonded on one side surface of the second carrier 130 away from the first carrier 110, the package device is bonded on the other side surface of the second carrier 130, the second plastic package 141 is covered outside the second chip 140 and the package device, a yield groove 113 penetrating through the second carrier 130 is disposed on the first carrier 110, the package device is disposed in the yield groove 113, a first layer 111 is disposed in the first carrier 110, a second wiring layer 131 and a second wiring layer 131 are disposed in the second carrier 130, the first wiring layer 131 and the second wiring layer 131 are electrically connected to the first wiring layer 131, and the second wiring layer 131 are electrically connected to the second wiring layer 131.
In this embodiment, the relief groove 113 extends to the edge of the device, so that the width of the first carrier plate 110 is smaller than the width of the second carrier plate 130, preferably, the width of the first carrier plate 110 is half of the width of the second carrier plate 130, so that the mounting space of the packaged device is the same as the mounting space of the first chip 120, which is beneficial to realizing uniform mounting.
In this embodiment, the package device includes a third chip 160, where the third chip 160 is attached to a surface of the second carrier 130 away from the second chip 140, and the third chip 160 is electrically connected to the second wiring layer 131. Specifically, the third chip 160 is disposed at an interval from the first chip 120, and the third chip 160 is mounted on the second carrier 130 in the yielding slot 113, the first chip 120 is mounted on the first carrier 110, and the first carrier 110 and the second carrier 130 are electrically connected through an internal circuit.
In this embodiment, two second chips 140 are disposed on a side surface of the second carrier 130 away from the first carrier 110, where the widths of the first chip 120, the second chip 140 and the third chip 160 are substantially the same, and the two second chips 140 respectively correspond to the third chip 160 and the first chip 120, so that the chips are symmetrically disposed on two sides of the carrier, and a dual-sided fan-out package structure is realized.
In this embodiment, a conductive pillar 143 is further disposed in the second plastic package 141, one end of the conductive pillar 143 extends to the second carrier 130 and is electrically connected to the second wiring layer 131, and the other end of the conductive pillar 143 extends to the wiring assembly layer 150 and is electrically connected to the wiring assembly layer 150. Specifically, conductive columns 143 are disposed on two sides of each second chip 140, and the conductive columns 143 may be copper columns and penetrate through the second plastic package 141, so that the upper wiring combination layer 150 and the second wiring layer 131 in the second carrier 130 can be electrically connected.
It should be noted that, in this embodiment, a plurality of connection pads are disposed on a side of the second carrier 130 away from the first carrier 110, and the connection pads are electrically connected to the second wiring layer 131, and the conductive columns 143 are disposed on the connection pads and electrically connected to each other.
In this embodiment, the first chip 120 is flip-chip mounted on the first carrier board 110, the first chip 120 is provided with a first conductive bump 123, a side surface of the first carrier board 110 away from the second carrier board 130 is provided with a first pad 115, the first pad 115 is electrically connected to the first wiring layer 111, and the first conductive bump 123 is bonded on the first pad 115. Specifically, the first chip 120 is electrically connected through the flip-chip structure, so that the installation requirement space can be further reduced, and miniaturization of the product is facilitated.
In this embodiment, the second chip 140 is mounted on the second carrier 130 in an inverted manner, the second chip 140 is provided with a second conductive bump 145, a side surface of the second carrier 130 away from the first carrier 110 is provided with a second pad 133, the second pad 133 is electrically connected to the second wiring layer 131, and the second conductive bump 145 is bonded to the second pad 133. Specifically, the plurality of second chips 140 are all inversely mounted on the second carrier 130, and the second chips 140 are electrically connected through the flip-chip structure, so that the installation requirement space of the second chips can be further reduced, miniaturization of products is facilitated, and meanwhile, interference between the wire bonding structure and the conductive columns 143 can be avoided to influence the electrical connection characteristics of the second chips.
In this embodiment, the third chip 160 is mounted on the second carrier 130 in an inverted manner, the third chip 160 is provided with a third conductive bump 161, a surface of the second carrier 130, which is far away from the second plastic package 141, is provided with a third pad 135, the third pad 135 is electrically connected to the second wiring layer 131, and the third conductive bump 161 is bonded on the third pad 135. Specifically, the third chip 160 is flipped on the second carrier 130 in the abdication groove 113, and is electrically connected through the flip structure, so that the installation requirement space can be further reduced, the miniaturization of the product is facilitated, and meanwhile, the wire bonding is prevented from being exposed out of the first plastic package body 121, so that the height of the first plastic package body 121 is lower, and the reduction of the device height is facilitated.
In this embodiment, the wiring combination layer 150 includes a first dielectric layer 151, a first metal layer 152, a second dielectric layer 153, a second metal layer 154, and a first solder ball 155, where the first dielectric layer 151 covers the surface of the second molding body 141, the first metal layer 152 is disposed in the first dielectric layer 151 and electrically connected to the conductive pillar 143, the second dielectric layer 153 covers the surface of the first dielectric layer 151, the second metal layer 154 is disposed in the second dielectric layer 153 and electrically connected to the first metal layer 152, and the first solder ball 155 is disposed on a side of the second dielectric layer 153 away from the second molding body 141 and electrically connected to the second metal layer 154. Specifically, after the second plastic package body 141 is formed, the fan-out type wiring structure may be completed on the surface of the second plastic package body 141, that is, the preparation of the first dielectric layer 151, the first metal layer 152, the second dielectric layer 153, the second metal layer 154, and the first solder balls 155 is sequentially completed, so as to implement the fan-out type package structure, where the basic structure and the preparation method of the wiring combination layer 150 are consistent with those of the conventional fan-out type wiring structure, and in this embodiment, reference may be made to the conventional fan-out type package structure.
The embodiment also provides a preparation method of the fan-out type double-sided package structure 100, which is used for preparing the fan-out type double-sided package structure 100, and the preparation method comprises the following steps:
S1, attaching a second carrier plate 130 to one side surface of the first carrier plate 110.
Specifically, referring to fig. 2 in combination, a first carrier plate 110 and a second carrier plate 130 are provided, wiring is completed in advance, and the first carrier plate 110 and the second carrier plate 130 are attached together, wherein line connection is achieved between the first carrier plate 110 and the second carrier plate 130, and electrical connection can be achieved through surface pad welding, that is, a first wiring layer 111 is disposed in the first carrier plate 110, a second wiring layer 131 is disposed in the second carrier plate 130, and the first wiring layer 111 and the second wiring layer 131 are electrically connected. Preferably, the solder bonding between the first carrier plate 110 and the second carrier plate 130 may be performed using solder paste, an adhesive, or using a cu-cu bonding pad high temperature annealing soldering method.
S2, grooving the first carrier plate 110 to form a yielding groove 113 and exposing the second carrier plate 130.
Specifically, referring to fig. 3 in combination, the first carrier plate 110 of the predetermined area may be removed by an etching process or a laser cutting process, to complete the slotting, and to expose the second carrier plate 130.
S3, attaching the first chip 120 on the first carrier 110.
Specifically, referring to fig. 4 in combination, the first chip 120 may be attached to a preset area of the first carrier plate 110, and in particular, the first chip 120 may be flip-chip mounted on the first carrier plate 110, and the electrical connection between the first chip 120 and the first wiring layer 111 may be achieved through the bonding between the first conductive bump 123 and the first pad 115.
S4, attaching a third chip 160 on the second carrier 130 in the abdication groove 113.
Specifically, with continued reference to fig. 4, step S3 and step S4 may be performed simultaneously, and the third chip 160 may be flip-chip bonded on the second carrier 130 in the region of the relief groove 113, and the electrical connection between the third chip 160 and the second wiring layer 131 is achieved through the bonding between the third conductive bump 161 and the third pad 135.
S5, forming a first plastic package 121 in the first carrier 110 and the abdication groove 113 and coating the first chip 120 and the third chip 160.
Specifically, referring to fig. 5, after the mounting of the first chip 120 and the third chip 160 is completed, a plastic packaging process may be performed, and a first plastic package body 121 is formed on the first carrier 110 and the second carrier 130 in the region of the relief groove 113, where the first plastic package body 121 is coated outside the first chip 120 and the third chip 160.
S6, attaching a second chip 140 on one side of the second carrier 130 away from the first chip 120.
Specifically, referring to fig. 6, the package structure of the first plastic package 121 is flipped over, and the mounting of the second chip 140 is completed on the second carrier 130. Here, the second chip 140 is flip-chip mounted on the second carrier 130, and electrical connection with the second wiring layer 131 is achieved by bonding the second conductive bump 145 and the second pad 133. Meanwhile, the second chip 140 needs to correspond to the first chip 120 and the third chip 160, respectively.
S7, forming a second plastic package 141 on the second carrier 130, wherein the second plastic package is wrapped outside the second chip 140.
Specifically, referring to fig. 7, a second molding body 141 is formed on the second carrier 130 by using a molding process, and the second molding body 141 is coated outside the second chip 140.
And S8, forming a wiring combination layer 150 on one side of the second plastic package body 141 far away from the second carrier 130.
Specifically, referring to fig. 8, after the preparation of the second molding body 141 is completed, it is first necessary to slot and plate a copper layer on the second molding body 141 to form the conductive pillars 143, the conductive pillars 143 are located at both sides of the second chip 140, and then spin-coat a dielectric material, or deposit a dielectric material, for example, by a physical vapor deposition Process (PVD), a chemical vapor deposition process (CVD) to form the first dielectric layer 151, and then pattern the first dielectric layer 151, expose and develop to form patterned openings, and plate a metal material, for example, copper, in the openings to form the first metal layer 152 and complete the wiring, wherein the first metal layer 152 is connected with the top ends of the conductive pillars 143. Then, a dielectric material is deposited again on the surface of the first dielectric layer 151 to form a second dielectric layer 153, a slot is formed on the second dielectric layer 153, and a metal material, such as copper, is electroplated in the slot, so as to form a second metal layer 154, wherein the second metal layer 154 is used as a pad structure and is electrically connected with the first metal layer 152. Then, the UBM layer is prepared on the second metal layer 154, and finally, the ball-implanting process is finished on the second metal layer 154 by means of steel screen printing or ball-implanting, so as to form the first solder balls 155, wherein the materials of the first solder balls 155 can be SnAg, snAgCu and the like. The dielectric material may be silicon nitride, silicon oxynitride, polyimide, benzocyclobutene, or the like.
After the preparation of the first solder balls 155 is completed, the dicing process is performed again, and a final product is formed.
In summary, according to the fan-out type double-sided package structure 100 and the preparation method thereof provided in the embodiment, the first carrier plate 110 and the second carrier plate 130 are attached to each other, the first chip 120 is attached to the first carrier plate 110, and the second chip 140 and the package device are attached to the second carrier plate 130, so that the double-sided fan-out type package structure is realized, meanwhile, the first wiring layer 111 is arranged in the first carrier plate 110, the second wiring layer 131 is arranged in the second carrier plate 130, and double-sided package is realized through the two carrier plates, so that the wiring density is greatly improved, the wiring requirement of higher density is realized, and the number of stacked chips is facilitated to be improved. Meanwhile, plastic package is respectively realized through the two carrier plates, so that a better supporting effect can be achieved, and the problem of plastic package warping can be relieved, so that the layering problem is relieved. The embodiment provides a fan-out type double-sided packaging structure 100, can alleviate plastic package warpage problem and layering problem, can promote wiring density by a wide margin simultaneously, has promoted chip wiring integrated level, and then promotes chip stacking quantity.
Second embodiment
Referring to fig. 9, the present embodiment provides a fan-out type double-sided package structure 100, whose basic structure and principle and technical effects are the same as those of the first embodiment, and for brevity, reference is made to the corresponding contents of the first embodiment where the description of the present embodiment is not mentioned.
The fan-out type double-sided package structure 100 provided in this embodiment includes a first carrier 110, a first chip 120, a first plastic package 121, a second carrier 130, a second chip 140, a second plastic package 141, a third plastic package 163, a wiring combination layer 150 and a package device, wherein the first chip 120 is mounted on one side surface of the first carrier 110, the first plastic package 121 is disposed on the first carrier 110 and is coated outside the first chip 120, the second carrier 130 is mounted on the other side surface of the first carrier 110, the second chip 140 is mounted on the other side surface of the second carrier 130, which is far away from the first carrier 110, the package device is mounted on the second side surface of the second carrier 130, the second plastic package 141 is coated outside the second chip 140 and the package device, a yielding groove 113 penetrating through the second carrier 130 is disposed on the first carrier 110, the third chip 160 is disposed in the yielding groove 113, a first wiring layer 111 is disposed in the first carrier 110, the second carrier 130 is disposed in the second carrier 130, the second wiring layer 131 is electrically connected to the second chip 131, and the first wiring layer 131 is electrically connected to the second chip 131. The third plastic package 163 is disposed on a side surface of the second carrier 130 away from the wiring assembly layer 150 and located in the yielding groove 113, and the third plastic package 163 is wrapped around the third chip 160.
It should be noted that, in the embodiment, the first plastic package body 121 is only located on the first carrier plate 110 and is coated outside the first chip 120, the third plastic package body 163 is disposed on the second carrier plate 130 in the yielding groove 113, and the third plastic package body 163 is coated outside the third chip 160, wherein the first plastic package body 121 and the third plastic package body 163 are formed in sequence, respectively, which can further alleviate the warpage problem.
In this embodiment, the side surface of the first plastic package body 121 far away from the second carrier 130 is flush with the side surface of the third plastic package body 163 far away from the second carrier 130, and the side walls of the first plastic package body 121 and the third plastic package body 163 are mutually jointed, so that an integral plastic package structure can be formed after molding, which is beneficial to miniaturization of the product.
The embodiment also provides a method for preparing the fan-out type double-sided package structure 100, which is used for preparing the fan-out type double-sided package structure 100 according to the embodiment, and the method comprises the following steps:
s1, a first chip 120 is attached to one side surface of the first carrier 110.
Specifically, referring to fig. 10 in combination, a first carrier plate 110 with wiring is provided, and a first chip 120 is mounted on the first carrier plate 110, wherein the first chip 120 is mounted on the first carrier plate 110 in an inverted manner. The first carrier 110 is provided with a first wiring layer 111 therein, and the first chip 120 is electrically connected to the first wiring layer 111.
S2, a first plastic package 121 is formed on the first carrier 110 and covers the first chip 120.
Specifically, referring to fig. 11 in combination, after the mounting of the first chip 120 is completed, a first plastic package body 121 is formed on the first carrier plate 110 by using a plastic package process, and the first plastic package body 121 is coated outside the first chip 120.
And S3, attaching a second carrier plate 130 to the other side surface of the first carrier plate 110.
Specifically, referring to fig. 12 in combination, the second carrier 130 is attached to the surface of the first carrier 110 away from the first plastic package 121, the second carrier 130 completes wiring in advance, and a second wiring layer 131 is provided, and electrical connection between the first carrier 110 and the second carrier 130, that is, electrical connection between the first wiring layer 111 and the second wiring layer 131 is achieved through bonding pads. Preferably, the solder bonding between the first carrier plate 110 and the second carrier plate 130 may be performed using solder paste, an adhesive, or using a cu-cu bonding pad high temperature annealing soldering method.
S4, slotting on the first plastic package body 121 and the first carrier plate to form a yielding slot 113 and exposing the second carrier plate.
Specifically, referring to fig. 13 in combination, the first plastic package body 121 and the mounting area of the first carrier plate may be removed by using an etching process or a laser cutting process, and a yielding groove 113 is formed on the first carrier plate, where the first plastic package body 121 may protect the first chip 120, and the second carrier plate may serve as a supporting member to play a supporting role.
S5, the third chip 160 is attached in the abdication groove 113.
Specifically, referring to fig. 14 in combination, a third chip 160 is mounted on the surface of the second carrier 130 in the yielding groove 113, the third chip 160 is mounted on the second carrier 130 in an inverted manner, and the third chip 160 is electrically connected to the second wiring layer 131.
And S6, forming a third plastic package 163 for coating and packaging the device in the abdication groove 113.
Specifically, referring to fig. 15 in combination, after the mounting of the third chip 160 is completed, a third plastic package 163 is formed in the yield groove 113 by using a plastic package process, wherein the first plastic package 121 and the third plastic package 163 jointly cover the surfaces of the first carrier 110 and the second carrier 130. In addition, the split type preparation of the first plastic package body 121 and the third plastic package body 163 can further make the stress on the first carrier plate 110 and the second carrier plate 130 more balanced, reduce the warpage phenomenon, and avoid the layering problem.
It should be noted that, the first plastic package body 121 and the third plastic package body 163 are used for preparation respectively, so that the problem of stress dispersion can be solved, and meanwhile, the first plastic package body 121 and the third plastic package body 163 can select the same or different plastic package materials according to the warpage degree of the double-sided package structure, so that the warpage degree, such as left warpage, of the whole double-sided package structure is balanced, and the plastic package materials with small CTE deformation are adopted for balancing.
S7, attaching a second chip 140 on the second carrier 130.
Specifically, referring to fig. 16 in combination, after the preparation of the third plastic package 163 is completed, the package structure is flipped over, and then the second chip 140 is mounted on a surface of the second carrier 130, which is far away from the first carrier 110, and the second chip 140 is electrically connected to the second wiring layer 131.
S8, forming a second plastic package 141 on the second carrier 130, wherein the second plastic package is coated outside the second chip 140.
Specifically, referring to fig. 17 in combination, after the mounting of the second chip 140 is completed, a second plastic package 141 is formed on the second carrier 130 again, and the second plastic package 141 is coated outside the second chip 140.
And S9, forming a wiring combination layer 150 on the second plastic package 141.
Specifically, referring to fig. 18 in combination, after the preparation of the second molding body 141 is completed, a wiring combination layer 150 is formed on the surface of the second molding body 141, and the wiring combination layer 150 is electrically connected to the second wiring layer 131, and the specific process thereof is the same as the first embodiment.
In summary, the present embodiment provides a fan-out type double-sided package structure 100 and a method for manufacturing the same, in which a first carrier plate 110 and a second carrier plate 130 are attached to each other, a first chip 120 is attached to the first carrier plate 110, and a second chip 140 and a package device are attached to the second carrier plate 130, so that the double-sided fan-out type package structure is realized, meanwhile, a first wiring layer 111 is disposed in the first carrier plate 110, a second wiring layer 131 is disposed in the second carrier plate 130, and double-sided package is realized through the two carrier plates, so that wiring density is greatly improved, wiring requirements of higher density are realized, and the number of stacked chips is facilitated to be improved. Meanwhile, plastic package is respectively realized through the two carrier plates, so that a better supporting effect can be achieved, and the problem of plastic package warping can be relieved, so that the layering problem is relieved. The embodiment provides a fan-out type double-sided packaging structure 100, can alleviate plastic package warpage problem and layering problem, can promote wiring density by a wide margin simultaneously, has promoted chip wiring integrated level, and then promotes chip stacking quantity. In addition, as the first plastic package body 121 and the third plastic package body 163 are prepared separately, the stress on the first carrier plate 110 and the second carrier plate 130 can be more balanced, the warping phenomenon is reduced, and the layering problem is avoided.
Third embodiment
Referring to fig. 19, the present embodiment provides a fan-out type double-sided package structure 100, whose basic structure and principle and technical effects are the same as those of the first embodiment, and for brevity, reference is made to the corresponding contents of the first embodiment where the description of the present embodiment is not mentioned.
In this embodiment, a plurality of second chips 140 are provided, each second chip 140 is provided with a second conductive bump 145, at least one second chip 140 is being mounted on the second carrier 130 such that the corresponding second conductive bump 145 is bonded on the first dielectric layer 151, a third wiring layer 156 is further provided in the first dielectric layer 151, a conductive layer 157 is further provided in the second dielectric layer 153, a second solder ball 158 is further provided on the second dielectric layer 153, the third wiring layer 156 is electrically connected with the second conductive bump 145 bonded on the first dielectric layer 151, the conductive layer 157 is electrically connected with the third wiring layer 156, the second solder ball 158 is electrically connected with the conductive layer 157, and the third wiring layer 156 is electrically isolated from the first metal layer 152 such that the third wiring layer 156 is individually wired in the first dielectric layer 151.
Specifically, in this embodiment, two second chips 140 are mounted on the second carrier 130, one is mounted on the second carrier 130 in a flip-chip manner, and the other is mounted on the second carrier 130, and the second conductive bumps 145 corresponding to the second chip 140 are bonded on the first dielectric layer 151, and are electrically connected to each other individually through the third wiring layer 156, the conductive layer 157 and the second solder balls 158, so that the chip is easy to be positioned quickly when the chip test fails.
In this embodiment, the second chips 140 on the second carrier 130 are disposed in opposite directions, wherein one of the second chips 140 is disposed in a flip-chip manner, and the basic connection structure is the same as that of the first embodiment, and the other second chip 140 is disposed in a positive manner and is electrically connected to the third wiring layer 156 disposed in the first dielectric layer 151 through the second conductive bump 145, and the third wiring layer 156 is electrically isolated from the first metal layer 152, so that the second chip 140 disposed in a positive manner is in an electrically isolated state with the common wiring structure, and separate wiring is realized. When the subsequent chip test fails, the position of the second chip 140 in the independent wiring area can be rapidly positioned, and meanwhile, the adjacent second chips 140 are reversely placed, so that the diversity of wiring structures can be improved, namely, independent wiring is realized from the upper part. Specifically, during chip failure analysis, the chip positions of the independent wiring areas (such as X-ray failure analysis-chip position reversal, chip back film analysis-reduction of the surface and back heights of the chip bonding pads, chip slicing analysis-position reversal and the like) can be rapidly positioned, and the problems that the traditional double-sided package cannot realize chip reversal placement and the independent chip wiring design and analysis cannot be realized are solved.
Fourth embodiment
Referring to fig. 20, the present embodiment provides a fan-out type double-sided package structure 100, whose basic structure and principle and technical effects are the same as those of the first embodiment, and for brevity, reference is made to the corresponding contents of the first embodiment where the description of the present embodiment is not mentioned.
In this embodiment, the package device includes a first heat dissipation block 170, the first heat dissipation block 170 is attached to the second carrier 130, the first plastic package 121 is wrapped around the first heat dissipation block 170, and a side of the first heat dissipation block 170 away from the second carrier 130 is exposed to the first plastic package 121. Specifically, compared to the first embodiment, the position of the third chip 160 is replaced with the first heat sink 170 in the present embodiment.
In this embodiment, the first heat dissipation block 170 is disposed in the yielding groove 113 and attached to the second carrier 130, and the first heat dissipation block 170 is exposed, so that direct heat dissipation on the back of the second carrier 130 can be achieved, and heat generated by the front second chip 140 can be dissipated from the bottom, thereby improving heat dissipation performance.
It should be noted that, the first heat dissipation block 170 may be a metal block or a ceramic block, or may be a heat dissipation silica gel, which is used to play a role in buffering, so as to further solve the warpage problem of the double-sided package product.
Fifth embodiment
Referring to fig. 21, the present embodiment provides a fan-out type double-sided package structure 100, whose basic structure and principle and technical effects are the same as those of the first embodiment or the fourth embodiment, and for brevity, reference may be made to the corresponding contents of the first embodiment or the fourth embodiment where the parts of the present embodiment are not mentioned.
In this embodiment, the second carrier 130 is further provided with a second heat dissipating block 180, the second heat dissipating block 180 is attached to a side surface of the second carrier 130 away from the first carrier 110, the second plastic package 141 is coated outside the second heat dissipating block 180, and the second heat dissipating block 180 and the package device are correspondingly disposed on two side surfaces of the second carrier 130. Specifically, compared with the first embodiment, in this embodiment, the second heat dissipation block 180 is used to replace the second chip 140 at the position corresponding to the third chip 160, and the second heat dissipation block 180 is directly contacted with the second carrier 130, so that a good heat dissipation effect can be achieved.
In the embodiment, the height of the second heat dissipating block 180 is the same as the height of the second plastic package 141, so that the second heat dissipating block 180 can be directly bonded to the bottom of the wiring assembly layer 150, so that the heat on the second carrier 130 is quickly conducted to the wiring assembly layer 150 and is transferred outwards through the wiring assembly layer 150, thereby improving the heat dissipation between the first solder balls 155 and the assembly substrate.
It should be noted that, here, by setting the second heat dissipating block 180, the welding strength of the solder ball area can be improved, which is beneficial to firm welding.
In this embodiment, the second heat dissipation block 180 may be a metal block or a ceramic block, or may be a heat dissipation silica gel, which is used to play a role in buffering, so as to further solve the warpage problem of the double-sided package product.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.