CN114709216A - pFlash structure and preparation method thereof - Google Patents
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Abstract
Description
Translated fromChinese技术领域technical field
本发明属于半导体技术领域，涉及一种pFlash结构及其制备方法。The invention belongs to the technical field of semiconductors, and relates to a pFlash structure and a preparation method thereof.
背景技术Background technique
快闪存储器(Flash Memory)是一种非挥发性存储集成电路，其主要特点是工作速度快、单元面积小、集成度高、可靠性好、可重复擦写10万次以上，数据可靠保持超过10年。嵌入式Flash（Embedded Flash，简称EMB Flash）在MCU(microcontroller Unit，微控制器)和DSP(Digital Signal Process，数字信号处理器)中得到越来越广泛的应用，几乎所有的MCU和DSP都带有嵌入式Flash。Flash memory (Flash Memory) is a non-volatile memory integrated circuit, its main features are fast working speed, small unit area, high integration, good reliability, can be repeatedly erased and written more than 100,000 times, and the data can be reliably maintained for more than 100,000 times. 10 years. Embedded Flash (Embedded Flash, referred to as EMB Flash) is more and more widely used in MCU (microcontroller Unit, microcontroller) and DSP (Digital Signal Process, digital signal processor), almost all MCUs and DSPs have Has embedded Flash.
根据产生电流的载流子类型不同，FLASH基本单元可分为nFLASH和pFLASH。目前的嵌入式pFlash的浮栅采用的是N型掺杂，相应的选择栅也是N型掺杂。由于选择栅晶体管是PMOS，但栅是N型，所以选择栅晶体管是埋层沟道（有一道P型离子注入在选择栅晶体管的硅表面）。According to the different types of carriers that generate current, FLASH basic units can be divided into nFLASH and pFLASH. The floating gate of the current embedded pFlash adopts N-type doping, and the corresponding select gate is also N-type doped. Since the select gate transistor is PMOS, but the gate is N-type, the select gate transistor is a buried channel (there is a P-type ion implantation on the silicon surface of the select gate transistor).
埋层沟道选择栅晶体管因为有一道P型离子注入在选择栅晶体管的硅表面，源极和漏极之间的亚阈值漏电流性能（Sub_Threshold leak performance）不好，所以选择栅晶体管的阈值电压（绝对值）要比较大（一般大于1.45 V）才能满足较小漏电的需求。选择栅晶体管的阈值电压（绝对值）比较大会限制写操作后的读操作电流，不利于单元收缩（cellshrinkage），也不利于耐久性（endurance performance），尤其是低电源电压（Vcc）时的耐久性。另外较大的选择栅晶体管亚阈值漏电流会导致循环（cycling）时选择栅晶体管容易退化（degradation），特别是在写入操作时被选中扇区的未被选中选择栅的存储单元在偏压条件下时和擦除操作时被选中扇区的存储单元在偏压条件下时。The buried channel select gate transistor has a P-type ion implantation on the silicon surface of the select gate transistor, and the sub-threshold leakage current performance (Sub_Threshold leak performance) between the source and drain is not good, so the threshold voltage of the select gate transistor is (absolute value) must be larger (generally greater than 1.45 V) to meet the needs of small leakage. The threshold voltage (absolute value) of the select gate transistor will limit the read operation current after the write operation, which is not conducive to cell shrinkage (cellshrinkage), nor is it conducive to endurance performance (endurance performance), especially the durability at low power supply voltage (Vcc) sex. In addition, the large sub-threshold leakage current of the select gate transistor will cause the select gate transistor to be easily degraded during cycling, especially the memory cells of the unselected select gate of the selected sector during the write operation are biased condition and when the memory cells of the selected sector are under bias conditions during the erase operation.
因此，如何提供一种新的pFlash结构及其制备方法以改善存储单元的写入性能和擦除性能，成为本领域技术人员亟待解决的一个重要技术问题。Therefore, how to provide a new pFlash structure and a preparation method thereof to improve the writing performance and erasing performance of the memory cell has become an important technical problem to be solved urgently by those skilled in the art.
发明内容SUMMARY OF THE INVENTION
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种pFlash结构及其制备方法，用于解决现有闪存结构中，闪存单元尺寸难以缩小、耐久性较差的问题。In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a pFlash structure and a preparation method thereof, which are used to solve the problems of difficulty in reducing the size of flash memory cells and poor durability in the existing flash memory structure.
为实现上述目的及其他相关目的，本发明提供一种pFlash结构，包括：In order to realize the above-mentioned purpose and other related purposes, the present invention provides a kind of pFlash structure, including:
N型半导体层；N-type semiconductor layer;
存储单元，包括P型源区、P型内部节点区、P型漏区、控制栅结构及选择栅结构，所述P型源区、所述P型内部节点区及所述P型漏区均位于所述N型半导体层中，所述P型内部节点区位于所述P型源区与所述P型漏区之间并分别与所述P型源区、所述P型漏区间隔预设距离，所述控制栅结构位于所述N型半导体层上并横跨于所述P型源区与所述P型内部节点区之间，所述选择栅结构位于所述N型半导体层上并横跨于所述P型内部节点区与所述P型漏区之间，所述控制栅结构与所述选择栅结构均包括自下而上依次层叠的隧穿介质层、P型浮栅层、隔离层及P型逻辑层。A memory cell includes a P-type source region, a P-type internal node region, a P-type drain region, a control gate structure and a select gate structure, wherein the P-type source region, the P-type internal node region and the P-type drain region are all Located in the N-type semiconductor layer, the P-type internal node region is located between the P-type source region and the P-type drain region, and is respectively spaced from the P-type source region and the P-type drain region in advance. Set a distance, the control gate structure is located on the N-type semiconductor layer and spans between the P-type source region and the P-type internal node region, and the select gate structure is located on the N-type semiconductor layer and spanning between the P-type internal node region and the P-type drain region, the control gate structure and the selection gate structure both include a tunnel dielectric layer and a P-type floating gate sequentially stacked from bottom to top layer, isolation layer and P-type logic layer.
可选地，所述P型浮栅层包括P型多晶硅，所述P型逻辑层包括P型多晶硅。Optionally, the P-type floating gate layer includes P-type polysilicon, and the P-type logic layer includes P-type polysilicon.
可选地，所述隔离层包括氧化硅层-氮化硅层-氧化硅层叠层结构。Optionally, the isolation layer includes a silicon oxide layer-silicon nitride layer-silicon oxide stacked layer structure.
可选地，在读取操作时，所述控制栅结构的P型逻辑层接负电压。Optionally, during a read operation, the P-type logic layer of the control gate structure is connected to a negative voltage.
可选地，所述N型半导体层包括N型掺杂硅衬底，或所述N型半导体层包括形成于P型硅衬底中的N型阱区。Optionally, the N-type semiconductor layer includes an N-type doped silicon substrate, or the N-type semiconductor layer includes an N-type well region formed in a P-type silicon substrate.
本发明还提供一种pFlash结构的制作方法，包括以下步骤：The present invention also provides a method for making a pFlash structure, comprising the following steps:
提供一N型半导体层；providing an N-type semiconductor layer;
基于所述N型半导体层形成存储单元，所述存储单元包括P型源区、P型内部节点区、P型漏区、控制栅结构及选择栅结构，所述P型源区、所述P型内部节点区及所述P型漏区均位于所述N型半导体层中，所述P型内部节点区位于所述P型源区与所述P型漏区之间并分别与所述P型源区、所述P型漏区间隔预设距离，所述控制栅结构位于所述N型半导体层上并横跨于所述P型源区与所述P型内部节点区之间，所述选择栅结构位于所述N型半导体层上并横跨于所述P型内部节点区与所述P型漏区之间，所述控制栅结构与所述选择栅结构均包括自下而上依次层叠的隧穿介质层、P型浮栅层、隔离层及P型逻辑层。A memory cell is formed based on the N-type semiconductor layer. The memory cell includes a P-type source region, a P-type internal node region, a P-type drain region, a control gate structure and a select gate structure. Both the P-type internal node region and the P-type drain region are located in the N-type semiconductor layer, and the P-type internal node region is located between the P-type source region and the P-type drain region and is respectively connected to the P-type internal node region. The P-type source region and the P-type drain region are separated by a predetermined distance, the control gate structure is located on the N-type semiconductor layer and spans between the P-type source region and the P-type internal node region, so The selection gate structure is located on the N-type semiconductor layer and spans between the P-type internal node region and the P-type drain region, and both the control gate structure and the selection gate structure include bottom-up A tunnel dielectric layer, a P-type floating gate layer, an isolation layer and a P-type logic layer are stacked in sequence.
可选地，所述控制栅结构的P型浮栅层与所述选择栅结构的P型浮栅层在同一沉积步骤及同一P型掺杂步骤中形成。Optionally, the P-type floating gate layer of the control gate structure and the P-type floating gate layer of the select gate structure are formed in the same deposition step and the same P-type doping step.
可选地，所述P型浮栅层包括P型多晶硅，所述P型逻辑层包括P型多晶硅；所述隔离层包括氧化硅层-氮化硅层-氧化硅层叠层结构。Optionally, the P-type floating gate layer includes P-type polysilicon, the P-type logic layer includes P-type polysilicon, and the isolation layer includes a silicon oxide layer-silicon nitride layer-silicon oxide stacked layer structure.
可选地，在读取操作时，所述控制栅结构的P型逻辑层接负电压。Optionally, during a read operation, the P-type logic layer of the control gate structure is connected to a negative voltage.
可选地，所述N型半导体层包括N型掺杂硅衬底，或所述N型半导体层是通过离子注入形成于P型硅衬底中的N型阱区。Optionally, the N-type semiconductor layer includes an N-type doped silicon substrate, or the N-type semiconductor layer is an N-type well region formed in the P-type silicon substrate by ion implantation.
如上所述，本发明的pFlash结构及其制备方法采用P型浮栅代替pFlash的N型浮栅，可以把选择晶体管从埋层沟道变为表面沟道，可以显著减小选择栅晶体管的阈值电压（绝对值），显著改善选择栅晶体管的亚阈值漏电流。另外选择栅晶体管的阈值电压（绝对值）显著减小，可以显著增加写入操作后的电流，对存储单元收缩和改善耐久性都很有帮助，其中，选择栅晶体管的亚阈值漏电流的显著改善可以改善写入操作时未选中选择栅的存储单元在偏压条件下时的选择栅晶体管耐久性，并可以改善擦除操作时被选中扇区的存储单元在偏压条件下时的选择晶体管耐久性，从而改善写入性能与擦除性能，即便是在100K次循环后。As mentioned above, the pFlash structure and its preparation method of the present invention use a P-type floating gate to replace the N-type floating gate of the pFlash, so that the selection transistor can be changed from a buried layer channel to a surface channel, and the threshold value of the selection gate transistor can be significantly reduced voltage (absolute value), significantly improving the subthreshold leakage current of select gate transistors. In addition, the threshold voltage (absolute value) of the select gate transistor is significantly reduced, which can significantly increase the current after the write operation, which is helpful for the shrinkage of the memory cell and the improvement of endurance. Among them, the subthreshold leakage current of the select gate transistor is significantly reduced. Improvements can improve select gate transistor endurance under bias conditions for memory cells with unselected select gates during write operations, and can improve select transistors for memory cells in selected sectors during erase operations under bias conditions Endurance, resulting in improved write and erase performance, even after 100K cycles.
附图说明Description of drawings
图1显示为本发明的pFlash结构的剖面结构示意图。FIG. 1 is a schematic cross-sectional structure diagram of the pFlash structure of the present invention.
图2显示为采用N型浮栅的pFlash结构与采用P型浮栅的pFlash结构的写入/擦除窗口比对图。FIG. 2 shows a comparison diagram of write/erase windows of a pFlash structure using an N-type floating gate and a pFlash structure using a P-type floating gate.
元件标号说明：1 N型半导体层，2 P型源区，3 P型内部节点区，4 P型漏区，5 控制栅结构，501 隧穿介质层，502 P型浮栅层，503 隔离层，504 P型逻辑层，6 选择栅结构，601隧穿介质层，602 P型浮栅层，603 隔离层，604 P型逻辑层，7 侧墙，8 保护层，9 层间介质层。Description of component numbers: 1 N-type semiconductor layer, 2 P-type source region, 3 P-type internal node region, 4 P-type drain region, 5 Control gate structure, 501 Tunneling dielectric layer, 502 P-type floating gate layer, 503 Isolation layer , 504 P-type logic layer, 6 select gate structure, 601 tunneling dielectric layer, 602 P-type floating gate layer, 603 isolation layer, 604 P-type logic layer, 7 spacers, 8 protective layers, 9 interlayer dielectric layers.
具体实施方式Detailed ways
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。The embodiments of the present invention are described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
请参阅图1至图2。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。See Figures 1 to 2. It should be noted that the drawings provided in this embodiment are only to illustrate the basic concept of the present invention in a schematic way, so the drawings only show the components related to the present invention rather than the number, shape and the number of components in actual implementation. For dimension drawing, the type, quantity and proportion of each component can be changed at will in actual implementation, and the component layout may also be more complicated.
如下表一所示，为位线被选中存储单元的一种操作偏压条件，其中，写入操作时被选中扇区的未被选中选择栅的存储单元的偏压条件以及擦除操作时被选中扇区的存储单元的偏压条件是选择栅晶体管在100K次循环期间主要的退化应力条件。由写入操作时被选中扇区的未被选中选择栅的存储单元的偏压条件、擦除操作时被选中扇区的存储单元的偏压条件及读取操作时被选择扇区的存储单元的偏压条件可以看出，较大的选择栅晶体管阈值电压（绝对值）会显著减小写操作后的读电流，不利于存储单元收缩及其耐久性，即便是在低Vcc条件下。As shown in Table 1 below, it is an operation bias condition of the selected memory cell of the bit line, wherein the bias condition of the memory cell of the unselected selection gate of the selected sector during the writing operation and the bias condition of the memory cell during the erasing operation are The bias condition of the memory cells of the selected sector is the dominant degradation stress condition of the select gate transistor during 100K cycles. The bias conditions of the memory cells of the unselected gate of the selected sector during the write operation, the bias conditions of the memory cells of the selected sector during the erase operation and the memory cells of the selected sector during the read operation It can be seen that a larger select gate transistor threshold voltage (absolute value) will significantly reduce the read current after a write operation, which is not conducive to memory cell shrinkage and its durability, even at low Vcc conditions.
表一：位线被选中存储单元的操作偏压条件Table 1: The operating bias conditions of the selected memory cell on the bit line
其中，Vcc表示电源电压，Vtn表示NMOS晶体管阈值电压，Vtp表示PMOS晶体管阈值电压。Among them, Vcc represents the power supply voltage, Vtn represents the threshold voltage of the NMOS transistor, and Vtp represents the threshold voltage of the PMOS transistor.
因此，本发明对pFlash结构进行改进，采用P型浮栅代替N型浮栅，从而改善存储单元的写入性能与擦除性能，有利于存储单元收缩并改善耐久性。Therefore, the present invention improves the pFlash structure and adopts the P-type floating gate instead of the N-type floating gate, thereby improving the writing performance and erasing performance of the memory cell, which is beneficial to the shrinkage of the memory cell and improves the durability.
实施例一Example 1
本实施例中提供一种pFlash结构，请参阅图1，显示为该pFlash结构的剖面结构示意图，包括N型半导体层1及存储单元，所述存储单元包括P型源区2、P型内部节点区3、P型漏区4、控制栅结构5及选择栅结构6，所述P型源区2、所述P型内部节点区3及所述P型漏区4均位于所述N型半导体层1中，所述P型内部节点区3位于所述P型源区2与所述P型漏区4之间并分别与所述P型源区2、所述P型漏区4间隔预设距离，所述控制栅结构5位于所述N型半导体层1上并横跨于所述P型源区2与所述P型内部节点区3之间，所述选择栅结构6位于所述N型半导体层1上并横跨于所述P型内部节点区3与所述P型漏区4之间，所述控制栅结构5包括自下而上依次层叠的隧穿介质层501、P型浮栅层502、隔离层503及P型逻辑层504，所述选择栅结构6包括自下而上依次层叠的隧穿介质层601、P型浮栅层602、隔离层603及P型逻辑层604。This embodiment provides a pFlash structure. Please refer to FIG. 1 , which is a schematic cross-sectional structure diagram of the pFlash structure, including an N-
具体的，所述控制栅结构5作为控制栅晶体管的组成部分，所述选择栅结构6作为选择栅的晶体管的组成部分，其中，所述P型源区2作为所述控制栅晶体管的源区，所述P型内部节点区3同时作为所述控制栅晶体管的漏区与所述选择栅晶体管的源区，所述P型漏区4作为所述选择栅晶体管的漏区，从而所述控制栅晶体管与所述选择栅晶体管串联。Specifically, the
作为示例，所述N型半导体层1可以是N型掺杂硅衬底，也可以是形成于P型硅衬底中的N型阱区，所述P型源区2、所述P型内部节点区3与所述P型漏区4的掺杂浓度均高于所述N型半导体层1的掺杂浓度。As an example, the N-
作为示例，所述控制栅结构5与所述选择栅结构6的隧穿介质层包括热氧化法生长的二氧化硅，P型浮栅层包括P型多晶硅，隔离层包括氧化硅层-氮化硅层-氧化硅层叠层结构，P型逻辑层包括P型多晶硅。As an example, the tunnel dielectric layer of the
作为示例，所述pFlash结构还包括位于所述控制栅结构5两侧及所述选择栅结构6两侧的侧墙7，并包括覆盖所述控制栅结构5两侧及所述选择栅结构6的保护层8及位于所述保护层8上的层间介质层9，所述侧墙7可包括氧化硅层、氮化硅层中的至少一种，所述保护层8可选用氮化硅层或其它合适的绝缘层，所述层间介质层9可选用氧化硅层或其它合适的绝缘层。As an example, the pFlash structure further includes
本实施例的N型浮栅的pFlash结构中，所述P型源区2接源线SL，所述P型漏区4接位线BL，所述控制栅结构5的P型逻辑层接控制栅线CG，所述选择栅结构6的P型浮栅层接选择栅线SG。In the pFlash structure of the N-type floating gate of this embodiment, the P-
作为示例，所述选择栅结构6的P型浮栅层的引出区域不与所述选择栅结构6的P型逻辑层所在区域重叠。As an example, the lead-out region of the P-type floating gate layer of the
请参阅图2，显示为采用N型浮栅的pFlash结构与采用P型浮栅的pFlash结构的写入/擦除窗口比对图，其中，Vcg表示控制栅电压。由图2可见，由于功函数的差异，采用P型浮栅的pFlash结构的写入/擦除窗口会往擦除端偏移2 V左右，窗口大小不变。因此，可以对读操作偏压条件进行优化，在读取操作时，在本实施的pFlash结构的控制栅结构的P型逻辑层接负电压。Please refer to FIG. 2 , which is a comparison diagram of the write/erase window of the pFlash structure using the N-type floating gate and the pFlash structure using the P-type floating gate, wherein Vcg represents the control gate voltage. As can be seen from Figure 2, due to the difference in work function, the write/erase window of the pFlash structure using the P-type floating gate will shift to the erase end by about 2 V, and the window size will remain unchanged. Therefore, the bias conditions of the read operation can be optimized. During the read operation, the P-type logic layer of the control gate structure of the pFlash structure of the present embodiment is connected to a negative voltage.
如下表二所示，为本实施例的P型浮栅pFlash结构的位线被选中存储单元的一种读操作偏压条件，其中，控制栅施加-2 V电压代替之前的0V。As shown in Table 2 below, a read operation bias condition for the selected memory cell of the bit line of the P-type floating gate pFlash structure of the present embodiment, wherein the control gate applies a voltage of -2 V instead of the previous 0V.
表二：P型浮栅pFlash结构的位线被选中存储单元的读操作偏压条件Table 2: Bias voltage conditions for read operation of the selected memory cell of the P-type floating gate pFlash structure
本实施例的pFlash结构采用P型浮栅代替pFlash的N型浮栅，可以把选择晶体管从埋层沟道变为表面沟道。由于功函数的差异，表面沟道选择栅晶体管的阈值电压（绝对值）可以做到0.85 V左右，远小于埋层沟道时的1.45 V，这样可以大幅提高写操作后的读电流，有利于单元收缩。其中，选用埋层沟道选择栅晶体管时，单元到0.11 μm节点就很难收缩了，主要是写操作后的读电流太小；而选用表面沟道选择栅晶体管，单元可以收缩到55 nm节点或40 nm节点，甚至28 nm技术节点。由于表面沟道选择栅晶体管的亚阈值漏电流会明显减小，会改善写操作时非选择单元在偏压条件下时选择栅晶体管的退化性能，并改善擦除操作时被选择单元在偏压条件下时选择栅晶体管的退化性能，从而改善写入性能与擦除性能，即便是在100K次循环后。In the pFlash structure of this embodiment, a P-type floating gate is used to replace the N-type floating gate of the pFlash, so that the selection transistor can be changed from a buried channel to a surface channel. Due to the difference in work function, the threshold voltage (absolute value) of the surface channel select gate transistor can be about 0.85 V, which is much smaller than 1.45 V in the buried channel, which can greatly improve the read current after the write operation, which is beneficial to Unit shrinks. Among them, when the buried channel select gate transistor is used, it is difficult to shrink the cell to the 0.11 μm node, mainly because the read current after the write operation is too small; and when the surface channel select gate transistor is used, the cell can shrink to the 55 nm node. Or the 40 nm node, or even the 28 nm technology node. Since the sub-threshold leakage current of the surface channel select gate transistor will be significantly reduced, it will improve the degradation performance of the select gate transistor when the non-selected cell is under the bias condition during the write operation, and improve the selected cell during the erase operation. Degradation of select gate transistors under constant conditions, resulting in improved write and erase performance, even after 100K cycles.
实施例二
本实施例提供一种pFlash结构的制作方法，包括以下步骤：The present embodiment provides a method for making a pFlash structure, comprising the following steps:
S1：提供一N型半导体层；S1: provide an N-type semiconductor layer;
S2：基于所述N型半导体层形成存储单元，所述存储单元包括P型源区、P型内部节点区、P型漏区、控制栅结构及选择栅结构，所述P型源区、所述P型内部节点区及所述P型漏区均位于所述N型半导体层中，所述P型内部节点区位于所述P型源区与所述P型漏区之间并分别与所述P型源区、所述P型漏区间隔预设距离，所述控制栅结构位于所述N型半导体层上并横跨于所述P型源区与所述P型内部节点区之间，所述选择栅结构位于所述N型半导体层上并横跨于所述P型内部节点区与所述P型漏区之间，所述控制栅结构与所述选择栅结构均包括自下而上依次层叠的隧穿介质层、P型浮栅层、隔离层及P型逻辑层。S2: A memory cell is formed based on the N-type semiconductor layer, the memory cell includes a P-type source region, a P-type internal node region, a P-type drain region, a control gate structure and a selection gate structure, the P-type source region, all The P-type internal node region and the P-type drain region are both located in the N-type semiconductor layer, and the P-type internal node region is located between the P-type source region and the P-type drain region and is respectively connected to the N-type semiconductor layer. The P-type source region and the P-type drain region are separated by a predetermined distance, and the control gate structure is located on the N-type semiconductor layer and spans between the P-type source region and the P-type internal node region , the selection gate structure is located on the N-type semiconductor layer and spans between the P-type internal node region and the P-type drain region, and both the control gate structure and the selection gate structure include bottom The tunnel dielectric layer, the P-type floating gate layer, the isolation layer and the P-type logic layer are stacked in sequence.
作为示例，所述控制栅结构的P型浮栅层与所述选择栅结构的P型浮栅层在同一沉积步骤及同一P型掺杂步骤中形成，仅使用一道掩膜，工艺简单且有助于降低成本。As an example, the P-type floating gate layer of the control gate structure and the P-type floating gate layer of the select gate structure are formed in the same deposition step and the same P-type doping step, using only one mask, the process is simple and efficient Help reduce costs.
作为示例，可以边沉积边掺杂以形成所述P型浮栅层，也可以先沉积得到未掺杂的浮栅层，再进行P型离子注入以得到所述P型浮栅层。As an example, the P-type floating gate layer may be formed by doping during deposition, or an undoped floating gate layer may be obtained by first deposition, and then P-type ion implantation may be performed to obtain the P-type floating gate layer.
作为示例，所述N型半导体层可以是N型掺杂硅衬底，也可以是通过离子注入形成于P型硅衬底中的N型阱区，所述P型浮栅层包括P型多晶硅，所述隔离层包括氧化硅层-氮化硅层-氧化硅层叠层结构，所述P型逻辑层包括P型多晶硅。As an example, the N-type semiconductor layer may be an N-type doped silicon substrate, or an N-type well region formed in a P-type silicon substrate by ion implantation, and the P-type floating gate layer includes P-type polysilicon , the isolation layer includes a silicon oxide layer-silicon nitride layer-silicon oxide stacked layer structure, and the P-type logic layer includes P-type polysilicon.
作为示例，在读取操作时，所述控制栅结构的P型逻辑层接负电压。As an example, during a read operation, the P-type logic layer of the control gate structure is connected to a negative voltage.
本实施例的pFlash结构的制作方法工艺简单，通过制作P型浮栅，可以把选择晶体管从埋层沟道变为表面沟道，显著减小选择栅晶体管的阈值电压（绝对值），显著改善选择栅晶体管的亚阈值漏电流，显著增加写入操作后的电流，对存储单元收缩和改善耐久性都很有帮助。The fabrication method of the pFlash structure in this embodiment is simple in process. By fabricating the P-type floating gate, the selection transistor can be changed from a buried channel to a surface channel, which can significantly reduce the threshold voltage (absolute value) of the selection gate transistor and significantly improve the The subthreshold leakage current of select gate transistors, which significantly increases the current after write operations, is helpful for both memory cell shrinkage and improved endurance.
综上所述，本发明的pFlash结构及其制备方法采用P型浮栅代替pFlash的N型浮栅，可以把选择晶体管从埋层沟道变为表面沟道，可以显著减小选择栅晶体管的阈值电压（绝对值），显著改善选择栅晶体管的亚阈值漏电流。另外选择栅晶体管的阈值电压（绝对值）显著减小，可以显著增加写入操作后的电流，对存储单元收缩和改善耐久性都很有帮助，其中，选择栅晶体管的亚阈值漏电流的显著改善可以改善写入操作时未选中选择栅的存储单元在偏压条件下时的选择栅晶体管耐久性，并可以改善擦除操作时被选中扇区的存储单元在偏压条件下时的选择晶体管耐久性，从而改善写入性能与擦除性能，即便是在100K次循环后。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。To sum up, the pFlash structure and its preparation method of the present invention use a P-type floating gate to replace the N-type floating gate of the pFlash, so that the selection transistor can be changed from a buried channel to a surface channel, and the cost of the selection gate transistor can be significantly reduced. Threshold voltage (absolute value), significantly improving the subthreshold leakage current of select gate transistors. In addition, the threshold voltage (absolute value) of the select gate transistor is significantly reduced, which can significantly increase the current after the write operation, which is helpful for the shrinkage of the memory cell and the improvement of endurance. Among them, the subthreshold leakage current of the select gate transistor is significantly reduced. Improvements can improve select gate transistor endurance under bias conditions for memory cells with unselected select gates during write operations, and can improve select transistors for memory cells in selected sectors during erase operations under bias conditions Endurance, resulting in improved write and erase performance, even after 100K cycles. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。The above-mentioned embodiments merely illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed in the present invention should still be covered by the claims of the present invention.
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