CN114691375B - Integrated circuit resistance extraction method based on parallel algorithm - Google Patents

Abstract

The invention relates to a thread processing method in the field of integrated circuits, in particular to an integrated circuit resistance extraction method based on a parallel algorithm, which comprises the following steps; reading layout information, and storing all conductors in corresponding units according to the coordinates of the conductors or the via holes and the layers to which the conductors or the via holes belong; firstly, establishing a thread pool, and establishing a task adding thread pool for each conductor layer of each unit; then, starting threads according to the thread number configured by the user, and performing the following operations on each thread: step two, taking out a task from the thread pool; traversing all conductors in the task, and creating nodes at the positions contacted with other conductors or via holes; step two, the created nodes and the conductors or the through holes corresponding to the nodes are returned to the main process; and step three, all threads run to the end, all nodes are stored in the conductor, and repeated nodes are deleted.

Description

Integrated circuit resistance extraction method based on parallel algorithm

Technical Field

The invention relates to a thread processing method in the field of integrated circuits, in particular to an integrated circuit resistance extraction method based on a parallel algorithm.

Background

In the process of extracting the resistance of the integrated circuit, the connection relation of the circuit needs to be found, and then the resistance is calculated according to the resistivity. This part is time consuming as the circuit scale increases, so that large scale circuits use multiple processes or multiple threads. The existing tools are made in several ways: the first approach is to divide the circuit into several units, each using a process or thread. This method requires that conductors across the cell boundary be cut and finally connected at the boundary. This approach is difficult to handle in some cases. Such as the case of fig. 2. Theconductor 2 is cut into 4 parts and finally the connection of the resistors is cumbersome and inaccurate. The second approach is to use one thread per layer. This method does not suffer from the problem of method one, but the number of threads is limited. Such as: if a circuit has 12 metal layers (M1-M12), the method can be processed with up to 12 threads. This approach is not applicable if the circuit is very large, requiring more threads.

Disclosure of Invention

The invention provides an integrated circuit resistance extraction method based on a multithreading parallel algorithm.

In order to solve the problems, the technical scheme adopted by the invention is as follows:

an integrated circuit resistance extraction method based on a parallel algorithm is characterized in that: comprises the following steps;

reading layout information, and storing all conductors in corresponding units according to the coordinates of the conductors or the via holes and the layers to which the conductors or the via holes belong; if the conductors cross the boundary, appearing in different other cells, a pointer to a conductor is maintained in each cell.

The layout information format generally includes LEFDEF or Calibre Connectivity Interface (CCI), the CCI Interface is preferably used in the present application, and the layout information is in GDS format. The information in the layout comprises conductors on all conductor layers of the layout and via holes on all via hole layers;

firstly, establishing a thread pool, and establishing a task adding thread pool for each conductor layer of each unit; then, starting threads according to the thread number configured by the user, and performing the following operations on each thread:

step two, taking out a task from the thread pool, and taking out the task according to a storage sequence for convenience;

step two, traversing all conductors in the task, and creating nodes at the positions where the conductors are contacted with other conductors or through holes, wherein the nodes comprise information including layer numbers and coordinates;

step two, the created nodes and the conductors or the through holes corresponding to the nodes are returned to the main process;

because a conductor may operate in different threads, if the created node is directly stored in the conductor, different threads may modify the condition of a conductor at the same time, and in order to avoid the condition, after all sub-threads are finished, the node is written into the conductor, see step three;

step three, after the thread pool is empty, all threads finish running, all nodes are stored in the conductors, each conductor is a class object, a list variable is stored in the members of the class to store all the nodes of the conductor, and repeated nodes are deleted;

step four, firstly, generating a task for each unit, each conductor layer and each via hole layer, and putting the task into a thread pool; then, starting a thread to calculate the resistance according to the configured thread number;

and step five, outputting the calculated resistance between the nodes after all the threads finish running.

As a further improvement, in step two, first, each conductor in the current cell is checked, if the conductor has contact with other conductors in the current cell, a node is created, and the coordinates of the node are the midpoint position of the contact;

then, each conductor in the current cell is examined and if the conductor has contact with a via in the current cell, a node is created whose coordinates are the midpoint of the overlap of the conductor and the via.

As a further improvement, in step four, for each thread, first, one task is taken out from the thread pool; then, traversing all conductors or via holes of the layer of the unit, and calculating the resistance between every two connected nodes according to the positions of the nodes and the resistivity RHO, the unit square resistivity RPSQ or the unit via hole resistivity RPV provided by a factory;

the conductor resistance between each two connected nodes is given by the formula: r = RHO L/W/T, R = RPSQ L/W; wherein, L: distance between nodes, W: the width of the conductor between the nodes and the thickness of the T conductor;

the formula of the resistance of the via hole between every two connected nodes is as follows: r = RPV/a; wherein, A: area of via hole

As a further improvement, in step one, a storage method is performed;

firstly, the whole circuit is cut into a plurality of units, and all conductors are stored in the corresponding units according to coordinates (x, y); if the conductors cross the boundary, appearing in different other cells, a pointer to a conductor is maintained in each cell.

As a further improvement, in the first, second and fourth steps, firstly, based on the storage method of the first step, each conductor layer in each cell is run by one thread, each thread operates all conductors on one conductor layer in one cell, the thread = cell × number of conductor layers, and a node is created at the contact point of each conductor and other conductors in the current cell by traversing all conductors; then, searching a contact point with a via hole in the same unit; after all the nodes are established, each conductor calculates the resistance according to the positions and the resistivity of the nodes; generating a resistance network; the resistor network connects the pins P1, P2 and P3 through nodes and resistors;

when the same conductor creates nodes in different units or different threads, the nodes created by each thread are stored, and after all threads are finished, the nodes are respectively stored in the conductor.

The invention provides a more flexible multithreading method, which can greatly improve the running speed. Nor do they pose any accuracy problems. For the difficulty of the prior art, another solution is provided: when each two conductors are examined, they are seen whether they are also stored in other units. If another unit also holds them, it does it only inside one of them. Therefore, the situation of repeatedly creating nodes is avoided, and the repeated nodes are not required to be deleted in the main process. But additional time is spent because each two conductors are checked for being stored in other cells.

When a program is started, a main process is provided, then a plurality of threads are started according to the setting of a user, and after each thread finishes a task, a result is transmitted to the main process through communication between a sub-thread and the main process, which is a conventional method of multi-thread communication.

Drawings

FIG. 1 is a schematic diagram of the process of using the present invention.

Fig. 2 is a schematic diagram of the prior art structure of the present invention.

Fig. 3 is a schematic diagram of a modified structure of the present invention.

Detailed Description

The invention adopts a new method to quickly find out the connection relation of the circuit and calculate the resistance. The method and the device can avoid the accuracy problem caused by splitting the conductor and can perform parallel calculation more finely.

S1, executing the storing method;

firstly, the whole circuit is cut into a plurality of units, and all conductors are stored in the corresponding units according to coordinates (x, y); then, if the boundary crossed by the conductor appears in different other units, a pointer of the conductor is stored in each unit;

such as the example of fig. 3: t1, V1 would be present inside cell (0, 0), T2 would be present inside two cells (0, 0) and (0, 1), and T9 would be present inside 4 cells (1, 1), (1, 2), (2, 1), (2, 2).

S2, executing a parallel algorithm;

first, based on the storage method of S1, each conductor layer in each cell is run with one thread, each thread operates all conductors on one conductor layer in one cell, and thread = cell × number of conductor layers; for example, in the example of FIG. 3, there may be a maximum of 27 threads in the interior, (9 cells, 3-level conductors), first, traversing all conductors and all connected vias; secondly, a node is created at the contact point of each conductor with other conductors in the current cell; thirdly, a contact point with the via hole is searched in the same unit, so that a conductor or the via hole which is contacted with the via hole is prevented from being searched globally, and the searching time can be saved; and finally, after all the nodes are established, each conductor calculates the resistance according to the positions of the nodes and the resistivity. This creates a resistor network connecting the pins P1, P2, P3 via nodes and resistors.

When the same conductor creates nodes in different units or different threads, the nodes created by each thread are stored and transmitted to a main process (shown in figure 1), and after all the threads are finished, the main process stores the nodes into the conductor respectively; when a duplicate node occurs, removing the duplicate node when the master process saves the node for each conductor;

the above algorithm has two difficulties: (1) the same conductor may create nodes in different units (and also in different threads), such as: the nodes of T9 and T8 are created in cell (1, 1) and the nodes of T9 and T10 are created in cell (0, 2), all of which need to be saved into T9. The upper and lower nodes of VIA are also created in different threads. If a node is created that writes conductors into each thread, this can lead to a situation where different threads modify a memory at the same time. The solution is as follows: storing the nodes created by each thread, and after all threads are finished, respectively storing the nodes into the conductors by the main process; (2) duplicate nodes may occur. Such as: the nodes of T5 and T6 are created at both cells (1, 1) and (2, 1). The solution is as follows: finally, duplicate nodes are removed as the master process saves nodes for each conductor. Since such a situation rarely occurs in the circuit, the influence on the operation time is very small.

According to the above description, the present invention requires the following steps:

reading layout information, and storing all conductors in corresponding units by a main process according to coordinates of conductors and/or via holes and layers to which the conductors and/or via holes belong;

firstly, establishing a task adding thread pool for each conductor layer of each unit by a main process; then, starting threads according to the configured thread number, and performing the following operations on each thread:

step two, taking out a task from the thread pool;

step two, traversing all conductors in the task;

in the second step, firstly, checking each other conductor in the current unit, if the conductor is contacted with other conductors in the current unit, creating a node, wherein the coordinates of the node are the midpoint position of the contact place;

then, each conductor in the current unit is checked, if the conductor is in contact with the via hole in the current unit, a node is created, and the coordinate of the node is the middle point of the overlapped part of the conductor and the via hole;

step two, the created nodes and the conductors or the through holes corresponding to the nodes are returned to the main process;

step three, all threads run to the end, the main process stores all nodes in the conductor, and the repeated nodes are deleted;

step four, firstly, the main process generates a task for each unit, each conductor layer and each via hole layer again and puts the task into a thread pool; then, starting a thread according to the configured thread number;

in step four, for each thread, firstly, taking out a task from the thread pool; then, traversing all conductors or via holes of the layer of the unit, and calculating the resistance between every two connected nodes according to the positions of the nodes and the resistivity RHO, the unit square resistivity RPSQ or the unit via hole resistivity RPV provided by a factory;

the conductor resistance between each two connected nodes is given by the formula: r = RHO L/W/T, R = RPSQ L/W; wherein, L: distance between nodes, W: the width of the conductor between the nodes and the thickness of the T conductor;

the formula of the resistance of the via hole between every two connected nodes is as follows: r = RPV/a; wherein, A: and step five, outputting the calculated resistance between the nodes by the main process after all the threads are operated.

The present invention has been described in sufficient detail for clarity of disclosure and is not exhaustive of the prior art.

Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; it is obvious as a person skilled in the art to combine several aspects of the invention. And such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention. The technical contents not described in detail in the present invention are all known techniques.

Claims (5)

1. An integrated circuit resistance extraction method based on a parallel algorithm is characterized in that: comprises the following steps;

reading layout information, and storing all conductors in corresponding units according to the coordinates of the conductors or the via holes and the layers to which the conductors or the via holes belong;

firstly, establishing a thread pool, and establishing a task adding thread pool for each conductor layer of each unit; then, starting threads according to the thread number configured by the user, and performing the following operations on each thread:

step two, taking out a task from the thread pool;

traversing all conductors in the task, and creating nodes at the positions contacted with other conductors or via holes;

step two, the created nodes and the conductors or the through holes corresponding to the nodes are returned to the main process;

step three, all threads run to the end, all nodes are stored in the conductor, and repeated nodes are deleted;

step four, firstly, generating a task for each unit, each conductor layer and each via hole layer, and putting the task into a thread pool; then, starting a thread to calculate the resistance according to the configured thread number;

and step five, outputting the calculated resistance between the nodes after all the threads finish running.

2. The integrated circuit resistance decimation method based on a parallel algorithm as claimed in claim 1, characterized in that: in the second step, firstly, checking each conductor in the current unit, if the conductor is contacted with other conductors in the current unit, creating a node, wherein the coordinate of the node is the midpoint position of the contact place;

then, each conductor in the current cell is examined and if the conductor has contact with a via in the current cell, a node is created whose coordinates are the midpoint of the overlap of the conductor and the via.

3. The integrated circuit resistance extraction method based on parallel algorithm of claim 1, characterized in that: in the fourth step, aiming at each thread, firstly, taking out a task from the thread pool; then, traversing all conductors or via holes of the layer of the unit, and calculating the resistance between every two connected nodes according to the positions of the nodes and the resistivity RHO, the unit square resistivity RPSQ or the unit via hole resistivity provided by a factory;

the conductor resistance between each two connected nodes is given by the formula: r = RHO L/W/T or R = RPSQ L/W; wherein, L: distance between nodes, W: the width of the conductor between the nodes and the thickness of the T conductor;

the formula of the via hole resistance between every two connected nodes is as follows: r = RPV/a; wherein, A: area of the via.

4. The integrated circuit resistance decimation method based on a parallel algorithm as claimed in claim 1, characterized in that: in step one, executing a storage method;

firstly, the whole circuit is cut into a plurality of units, and all conductors are stored in the corresponding units according to coordinates (x, y); if the boundary crossed by the conductor appears in different other cells, a pointer to the conductor is maintained in each cell.

5. The integrated circuit resistance decimation method based on a parallel algorithm as claimed in claim 4, characterized in that: in the first, second and fourth steps, firstly, based on the storage method of the first step, each conductor layer in each cell is operated by one thread, each thread operates all conductors on one conductor layer in one cell, the thread = the cell × the number of conductor layers, and a node is created at the contact point of each conductor and other conductors in the current cell by traversing all conductors; then, searching a contact point with a via hole in the same unit; after all the nodes are established, each conductor calculates the resistance according to the positions and the resistivity of the nodes; generating a resistance network; the resistor network connects the pins P1, P2 and P3 through nodes and resistors;

when the same conductor creates nodes in different units or different threads, the nodes created by each thread are stored, and after all threads are finished, the nodes are respectively stored in the conductor.

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