Disclosure of Invention
Aiming at the technical problem of single triggering mode in the background technology, the invention provides a double-level triggering locking circuit supporting setting and resetting, which can lock a triggering signal and unlock the triggering circuit.
The invention discloses a double-level trigger locking circuit supporting setting and resetting, which comprises:
the first resistor, the second resistor, the third resistor, the fourth resistor and the fifth resistor are arranged on the first triode, the second triode and the third triode;
the power supply circuit comprises a SET/reset control signal SET/RST, a Low-level trigger control signal Low-IO, a High-level trigger control signal High-IO and a circuit power supply VCC-GND, wherein the VCC-GND power supply is used for supplying power to the whole circuit, the SET/reset control signal SET/RST is used for setting and resetting the whole circuit, SET/RST=VCC is High during setting, and SET/RST=GND is Low during resetting;
The base electrode of the first transistor is connected with the first resistor, the emitter electrode of the first transistor is respectively connected with the SET/reset control signal SET/RST and the fifth resistor, the collector electrode of the first transistor is respectively connected with the High-level trigger control signal High-IO and the third resistor, and the first transistor is pulled down to a power supply GND by being connected with the fourth resistor;
the base electrode of the second transistor is connected with the third resistor, the emitter electrode of the second transistor is connected with the collector electrode of the third transistor, and the collector electrode of the second transistor is connected with the Low-level trigger control signal Low-IO and the first resistor respectively and is pulled up to the power supply VCC by being connected with the second resistor;
the base electrode of the third triode is connected with the fifth resistor, the emitter electrode of the third triode is connected with the power supply GND, and the collector electrode c of the third triode is connected with the emitter electrode of the second triode;
The Low-level trigger control signal Low-IO is pulled up to the power supply VCC through the second resistor and is used for detecting an input pull-up signal or used as an output signal;
The High-level trigger control signal High-IO is pulled down to the power supply GND through the fourth resistor, and is used for detecting an input pull-up signal or as an output signal.
Alternatively to this, the method may comprise,
When the SET/reset control signal SET/RST is SET, SET/rst=vcc, and SET/RST pulls the base of the third triode high through the fifth resistor, the emitter of the third triode is connected with the power supply GND, the third triode is turned on, and the collector of the third triode is connected to the power supply GND;
When the High-IO trigger control signal is used for input detection, when the High-IO trigger control signal detects Low-level input, the base electrode of the second triode is pulled down through the third resistor, the emitter of the second triode is communicated with GND, the second triode is in a closed state, and the Low-level trigger control signal Low-IO is pulled up to VCC through the second resistor, namely a default High-level state.
Alternatively to this, the method may comprise,
When High-IO detects High-level input, the base electrode of the second triode is pulled up through the third resistor, the emitter electrode of the second triode is communicated with GND, the second triode is conducted, the collector electrode of the second triode is communicated with GND, the Low-level trigger control signal Low-IO is communicated with GND, and the base electrode of the first triode is pulled down through the first resistor;
the emitting electrode of the first triode is VCC high level, and the first triode is conducted;
And the collector electrode of the first triode is communicated with VCC High level, the High-IO is communicated with VCC, and when the High-IO is pulled up or pulled down, the High-IO is locked to be High level, and the Low-IO is locked to be Low level.
Alternatively to this, the method may comprise,
When the Low-IO trigger control signal is used for input detection, when the Low-IO trigger control signal detects High-level input, the base electrode of the first triode is pulled up through the first resistor, the emitter of the first triode is communicated with VCC, the first triode is in a closed state, and the High-IO trigger control signal is pulled down to GND through the fourth resistor, namely a default Low-level state.
Alternatively to this, the method may comprise,
When Low-IO detects Low-level input, the base electrode of the first triode is pulled down through the first resistor, the emitter electrode of the first triode is of VCC High level, the first triode is conducted, the collector electrode of the first triode is of VCC High level, the High-level trigger control signal High-IO is of VCC High level, the base electrode of the second triode is pulled up through the third resistor, the emitter electrode of the second triode is communicated with the power supply GND, and the second triode is conducted;
The collector of the second triode is connected to the power supply GND, the Low-IO is connected with the power supply GND, and when the Low-IO is pulled up or pulled down, the Low-IO is locked to be at a Low level, and the High-IO is locked to be at a High level.
Alternatively to this, the method may comprise,
When the SET/reset control signal SET/RST is reset, SET/rst=gnd low level, the emitter of the first transistor is connected to SET/RST and simultaneously connected to GND, and at this time, the first transistor is always turned off.
Alternatively to this, the method may comprise,
The SET/RST pulls down the base electrode of the third triode through the fifth resistor, the emitter electrode of the third triode is connected with the power supply GND, the third triode is turned off, the emitter electrode of the second triode is not communicated with the GND any more, the second triode is always turned off at the moment, the Low-level trigger control signal Low-IO cannot be locked, and the Low-level trigger control signal High-IO cannot be locked.
Compared with the prior art, the application has the following beneficial effects:
(1) The invention uses the triode to realize the double-level triggering locking and unlocking of the circuit;
(2) The invention supports setting and resetting operations for the trigger circuit;
(3) The detection IO can be used as signal detection input and control signal output;
(4) The invention supports the output complementary level and increases the flexibility of circuit application.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The words "a", "an", and "the" as used herein are also intended to include the meaning of "a plurality", etc., unless the context clearly indicates otherwise. Furthermore, the terms "comprises," "comprising," and the like, as used herein, specify the presence of stated features, steps, operations, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, or components.
All terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art unless otherwise defined. It should be noted that the terms used herein should be construed to have meanings consistent with the context of the present specification and should not be construed in an idealized or overly formal manner.
Referring now to fig. 1, the present invention provides a dual-level trigger lock circuit supporting set and reset, comprising: five resistors R1, R2, R3, R4 and R5, a PNP transistor Q1, two NPN transistors Q2 and Q3, a SET/reset control signal SET/RST, a Low-level trigger control signal Low-IO, a High-level trigger control signal High-IO, and a circuit power supply VCC-GND, wherein:
The VCC-GND power supply is used for supplying power to the whole circuit;
The SET/reset control signal SET/RST is used for setting and resetting the whole circuit, and the SET/rst=vcc high level during setting; SET/rst=gnd low level at reset;
The Low level trigger control signal Low-IO is pulled up to the power supply VCC by default through the resistor R2, and can be used for detecting an input pull-up signal and a pull-down signal and can be used as an output signal;
The High level trigger control signal High-IO is pulled down to the power supply GND by default through the resistor R4, and can be used for detecting an input pull-up signal and a pull-down signal and can be used as an output signal;
The Q1 is a PNP transistor, the base b of the PNP transistor is connected with the resistor R1, the emitter e of the PNP transistor is connected with the SET/reset control signal SET/RST and the resistor R5, the base collector c of the PNP transistor is connected with the High-level trigger control signal High-IO and the resistor R3, and the PNP transistor is pulled down to the power supply GND by being connected with the resistor R4;
The Q3 is an NPN transistor, the base b of the transistor is connected with the resistor R5, the emitter e of the transistor is connected with the power supply GND, and the collector c of the transistor is connected with the emitter e of the transistor Q2;
when the SET/reset control signal SET/RST is SET (SET/rst=vcc), SET/RST pulls the base b of the transistor Q3 high through the resistor R5, the transistor Q3 is turned on because the emitter e of the transistor Q3 is connected to the power supply GND, the collector c of the transistor Q3 is also connected to the power supply GND, and the emitter e of the transistor Q2 is also connected to the power supply GND; in addition, the emitter e of the triode Q1 is connected with SET/RST and also connected with VCC;
When the High-IO signal is used for input detection, when the High-IO signal detects Low-level input, the base b of the triode Q2 is pulled down through the resistor R3, the triode Q2 is in a closed state because the emitter e of the triode Q2 is communicated with GND, and the Low-level trigger control signal Low-IO is pulled up to VCC through the resistor R2, namely a default High-level state;
When High-IO detects High-level input, the base b of the triode Q2 is pulled High through the resistor R3, the triode Q2 is conducted because the emitter e of the triode Q2 is communicated with GND, the collector c of the triode Q2 is also communicated with GND, the Low-level trigger control signal Low-IO is also communicated with GND, the base b of the triode Q1 is pulled Low through the resistor R1, the triode Q1 is conducted because the emitter e of the triode Q1 is VCC High, the collector c of the triode Q1 is also communicated with VCC High, at this time, the High-IO is also directly communicated with VCC, no matter whether the High-IO is pulled up or pulled down, the High-IO is locked to be High, and the Low-IO is locked to be Low;
When the Low-level trigger control signal Low-IO is used for input detection, when the Low-IO detects High-level input, the Low-level trigger control signal Low-IO pulls the base b of the triode Q1 High through the resistor R1, and because the emitter e of the triode Q1 is also in a High-level VCC, the triode Q1 is in a closed state, and the High-level trigger control signal High-IO is pulled down to GND through the resistor R4, namely a default Low-level state;
When Low-IO detects Low-level input, it pulls down the base b of the triode Q1 through the resistor R1, because the emitter e of the Q1 is VCC High level, the triode Q1 is turned on, the collector c of the triode Q1 also becomes VCC High level, the High-level trigger control signal High-IO also becomes VCC High level, and pulls up the base b of the triode Q2 through the resistor R3, because the emitter e of the triode Q2 is connected to the power supply GND, the triode Q2 is turned on, the collector c of the triode Q2 is also connected to the power supply GND, and at this time, low-IO is also directly connected to the power supply GND, regardless of pulling up or pulling down the Low-IO, the Low-IO is locked to Low level, and the High-IO is locked to High level; because of the locked low level and the locked high level, the circuit can be flexibly applied to an actual circuit.
When the unlocking circuit is needed, the SET/reset control signal SET/RST is reset, the SET/RST=GND is Low, the emitter e of the triode Q1 is connected with the SET/RST and also connected with GND, so the triode Q1 can not be opened through the resistor R1 no matter how the Low-IO level changes, the triode Q1 is connected with the GND
The base b of the Q2 is connected with the resistor R3, the emitter e of the Q2 is connected with the collector c of the triode Q3, the collector c of the Q2 is connected with the Low-level trigger control signal Low-IO and the resistor R1, and the Q2 is pulled up to the power supply VCC through being connected with the resistor R2 and is always turned off; the SET/RST pulls down the base b of the triode Q3 through the resistor R5, the triode Q3 is turned off because the emitter e of the triode Q3 is connected with the power supply GND, the emitter e of the triode Q2 is not communicated with the GND any more, the triode Q2 cannot be turned on through the resistor R3 no matter the High-IO level changes, and the triode Q2 is always turned off; under the condition that the levels of the Low-IO and the High-IO cannot be locked, the unlocking function of the circuit is realized.
It can be seen that both Low-IO and High-IO can be used for input signal detection and output signals, and meanwhile, the circuits can be locked and unlocked through the SET/RST, so that the flexibility of the circuit use is greatly improved.
It should be noted that, in the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described as different from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
In the context of the present application, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium.
The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and pointing device (e.g., a mouse or trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.
The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), and the internet.
The computer system may include a client and a server. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other.
Artificial intelligence is the discipline of studying computers to simulate certain mental processes and intelligent behaviors (e.g., learning, reasoning, thinking, planning, etc.) of humans, both hardware-level and software-level techniques. Artificial intelligence hardware technologies generally include technologies such as sensors, dedicated artificial intelligence chips, cloud computing, distributed storage, big data processing, and the like; the artificial intelligence software technology mainly comprises a computer vision technology, a voice recognition technology, a natural voice processing technology, a machine learning/deep learning technology, a big data processing technology, a knowledge graph technology and the like.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present application may be performed in parallel, sequentially, or in a different order, provided that the desired results of the disclosed embodiments are achieved, and are not limited herein.
The above embodiments do not limit the scope of the present application. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the scope of the present application.