Disclosure of Invention
First, the technical problem to be solved
The invention aims to solve the technical problem of providing a reliable transmission method which is easy to realize on an FPGA, consumes less resources, has high transmission efficiency, can quickly position the problem when communication is abnormal and can also quickly recover normal communication.
(II) technical scheme
In order to solve the technical problems, the invention provides a method for realizing the reliable transmission of an Ethernet message based on an FPGA, which comprises the following steps:
A method for realizing reliable transmission of an Ethernet message based on an FPGA is characterized by redefining a message frame format of reliable transmission and comprises a reliable header field, wherein the reliable header field comprises a packet sequence number, the method comprises the following steps of S1 initializing a step that an Ethernet terminal 1 sends a handshake packet to an FPGA end, the handshake packet carries the packet sequence number of the message to be sent by the Ethernet terminal 1, the FPGA receives the handshake packet and then sends the handshake packet to the Ethernet terminal 1, the handshake packet carries the packet sequence number of the message to be sent by the FPGA side, S2 data communication step that the Ethernet terminal 1 sends the message to a receiving module of a reliable module 1 of the FPGA, the receiving module of the reliable module 1 of the FPGA analyzes the reliable header field of the message and sends the message to a sending module of a reliable module 2 of the FPGA, the sending module of the reliable module 2 of the FPGA sends the message to the Ethernet terminal 2 and waits for the Ethernet terminal 2 to reply a corresponding response packet, and S3 ends the communication step that the sending of the handshake packet is finished and the communication link of any data packet is not overtime is not reached.
Further, the reliable header field further comprises a message type, a packet response number, a receiving state and a sending state.
Further, the receiving module of the reliable module 1 of the FPGA parses the reliable header field of the message, including:
Judging whether the packet is a data packet, if the packet is the data packet, judging whether the packet sequence number of the packet is an expected packet sequence number, if the packet is the expected packet sequence number, caching the packet and waiting to be taken away, and if n normal data packets are continuously received, informing a local side transmitting module to transmit a normal response packet to the Ethernet terminal 1, wherein the packet response number of the response packet is the packet sequence number +1 of the n normal data packet.
Further, if the packet sequence number of the packet is smaller than the expected packet sequence number, the packet is considered as a retransmitted data packet, the FPGA side discards the packet and simultaneously informs the local side transmitting module to immediately transmit a normal response packet to the Ethernet terminal 1, if the packet sequence number of the packet is larger than the expected packet sequence number and the difference between the received packet sequence number and the expected packet sequence number is smaller than a window value, the data packet is considered to be lost, all the data packets larger than the expected packet sequence number are discarded, and the local side transmitting module is informed to immediately transmit a retransmitted response packet to the Ethernet terminal 1, and if the packet sequence number of the packet is larger than the expected packet sequence number and the difference between the received packet sequence number and the expected packet sequence number is not smaller than the window value, the local side transmitting module is considered to be out of step, and the local side transmitting module is informed to immediately transmit the response packet containing the out-of-step information to the Ethernet terminal 1.
Further, after receiving the response packet containing the step-out state sent by the FPGA side, the ethernet terminal 1 sends a handshake packet to the FPGA side, and when the FPGA side receives the handshake packet, the ethernet terminal returns a handshake packet to reestablish communication.
Further, the sending module of the reliable module 2 sends the data packet to the ethernet terminal 2 by adopting a sliding window, starts a timer to wait for the ethernet terminal 2 to reply to the corresponding response packet, if the timer is overtime, the receiving module of the reliable module 2 does not receive the expected response packet yet, the sending module of the reliable module 2 retransmits the corresponding data packet, if the timer is not overtime, the receiving module of the reliable module 2 receives the expected response packet and updates the sliding window, and if the receiving module of the reliable module 2 receives the retransmission response packet, the sending module of the reliable module 2 is informed to retransmit the corresponding data packet.
Further, the S2 data communication stage can also perform bidirectional communication, wherein the Ethernet terminal 1 sends the message 1 to a receiving module of the reliable module 1 of the FPGA, the Ethernet terminal 2 sends the message 2 to a receiving module of the reliable module 2 of the FPGA, the receiving module of the reliable module 1 of the FPGA analyzes a reliable header field of the message 1 sent by the Ethernet terminal 1 and sends the message 1 to a sending module of the reliable module 2 of the FPGA, the receiving module of the reliable module 2 of the FPGA analyzes a reliable header field of the message 2 sent by the Ethernet terminal 2 and sends the message 2 to a sending module of the reliable module 1 of the FPGA, the sending module of the reliable module 2 of the FPGA sends the message 1 to the Ethernet terminal 2, the receiving module of the reliable module 2 of the FPGA waits for the Ethernet terminal 2 to reply a corresponding response packet 1, and the sending module of the reliable module 1 of the FPGA sends the message 2 to the Ethernet terminal 1, and waits for the receiving module 1 of the reliable module 1 of the FPGA to reply the corresponding Ethernet packet.
(III) beneficial effects
The invention improves the performance of reliable transmission, consumes less logic resources and reduces the complexity. When the network is abnormal and out of step, the received data packet is not lost, and the retransmission rate of the network is greatly reduced. When the network is abnormal, the terminal can quickly locate the problems by analyzing the reliable header field of the message, so that the terminal can quickly recover to the normal network.
Detailed Description
To make the objects, contents and advantages of the present invention more apparent, the following detailed description of the present invention will be given with reference to the accompanying drawings and examples.
Fig. 1 is an overall frame diagram of the present invention. As shown in fig. 1, there is full duplex communication between an ethernet terminal 1 and an ethernet terminal 2. Wherein the solid line represents the processing procedure of the application data message from the ethernet terminal 1 to the ethernet terminal 2 through the FPGA, and the dotted line represents the processing procedure of the application data message from the ethernet terminal 2 to the ethernet terminal 1 through the FPGA. Reliable transmission is required between the Ethernet terminal 1 and the FPGA and between the Ethernet terminal 2 and the FPGA to ensure that messages transmitted between the Ethernet terminals are not lost, repeated and controllable in flow.
In order to achieve reliable transmission between the ethernet terminal and the FPGA, the message frame format of the transmission is redefined, see fig. 2. The definition of the reliable header field is as follows:
the message types are defined as four message types, namely a handshake packet, a data packet, a response packet and a data plus response packet.
The handshake packet is used for initializing packet sequence numbers of the Ethernet terminal and the FPGA and is used for updating the packet sequence numbers of the Ethernet terminal and the FPGA again after the communication between the Ethernet terminal and the FPGA is out of step. The packet sequence number field is of interest when the message type is handshake packet.
A data packet refers to a packet containing only application data, including retransmitted data packets. When the message type is a data packet, only the packet sequence number and the sending state need to be concerned.
The first reply packet is a reply packet which is returned to the sender to indicate that the sender receives the confirmation packet of the packet when the normal packet containing the application data is received, and the second reply packet is returned to the sender to indicate that the sender needs to retransmit when the packet containing the application data is received and the packet is lost. When the message type is a response packet, attention is paid to the packet response number and the receiving state.
The data+response packet is a packet in which the data packet carries information to be responded. When the message type is data+response packet, attention is paid to packet sequence number, packet response number, receiving state and transmitting state.
Packet sequence number: the number of the data packet (including data + acknowledgement packet) or handshake packet. The ethernet terminal and the FPGA each maintain their own packet sequence numbers. If the packet is a normal data packet (including data and response packet), the packet sequence number is accumulated by 1, if the packet is a retransmitted data packet (including data and response packet), the packet sequence number is the response number of the retransmitted response packet (including data and response packet), if the packet is a handshake packet, the field Ethernet terminal starts from any value, the FPGA starts from 0, and when the FPGA is out of step, the field in the handshake packet indicates the packet sequence number of the next data packet (including data and response packet) expected to be received.
Packet acknowledgement number: the number of the acknowledgement packet (including data + acknowledgement packet) indicates the packet sequence number for which the next data packet (including data + acknowledgement packet) is expected to be received. When the Ethernet terminal receives a normal data packet (including data and response packet), the field is the packet sequence number of the data packet (including data and response packet) plus 1; when the FPGA continuously receives n (n value can be obtained through register configuration, 1< = n < window value) normal data packets (including data+response packet), this field is the packet sequence number of the nth data packet (including data+response packet) plus 1. When a packet is received that is missing (including data + acknowledgement), this field is the packet sequence number of the first packet that is missing (including data + acknowledgement).
The receiving state is a state of receiving data packets (including data and response packets) and comprises whether the packets are lost, whether the buffer memory is full or not and whether the message type is normal or not. This state is updated in the response packet (containing data + response packet). Under normal conditions, the state is normal, the buffer is not full, and the message type is normal. If the packet is lost, the packet is normally updated to a packet loss state, if the buffer is full, the buffer is not fully updated to a buffer full state, and if the message type is abnormal, the message type is normally updated to be abnormal.
The sending state is a state indicating that the sender sends currently and comprises whether the sender is a retransmission data packet (comprising data and response packet), whether a window is full or not, and whether the sender is out of step or not. Under normal conditions, the state is normal, the window is not full, and no step out occurs. If the transmitted data packet (including data and response packet) waits for the corresponding response packet to be overtime or the retransmission response packet is received to retransmit the data packet (including data and response packet), the method will update the data packet normally for retransmission, if no redundant window can transmit the data packet (including data and response packet), the window is not fully updated to be full, and if the packet response number of the received response packet (including data and response packet) exceeds the maximum value of the window, the method will update the non-step-out to be step-out.
And the reliable transmission between the Ethernet terminal and the FPGA is realized, and three stages s1, s2 and s3 are totally realized.
S1. initialization phase.
Firstly, the Ethernet terminal 1 sends a handshake packet to the FPGA, the handshake packet carries a packet sequence number of a message to be sent by the Ethernet terminal 1, the FPGA initializes an expected received packet sequence number maintained by a receiving module after receiving the handshake packet, then the handshake packet carries a packet sequence number of the message to be sent by the FPGA side, and the Ethernet terminal 1 initializes the expected received packet sequence number maintained after receiving the handshake packet.
The packet serial numbers of the Ethernet terminal and the FPGA side are initialized through a one-to-one handshake package, and then communication is started, so that the communication establishment flow is simplified.
And S2, data communication stage.
The communication is classified into one-way communication and two-way communication. The unidirectional communication is that the ethernet terminal 1 sends a data packet to the ethernet terminal 2 through the FPGA, or that the ethernet terminal 2 sends a data packet to the ethernet terminal 1 through the FPGA, that is, only the solid line flow or the dotted line flow of fig. 1 is provided, at this time, the receiving party does not send a data packet when replying a response packet to the sending party, so that the data+response packet does not occur. Two-way communication is the simultaneous processing of the solid line flow and the dashed line flow of fig. 1. The ethernet terminal 1 and the ethernet terminal 2 simultaneously transmit data packets to the opposite terminal through the FPGA, and at this time, the receiving party replies the response packet to the transmitting party and simultaneously has data packets to transmit, so that data+response packets may occur.
Fig. 3 is a block diagram of an implementation of unidirectional communication of a packet, for example, the ethernet terminal 1 sends a data packet to the ethernet terminal 2.
S11, the Ethernet terminal 1 sends a message to a receiving module of the reliable module 1 of the FPGA;
S12, analyzing the reliable head of the message by the receiving module of the reliable module 1 of the FPGA, informing the sending module of the local side to send a corresponding response packet to the Ethernet terminal 1, and sending the message to the sending module of the reliable module 2 of the FPGA by the receiving module of the reliable module 1 of the FPGA;
s13, the reliable module 2 of the FPGA sends the message to the Ethernet terminal 2 through the sending module, and meanwhile the receiving module at the local side waits for the Ethernet terminal 2 to reply a corresponding response packet.
The FPGA side specifically realizes the following steps that a receiving module of the reliable module 1 analyzes a reliable header field in a received message frame format. Judging whether the packet is a data packet, if the packet is the data packet, judging whether the packet sequence number of the packet is an expected packet sequence number, if the packet is the expected packet sequence number, on the one hand, caching the packet and waiting to be taken away, and on the other hand, if n normal data packets are continuously received, informing a sending module at the local side to send a normal response packet to the Ethernet terminal 1, wherein the packet response number of the response packet is the packet sequence number +1 of the nth normal data packet;
If the packet sequence number of the packet is smaller than the expected packet sequence number, the packet is considered as a retransmitted data packet, and in order to avoid the Ethernet terminal to always retransmit the data packet, the FPGA side discards the packet and simultaneously informs the local side transmitting module to immediately transmit a normal response packet to the Ethernet terminal 1;
if the packet sequence number of the packet is greater than the expected packet sequence number and the difference between the received packet sequence number and the expected packet sequence number is smaller than the window value, the packet is considered to be lost, all the packets greater than the expected packet sequence number are discarded, and the local side transmitting module is informed to immediately transmit a retransmission response packet to the Ethernet terminal 1;
If the packet sequence number of the packet is larger than the expected packet sequence number and the difference between the received packet sequence number and the expected packet sequence number is not smaller than the window value, the step is considered to be out of step, and the sending module at the local side is informed to immediately send a response packet containing step-out information to the Ethernet terminal 1. After receiving the response packet containing the step-out state sent by the FPGA side, the Ethernet terminal sends a handshake packet to the FPGA side, and when the FPGA side receives the handshake packet, the Ethernet terminal returns a handshake packet to indicate that communication is reestablished, and updates the packet response number of the response packet expected to be received by the local side receiving module. The handshake packet only changes the packet sequence number of the desired data packet or the packet response number of the desired response packet, and the data packet that has been buffered normally is not lost.
If the data packet is not the data packet and is the handshake packet, the packet sequence number of the data packet expected to be received is updated, and the sending module at the local side is informed to send the handshake packet. And if the message is other, discarding the message.
If the data packet is the data packet, the reliable header information of the data packet is cut, after the cut data packet reaches the transmitting module of the reliable module 2, the transmitting module of the reliable module 2 adds the reliable header information to the data packet containing the application data according to the serial number of the data packet at the local side, and then the data packet is transmitted to the Ethernet terminal 2, and the data packet is transmitted by adopting the sliding window, and if the sliding window is not full and the data packet to be transmitted still exists, the data packet is continuously transmitted to the Ethernet terminal 2. If the sliding window is full and there is still a data packet to be transmitted, the data packet is not continuously transmitted to the ethernet terminal 2 until the sliding window is not full. The sending module of the reliable module 2 starts a timer to wait for a response packet sent by the Ethernet terminal 2, if the timer is overtime, the receiving module of the reliable module 2 does not receive the expected response packet yet, the sending module of the reliable module 2 retransmits the corresponding data packet, if the timer is not overtime, the receiving module of the reliable module 2 updates the sliding window if the expected response packet is received, if the receiving module of the reliable module 2 retransmits the response packet, the sending module of the reliable module 2 is informed to retransmit the corresponding data packet, the processing process of retransmitting the data packet is seen in fig. 4, and if the packet response number of the received response packet exceeds the sum of the expected packet response number and the window value, the sending module of the reliable module 2 is considered to be out of step, and the sending module of the reliable module is informed to send the response packet containing the out-of-step information.
Fig. 5 is a block diagram of an implementation of two-way communication of messages. The ethernet terminal 2 may also transmit a data packet to the ethernet terminal 1, for example, while the bi-directional communication ethernet terminal 1 transmits a data packet to the ethernet terminal 2.
S21, the Ethernet terminal 1 sends the side data packet (containing data and response packet) to a receiving module of the reliable module 1 of the FPGA, and the Ethernet terminal 2 sends the side data packet (containing data and response packet) to a receiving module of the reliable module 2 of the FPGA;
S22, the receiving module of the reliable module 1 of the FPGA analyzes the reliable header field of the message sent by the Ethernet terminal 1, on one hand, the receiving module of the reliable module 1 of the FPGA sends a corresponding response packet to the Ethernet terminal 1, on the other hand, the receiving module of the reliable module 1 of the FPGA sends a data packet to the sending module of the reliable module 2 of the FPGA, the receiving module of the reliable module 2 of the FPGA analyzes the reliable header field sent by the Ethernet terminal 2, on the other hand, the receiving module of the reliable module 2 of the FPGA sends a corresponding response packet to the Ethernet terminal 2, on the other hand, the receiving module of the reliable module 2 of the FPGA sends the data packet to the sending module of the reliable module 1 of the FPGA.
S23, the reliable module 2 of the FPGA sends the data packet (including the data and the response packet) to the Ethernet terminal 2 through the sending module and the receiving module at the local side waits for the Ethernet terminal 2 to reply the corresponding response packet (including the data and the response packet), and the reliable module 1 of the FPGA sends the data packet (including the data and the response packet) to the Ethernet terminal 1 through the sending module and the receiving module at the local side waits for the Ethernet terminal 1 to reply the corresponding response packet (including the data and the response packet).
The Ethernet terminal 1 corresponds to the reliable module 1 of the FPGA, and the Ethernet terminal 2 corresponds to the reliable module 2 of the FPGA. The opposite side of the reliable module 1 is the reliable module 2, and the opposite side of the reliable module 2 is the reliable module 1.
The FPGA-side implementation process is shown in fig. 6, and the implementation process of the reliable module 1 and the reliable module 2 is the same. Take the example of a reliable module 1.
The receiving module of the reliable module 1 performs reliable header analysis judgment on the received message frame format, if the received message frame format is a data packet, judges whether the packet sequence number of the packet is an expected packet sequence number, if the received message frame format is a data packet, on the one hand, caches the packet to be taken away, and on the other hand, if the received message frame format is a data packet, informs the local side transmitting module of transmitting normal response packets to the corresponding Ethernet terminal, the packet response number of the response packet is the packet sequence number +1 of the n normal data packet, if the received message frame format is smaller than the expected packet sequence number, considers the retransmitted data packet as the retransmitted data packet, and if the received message frame format is smaller than the expected packet sequence number, the local side transmitting module is informed of immediately transmitting the normal response packets to the corresponding Ethernet terminal while discarding the received message frame sequence number is larger than the expected packet sequence number, if the received message frame sequence number is smaller than the window value, and informs the local side transmitting module of immediately transmitting the data packet loss packets to the corresponding Ethernet terminal. At this time, if there is a data packet sent from the opposite side to be sent to the corresponding ethernet terminal of the local side, the data packet carries the response packet information and is sent to the corresponding ethernet terminal, and if there is no data packet from the opposite side to be sent, the response packet is sent to the corresponding ethernet terminal.
If the response packet is the expected response packet, updating a sliding window of the sending module of the side; if the received response packet has a packet response number exceeding the sum of the expected packet response number and the window value, the step is considered to be out of sync, and the sending module of the local side is informed to send the response packet containing the step-out information. And if the packet is a data plus response packet, analyzing according to the data packet and the response packet.
If the handshake packet updates the packet sequence number of the data packet expected to be received, the sending module at the home side is informed to send the handshake packet. And if the message is other, discarding the message. If the receiving module does not receive any packet, and the data packet sent from the opposite side needs to be sent to the Ethernet terminal corresponding to the local side, only the normal data packet is sent, and no response information is carried.
The transmission rule of the data packet with the response information and the data packet without the response information in the bidirectional communication is the same as the transmission rule of the data packet without the response information in the unidirectional communication.
The FPGA side sliding window control flow mechanism is shown in fig. 7. The sliding window is used only when transmitting the data packet, and the sliding window value size is obtained by the ethernet terminal through the register configuration. The FPGA needs to maintain the leftmost, rightmost and currently sent pointers of the sliding window. The left-most part of the sliding window is the minimum packet sequence number a of the data packet which is already transmitted but not received with the corresponding response packet, and the right-most part is the maximum packet sequence number of the data packet which can be transmitted, denoted b, and b is equal to the value of the a+ sliding window. If the packet sequence number of the packet is noted d between a and b, indicating that the sliding window is not full, the packet may be sent out. If the packet sequence number of the data packet is b+1, the data packet is indicated that the sliding window is full, the data packet cannot be sent out temporarily, and the data packet cannot be sent out until the sliding window is not full. And if a is less than or equal to c-1 and less than or equal to b, considering that all data packet receivers from a to c-1 (containing c-1) have been received, updating the leftmost value of the sliding window to c and updating the rightmost value to the c+ sliding window value.
S3. ends the communication phase.
When the FPGA side transmits retransmission data packets due to timeout reaches a certain number m (configured by a register), and does not receive any packet, the link disconnection communication is considered to be ended.
The invention first simplifies the flow of establishing communication. And initializing packet serial numbers of the Ethernet terminal and the FPGA side through a one-to-one handshake package, and then starting communication. When the FPGA receiving side detects that the data packet is lost, all the data packets after the packet loss are discarded, so that the cache resources of the FPGA are saved, and meanwhile, the complexity of disordered processing due to the packet loss in the FPGA is reduced. In the data communication process, reliable transmission of the message is realized in the FPGA according to the packet serial number, the packet response number, the sending state and the receiving state of the packet, the method is simple and easy to realize, and on the other hand, the Ethernet terminal can also rapidly judge the capability of the FPGA for sending the data packet and analyze the state of the sending side of the FPGA. If the step is out, the communication between the two parties can be initialized again through the handshake packet on the premise that the received data packet at the FPGA side is not lost, and the communication efficiency is improved while the normal communication is recovered from the abnormality. When the FPGA receives the data packet with the sequence number smaller than the expected packet, the FPGA discards the packet and immediately replies a response packet to the corresponding Ethernet terminal, so that the Ethernet terminal is prevented from retransmitting all the time, and the communication congestion is reduced. In addition, the FPGA side receives the normal data packet, adopts a mode of multi-inclusion and reply of the response packet, and greatly improves the transmission efficiency. The use of sliding windows to control traffic through ethernet terminals and FPGAs is more efficient than other mechanisms such as interrupt modes. When the communication is finished, the FPGA side sends retransmission data packets to a certain number, and does not receive any packet, and the communication of the two parties is considered to be finished, so that the use of heartbeat packets is reduced, and the processing complexity is reduced.
Compared with the reliable transmission of TCP protocol, the invention improves the performance of the reliable transmission, consumes less logic resources and reduces the complexity. When the network is abnormal and out of step, the received data packet is not lost, and the retransmission rate of the network is greatly reduced. When the network is abnormal, the terminal can quickly locate the problems by analyzing the reliable header field of the message, so that the terminal can quickly recover to the normal network.
The foregoing is merely a preferred embodiment of the present invention, and it should be noted that modifications and variations could be made by those skilled in the art without departing from the technical principles of the present invention, and such modifications and variations should also be regarded as being within the scope of the invention. Specific embodiments of the invention are described in further detail.