Disclosure of Invention
In order to solve the technical problems or at least partially solve the technical problems, the application provides a page fault processing method, a page fault processing device, a page fault processing system, electronic equipment and a storage medium.
According to an aspect of the embodiment of the present application, there is provided a page fault processing method applied to an FPGA chip, the method including:
receiving a page fault handling request from a central processing unit, wherein the page fault handling request is triggered by the central processing unit when determining that a page fault exists in a page table entry;
analyzing the page fault processing request to obtain page fault processing information carried by the page fault processing request;
Executing data writing operation or data reading operation in a target storage object based on the page fault processing information to obtain a processing result, wherein the target storage object is deployed on the FPGA chip;
and feeding back the processing result to the central processing unit so that the central processing unit updates the page table entry according to the processing result.
Further, the analyzing the page fault processing request to obtain page fault processing information carried by the page fault processing request includes:
calling a computer quick link protocol to analyze the page fault processing request to obtain original page fault processing information;
Extracting a target identifier from the original page fault processing information and associated data of the target identifier, and determining the target identifier and the associated data as the page fault processing information, wherein the target identifier is used for indicating to execute a data writing operation or a data reading operation.
Further, before performing a data writing operation or a data reading operation in the target storage object based on the page fault processing information, to obtain a processing result, the method further includes:
And determining the target storage object based on a target identifier in the page fault processing information, wherein the target storage object is a memory of the FPGA chip under the condition that the target identifier is used for indicating to execute the data writing operation, and is a random access memory of the FPGA chip under the condition that the target identifier is used for indicating to execute the data reading operation.
Further, the executing the data writing operation or the data reading operation in the target storage object based on the page fault processing information to obtain a processing result includes:
Under the condition that the target mark carried in the page fault processing information is used for indicating to execute data writing operation, executing interrupt operation on a communication link between the FPGA chip and the central processing unit;
Detecting whether the first data exists in a buffer area connected with the FPGA chip;
Writing the first data from a buffer into the memory in the presence of the first data in the buffer, wherein the first data is written into the buffer by the central processing unit after the communication link is interrupted;
And updating page table information of a page table in the memory by using the first data to obtain updated page table information, and determining the updated page table information as the processing result.
Further, the executing the data writing operation or the data reading operation in the target storage object based on the page fault processing information to obtain a processing result includes:
under the condition that a target mark carried in the page fault processing information is used for indicating to execute data reading operation, acquiring a page fault address from associated data of the target mark;
Inquiring whether the page missing address exists in a buffer area connected with the FPGA chip, and obtaining an inquiry result;
And executing the data reading operation corresponding to the query result to obtain the processing result.
Further, the executing the data reading operation corresponding to the query result includes:
Generating first notification information when the query result indicates that the page missing address exists, wherein the first notification information is used for notifying the central processing unit to read second data corresponding to the page missing address from the buffer area;
and under the condition that the query result is that the page missing address does not exist, reading update data from the MEM controller connected with the FPGA chip, writing the update data into the buffer area, updating the fast table information in the random access memory, and sending second notification information to the central processing unit, wherein the second notification information is used for notifying the central processing unit to read second data corresponding to the page missing address from the buffer area.
According to another aspect of the embodiment of the present application, there is also provided a page fault handling apparatus, including:
The receiving module is used for receiving a page fault processing request from the central processing unit, wherein the page fault processing request is triggered when the central processing unit determines that a page table entry has a page fault;
The analyzing module is used for analyzing the page fault processing request to obtain page fault processing information carried by the page fault processing request;
The execution module is used for executing data writing operation or data reading operation in a target storage object based on the page fault processing information to obtain a processing result, wherein the target storage object is deployed on the FPGA chip;
And the sending module is used for feeding back the processing result to the central processing unit so that the central processing unit updates the page table entry according to the processing result.
According to another aspect of the embodiment of the application, the application also provides a page fault processing system, which comprises a central processing unit and an FPGA chip;
The central processing unit is used for acquiring a virtual address, generating a page table entry address according to the virtual address, reading the page table entry from the memory according to the page table entry address, detecting the page table entry, and sending a page fault processing request to the FPGA chip under the condition that a page fault exists in the page table entry;
The FPGA chip is used for receiving a page fault processing request from the central processing unit, analyzing the page fault processing request to obtain page fault processing information carried by the page fault processing request, executing data writing operation or data reading operation in a target storage object based on the page fault processing information to obtain a processing result, wherein the target storage object is arranged on the FPGA chip, and feeding back the processing result to the central processing unit so that the central processing unit can update the page table entry according to the processing result.
According to another aspect of the embodiments of the present application, there is also provided a storage medium including a stored program that performs the above steps when running.
According to another aspect of the embodiment of the application, there is also provided an electronic device, including a processor, a communication interface, a memory and a communication bus, where the processor, the communication interface, and the memory complete communication with each other through the communication bus, where the memory is used to store a computer program, and the processor is used to execute the steps in the above method by running the program stored on the memory.
Embodiments of the present application also provide a computer program product comprising instructions which, when run on a computer, cause the computer to perform the steps of the above method.
Compared with the prior art, the technical scheme provided by the embodiment of the application has the advantages that when the central processing unit determines that the page table entry has the page fault, the FPGA chip is requested to execute the page fault processing operation, and the mode of accessing the FPGA chip to replace the original access disk is adopted, so that the central processing unit can conveniently and quickly access, and meanwhile, a large amount of central processing unit resources are not required to be consumed.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments, illustrative embodiments of the present application and descriptions thereof are used to explain the present application and do not constitute undue limitations of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
It should be noted that in this document, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another similar entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
The embodiment of the application provides a page fault processing method, device, system, electronic equipment and storage medium. The method provided by the embodiment of the application can be applied to any needed electronic equipment, for example, the electronic equipment can be a server, a terminal and the like, is not particularly limited, and is convenient to describe and is called as the electronic equipment for short hereinafter.
According to an aspect of the embodiment of the application, a method embodiment of a page fault processing method is provided. Fig. 1 is a flowchart of a page fault processing method according to an embodiment of the present application, as shown in fig. 1, where the method includes:
Step S11, receiving a page fault processing request from the central processing unit, wherein the page fault processing request is triggered by the central processing unit when determining that a page fault exists in a page table entry.
The method provided by the embodiment of the application is applied to the FPGA chip, the FPGA chip is deployed in the page fault processing system, and the FPGA chip is in communication connection with a central processing unit in the page fault processing system. The central processing unit acquires the virtual address, generates a page table entry address according to the virtual address, reads the page table entry from the memory according to the page table entry address, detects the page table entry, and sends a page fault processing request to the FPGA chip when a page fault exists in the page table entry. After receiving the page fault processing request, the FPGA chip executes corresponding page fault processing operation according to the page fault processing request.
Specifically, as shown in FIG. 2, the FPGA chip comprises a CXL subsystem (comprising CXL.io, CXL.mem sub-protocol layers, CXL Coherency Engine and CXL phy), a fast table control unit, a bus arbitration management module, a MEM controller, a control register, a status register and the like. The CXL.io sub-protocol is used for realizing IO communication between HOST and FPGA, and comprises the functions of link training, command sending, msi-x interrupt and the like, the CXL.mem sub-protocol is used for MEM access control, and the TLB fast table control unit is used for caching MEM. The bus arbitration management module is responsible for access arbitration of the plurality of MEMs.
In the embodiment of the application, before receiving the page fault processing request, the FPGA chip initializes a communication link between the FPGA chip and the central processing unit to wait for the central processing unit to send the page fault processing request, and after the page fault processing request exists in the communication link, CXL.Engine of the FPGA chip receives the page fault processing request.
And S12, analyzing the page fault processing request to obtain page fault processing information carried by the page fault processing request.
In the embodiment of the present application, as shown in fig. 3, step S12, analyzing a page fault processing request to obtain page fault processing information carried by the page fault processing request, includes the following steps A1-A2:
and step A1, calling a computer quick link protocol to analyze the page fault processing request to obtain original page fault processing information.
In the embodiment of the application, the FPGA chip can call a computer quick link protocol (CXL.io sub-protocol) to analyze the page fault processing request, and the obtained original page fault processing information comprises information such as a target identification, a data source, an address, page fault or exchange. The target identifier is used for indicating to execute a data writing operation or a data reading operation, and it should be noted that if the target identifier is the data writing identifier, the page swapping operation needs to be executed. If the target identifier is a data reading identifier, a page fault operation needs to be executed.
And step A2, extracting a target identifier from the original page fault processing information and associated data of the target identifier, and determining the target identifier and the associated data as page fault processing information.
In the embodiment of the application, the target mark and the associated data of the target mark are extracted from the original page fault processing information, and when the target mark is the data writing mark, the associated data of the target mark does not need to be extracted from the original page fault processing information. And under the condition that the target identifier is a data reading identifier, extracting the missing page address from the original missing page processing information, and taking the missing page address as associated data. After the target identification and the associated address are obtained, the target identification and the associated data are determined to be page fault processing information.
And step S13, performing data writing operation or data reading operation in the target storage object based on the page fault processing information to obtain a processing result, wherein the target storage object is deployed on the FPGA chip.
In the embodiment of the application, before the data writing operation or the data reading operation is executed in the target storage object based on the page fault processing information to obtain the processing result, the method further comprises determining the target storage object based on the target identification in the page fault processing information.
In the embodiment of the application, the target identifier is used for indicating the execution of the data writing operation or the data reading operation. At this time, different target storage objects are set according to data reading operation or data writing operation, and meanwhile, a page table is stored in a memory of the FPGA chip, and a fast table is stored in a random access memory of the FPGA chip. Therefore, the target storage object is the memory of the FPGA chip in the case that the target identifier is used for indicating that the data writing operation is performed, and is the random access memory of the FPGA chip in the case that the target identifier is used for indicating that the data reading operation is performed.
In the embodiment of the present application, step S13, performing a data writing operation or a data reading operation in a target storage object based on the page fault processing information, obtains a processing result, includes the following steps B1-B4:
and B1, under the condition that the target mark carried in the page fault processing information is used for indicating to execute the data writing operation, executing the interrupt operation on the communication link between the FPGA chip and the central processing unit.
And B2, detecting whether first data exist in a buffer area connected with the FPGA chip.
And B3, under the condition that the first data exists in the buffer area, writing the first data into the memory from the buffer area, wherein the first data is the data written into the buffer area by the central processing unit after the communication link is interrupted.
And B4, updating page table information of a page table in the memory by using the first data to obtain updated page table information, and determining the updated page table information as a processing result.
In the embodiment of the present application, when the target identifier is used to indicate to perform a data writing operation, an interrupt operation is performed on a communication link between the FPGA chip and the central processor, and at this time, the central processor detects that the communication link is interrupted, and the central processor directly writes the first data into the buffer. The FPGA chip notifies the central processor by interrupting the communication link, so that the central processor sends the first data to the buffer when the communication link is interrupted.
In the embodiment of the application, whether first data exist in the buffer area of the FPGA chip or not, and under the condition that the first data exist in the buffer area, the first data are written into the memory of the FPGA chip from the buffer area. And then updating page table information in the memory, and determining the updated page table information as a processing result. It should be noted that, in the embodiment of the application, the page table is arranged in the FPGA chip, so that when the page exchange is performed, the data sent by the central processing unit can be stored in the memory of the FPGA chip, the page table is transferred from the system disk to the inner side of the FPGA chip for storage, the central processing unit can conveniently and quickly access, a large amount of resources of the central processing unit can not be consumed, and the access efficiency of the central processing unit is improved.
In the embodiment of the present application, step S13, performing a data writing operation or a data reading operation in a target storage object based on the page fault processing information, obtains a processing result, includes the following steps C1 to C3:
and step C1, acquiring the page missing address from the associated data of the target mark under the condition that the target mark carried in the page missing processing information is used for indicating to execute the data reading operation.
And C2, inquiring whether a page missing address exists in a buffer area connected with the FPGA chip, and obtaining an inquiry result.
And step C3, executing data reading operation corresponding to the query result to obtain a processing result.
In the embodiment of the application, under the condition that the target identifier is used for indicating to execute the data reading operation, the FPGA chip can directly acquire the page missing address from the associated data, then inquire whether the page missing address exists in the buffer zone, execute the corresponding data reading operation according to the inquired result,
Specifically, the data reading operation corresponding to the query result is executed, including the following steps C301-C302:
and generating first notification information when the query result is that the missing page address exists, wherein the first notification information is used for notifying a central processing unit to read second data corresponding to the missing page address from a buffer area.
Or under the condition that the query result is that the page missing address does not exist, reading update data from the MEM controller connected with the FPGA chip, writing the update data into the buffer area, updating the fast table information in the random access memory, and sending second notification information to the central processing unit, wherein the second notification information is used for notifying the central processing unit to read second data corresponding to the page missing address from the buffer area.
In the embodiment of the application, when the query result is that the page missing address exists, the first notification information is used as the processing result. And taking the second notification information as a processing result when the query result is that the page missing address does not exist.
Step S14, feeding back the processing result to the central processing unit so that the central processing unit updates the page table entry according to the processing result.
According to the application, when the central processing unit determines that the page table entry has the page fault, the FPGA chip is requested to execute the page fault processing operation, and the mode of accessing the FPGA chip to replace the original access disk is adopted, so that the central processing unit can conveniently and quickly access, and meanwhile, a large amount of central processing unit resources are not required to be consumed.
Fig. 4 is a block diagram of a page fault handling apparatus according to an embodiment of the present application, where the apparatus may be implemented as part or all of an electronic device by software, hardware, or a combination of both. As shown in fig. 4, the apparatus includes:
A receiving module 31, configured to receive a page fault handling request from a central processing unit, where the page fault handling request is triggered when the central processing unit determines that a page fault exists in a page table entry;
The parsing module 32 is configured to parse the page fault processing request to obtain page fault processing information carried by the page fault processing request;
The execution module 33 is configured to execute a data writing operation or a data reading operation in a target storage object based on the page fault processing information to obtain a processing result, where the target storage object is disposed on the FPGA chip;
and the sending module 34 is used for feeding back the processing result to the central processing unit so that the central processing unit updates the page table entry according to the processing result.
In the embodiment of the application, the analyzing module is used for calling a computer quick link protocol to analyze the page fault processing request to obtain original page fault processing information, extracting a target identifier and associated data of the target identifier from the original page fault processing information, and determining the target identifier and the associated data as the page fault processing information, wherein the target identifier is used for indicating to execute data writing operation or data reading operation.
The page fault processing device further comprises a determining module, wherein the determining module is used for determining a target storage object based on a target identifier in page fault processing information, the target storage object is a memory of the FPGA chip when the target identifier is used for indicating to execute data writing operation, and the target storage object is a random access memory of the FPGA chip when the target identifier is used for indicating to execute data reading operation.
In the embodiment of the application, the execution module is used for executing interrupt operation on a communication link between the FPGA chip and the central processing unit under the condition that a target mark carried in the page fault processing information is used for indicating execution of data writing operation, detecting whether first data exist in a buffer area connected with the FPGA chip, writing the first data into a memory from the buffer area under the condition that the first data exist in the buffer area, wherein the first data are data written into the buffer area by the central processing unit after the communication link is interrupted, updating page table information of a page table in the memory by utilizing the first data, obtaining updated page table information, and determining the updated page table information as a processing result.
In the embodiment of the application, the execution module is used for acquiring the page missing address from the associated data of the target mark under the condition that the target mark carried in the page missing processing information is used for indicating to execute the data reading operation, inquiring whether the page missing address exists in a buffer area connected with the FPGA chip to obtain an inquiry result, and executing the data reading operation corresponding to the inquiry result.
In the embodiment of the application, the execution module is used for sending first notification information to the central processing unit when the query result is that the page missing address exists, so that the central processing unit reads second data corresponding to the page missing address from the buffer area according to the first notification information, reading updated data from the MEM controller connected with the FPGA chip when the query result is that the page missing address does not exist, writing the updated data into the buffer area, and sending second notification information to the central processing unit, so that the central processing unit reads the second data corresponding to the page missing address from the updated data in the buffer area according to the second notification information.
Fig. 5 is a block diagram of a page fault handling system according to an embodiment of the present application, where the system may be implemented as part or all of an electronic device by software, hardware, or a combination of both. As shown in fig. 5, the system includes a central processor 51 and an FPGA chip 52;
The central processing unit 51 is configured to obtain a virtual address, generate a page table entry address according to the virtual address, read a page table entry from the memory according to the page table entry address, detect the page table entry, and send a page fault processing request to the FPGA chip when a page fault exists in the page table entry;
The FPGA chip 52 is used for receiving a page fault processing request from the central processing unit, analyzing the page fault processing request to obtain page fault processing information carried by the page fault processing request, executing data writing operation or data reading operation in the target storage object based on the page fault processing information to obtain a processing result, wherein the target storage object is arranged on the FPGA chip, and feeding back the processing result to the central processing unit to enable the central processing unit to update page table entries according to the processing result.
In the embodiment of the application, the FPGA chip is connected with the CPLD, the flash memory and the MEM controllers, as shown in fig. 6, the system adopts the FPGA as a main processing chip, the CPLD is used for power management and board card management, supports 4 paths of large-capacity DDR, the interface adopts CXL protocol, is compatible with PCIe protocol in physical form, and the board card can be directly inserted into a PCIe slot of a main board through a golden finger.
In the embodiment of the application, the processing flow of the system is as follows:
Step 1, a central processing unit generates a virtual address.
And 2, the memory management unit of the central processing unit generates a page table entry address according to the virtual address generated by the central processing unit.
And 3, reading the memory to obtain the page table entry corresponding to the page table entry address.
And 4, the memory management unit judges whether the effective flag bit of the page table entry is 0, if the effective flag bit is 0, the page table entry triggers a page fault processing request, and the FPGA chip executes a page fault exception processing program.
And 5, determining the page missing or page exchange related information by the page missing exception processing program, and sending the information to the CXL HOST.
And 6, CXL HOST realizes the reading and writing operation of the MEM on the FPGA side through CXL.io and CXL.mem. And paging the new page into the local memory while the system updates the page table entries in the local memory.
And 7, returning the page fault processing program to the original process, and executing the instruction causing the page fault again. Because the new page is cached in memory, the memory management unit hits, thereby generating a physical address, and the process continues.
The embodiment of the application also provides an electronic device, as shown in fig. 7, where the electronic device may include a processor 1501, a communication interface 1502, a memory 1503 and a communication bus 1504, where the processor 1501, the communication interface 1502 and the memory 1503 complete communication with each other through the communication bus 1504.
A memory 1503 for storing a computer program;
The processor 1501, when executing the computer program stored in the memory 1503, implements the steps of the above embodiments.
The communication bus mentioned by the above terminal may be a peripheral component interconnect standard (PERIPHERAL COMPONENT INTERCONNECT, abbreviated as PCI) bus or an extended industry standard architecture (Extended Industry Standard Architecture, abbreviated as EISA) bus, etc. The communication bus may be classified as an address bus, a data bus, a control bus, or the like. For ease of illustration, the figures are shown with only one bold line, but not with only one bus or one type of bus.
The communication interface is used for communication between the terminal and other devices.
The memory may include random access memory (Random Access Memory, RAM) or may include non-volatile memory (non-volatile memory), such as at least one disk memory. Optionally, the memory may also be at least one memory device located remotely from the aforementioned processor.
The processor may be a general-purpose processor, including a central Processing unit (Central Processing Unit, CPU), a network processor (Network Processor, NP), a digital signal processor (DIGITAL SIGNAL Processing, DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable gate array (FPGA) or other Programmable logic device, discrete gate or transistor logic device, or discrete hardware components.
In yet another embodiment of the present application, a computer readable storage medium is provided, in which instructions are stored, which when run on a computer, cause the computer to perform the page fault handling method according to any one of the above embodiments.
In yet another embodiment of the present application, a computer program product containing instructions that, when run on a computer, cause the computer to perform the page fault handling method of any of the above embodiments is also provided.
In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line), or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk Solid STATE DISK), etc.
The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.
The foregoing is only a specific embodiment of the application to enable those skilled in the art to understand or practice the application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.