Disclosure of Invention
In order to overcome the defects in the prior art, the invention provides a method for reducing the power consumption of USB transmission and an electronic device, which realize the normal function of a USB PHY by using an externally provided 60M clock through closing a PLL, thereby saving the power consumption of one PLL in certain specific scenes.
In order to achieve the above purpose, the present invention may be performed by the following technical scheme:
A method of reducing USB transmission power consumption, comprising:
judging that the USB is about to enter or exit a high-speed mode according to the received control signal, the bus state signal and the current connection state;
If the high-speed mode is about to be entered, opening the PLL of the USB, and switching a clock source to the PLL;
and if the high-speed mode is about to be exited, switching the clock source of the USB to an externally provided clock, and closing the PLL.
The method for reducing the power consumption of USB transmission further obtains the current bus state signal according to the signal level on the port of the USB.
The method for reducing the power consumption of USB transmission as described above further comprises the current connection state including reset handshake, high-speed idle, full-speed idle, high-speed sleep, full-speed sleep state.
An electronic device for reducing USB transmission power consumption, comprising:
a first transceiver;
a second transceiver having a lower transmission data rate than the first transceiver, and the first transceiver and the second transceiver communicate with another electronic device through a data line DP and a data line DM;
a clock unit having a first clock circuit and a second clock circuit and connected to the first transceiver and the second transceiver, respectively; and
A controller connected to the first transceiver, the second transceiver and the clock unit, respectively, wherein,
The controller judges whether the subsequent operation mode of the USB is a high-speed mode or a non-high-speed mode according to the control signals, the bus state signals and the current connection state received by the first transceiver or/and the second transceiver of the USB.
In the electronic device for reducing USB transmission power consumption, the clock unit further switches between the first clock circuit and the second clock circuit according to an instruction sent by the controller.
In the electronic device for reducing USB transmission power consumption, when the controller determines that the USB is in the non-high speed mode or is about to enter the non-high speed mode, the clock source of the USB is changed from the first clock circuit to the second clock circuit.
In the electronic device for reducing USB transmission power consumption, when the controller determines that the USB is in the high-speed mode or is about to enter the high-speed mode, the clock source of the USB is changed from the second clock circuit to the first clock circuit.
In the electronic device for reducing USB transmission power consumption, the first transceiver and/or the second transceiver may further obtain a current bus status signal according to a signal level on a port of the USB.
The electronic device for reducing USB transmission power consumption as described above, further, the current connection state machine includes a reset handshake, a high-speed idle, a full-speed idle, a high-speed sleep, and a full-speed sleep state.
The electronic device for reducing USB transmission power consumption as described above, further, the first transceiver is of USB2.0 standard supporting 480Mbps rate; the second transceiver is a USB1.1 specification supporting a 12Mbps rate or/and a USB1.0 specification supporting a 1.5Mbps rate.
Compared with the prior art, the invention has the beneficial effects that: the invention provides a method for reducing USB transmission power consumption and an electronic device, which realize the normal function of a USB PHY by using an externally provided 60M clock through closing a PLL, thereby saving the power consumption of one PLL in certain specific scenes.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Examples:
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed or inherent to such process, method, article, or apparatus.
In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise. Furthermore, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
Referring to fig. 1 to 6, the present invention provides a method and an electronic device for reducing power consumption of USB transmission, which uses an externally provided 60M clock to implement normal functions of USB PHY by turning off PLL, thereby saving power consumption of one PLL in some specific scenarios.
It should be noted that, in the latest version of the USB2.0 interface standard, USB1.1 is 12Mbps, and the new USB2.0 standard classifies USB interface speeds into three types, namely, high-speed interfaces (abbreviated as HS) with transmission rates of 25Mbps-400Mbps (maximum 480 Mbps); a Full-speed interface (FS) with a transmission rate of 500Kbps-10Mbps (maximum 12 Mbps); the transmission rate is a Low-speed interface (LS) of 10kbps-400100kbps (maximum 1.5 Mbps).
Note that DM is a data line D- (normally white line) of the USB, and DP is a data line d+ (normally green line) of the USB.
The full speed USB peripheral (FS) and the low speed USB peripheral (LS) are distinguished by a 1.5K pull-up resistor on the D+ or D-data line, D+ being the full speed peripheral and D-being the low speed peripheral. The identification of the high-speed peripheral device can be identified by handshaking the host and the high-speed peripheral device.
The USB PHY of the present invention is a device connected to a USB controller, has a speed of 480Mbps or more at the maximum, and is a high-speed USB device compliant with the USB2.0 standard specification. Further, the USB PHY according to the present invention is in the form of a module or a device, which can be loaded in a portable terminal apparatus.
It should be noted that, in the following embodiments, the first transceiver and the second transceiver of the present invention are also referred to as a high-speed transceiver and a non-high-speed transceiver, respectively.
Referring to fig. 1, a USB host 101 connects the USB host 101 and a first USB PHY 102 through a connection line or a data cable inside an integrated circuit, and transmits and receives data. The USB slave 104 connects the USB slave 104 and the second USB PHY 103 through a connection line or a data cable inside the integrated circuit, wherein the first USB PHY 102 and the second USB PHY 103 communicate through a data line DM and a data line DP.
The method of clock switching of the clock unit in this embodiment is shown in fig. 2. The PLL is in an off state when the PHY is reset, defaults to an off state after reset release, and does not open until certain conditions are met. When the high speed mode is subsequently entered, the PLL is turned on, and after the PLL stabilizes, the phase Guan Shizhong source is switched to the clock generated by the PLL. When the high speed mode is subsequently exited, the Guan Shizhong source is switched to the external clock and the PLL is turned off. The logic to determine whether the PLL needs to be switched later may be implemented within the PHY or within the controller. The circuit using the PLL and its divided clock is a first clock circuit, and the circuit using the external clock is a second clock circuit. It can be understood that only one wake-up signal in this embodiment, i.e. the wake-up signal conforming to the USB standard protocol, is used, the controller determines the data rate of the subsequent normal operation mode according to the connection state before entering sleep, and determines whether the clock source selects the external low frequency clock or the PLL high frequency clock according to the data rate. With reference to fig. 1, further, after receiving the sleep signal, the PLL clock is directly turned off, after receiving the wake-up signal, the subsequent connection state is determined according to the wake-up signal and the previous connection state, and the clock source of the normal working mode is switched according to the subsequent connection state. In the above embodiment, further, the controller switches the clock source according to the predetermined peripheral connection state and when the sleep is finished, and selects the available clock source with the smallest power consumption according to the data transmission rate, which saves the power consumption during the normal operation (non-sleep).
Table 1 USB timing parameters table for high speed handshake operation
Referring to fig. 3 and table 1, fig. 3 is a schematic flow chart of a high-speed handshake performed by the USB. If the final arbitration result of the reset handshake is full speed or low speed, the PLL does not need to be started, so this embodiment does not involve other reset handshake procedures, but only analyzes the high-speed mode handshake procedure. When the host state machine is in an unconnected state at time T0, the device DP is pulled up to 3.3V through a 1.5K resistor, DM is pulled down to ground, the host state machine enters a reset state, a xcvrsel signal is set to 0, a termsel signal is set to 0, a 45 omega termination resistor is opened, and the bus becomes SE0. If the device supports the high-speed mode, the device enters the high-speed mode at the time T1 to start transmitting the Chirp K (a port signal defined in a USB standard protocol), the length of the Chirp K transmitted by the slave is at least 1ms, and the host starts transmitting the KJ sequence after detecting that the Chirp K transmitted by the device is ended. For the slave, after seeing that the host sends 6 KJ sequences, the slave considers that the host supports the high-speed mode, and then enters the high-speed mode, at the moment, the slave can turn on the PLL, and after the PLL is stabilized, the clock source is switched to the PLL clock. According to USB protocol section 7.1.7.5, the device can be switched to a high-speed mode only after TWTHS at the time of T4, the maximum value of TWTHS is 500us, and the PLL only needs 50us from opening to stabilization in design, so that the time sequence requirement of the protocol can be met. For the host, according to the USB protocol section 7.1.7.5, the interval between T6 and T7 is not less than 100us and not more than 500us, if the host turns on the PLL at time T6, after 50us, the PLL can switch the clock source to the PLL clock after the PLL stabilizes, so as to satisfy the timing requirement of the USB protocol.
TABLE 2 USB timing parameters Table for Supend operation
Referring to fig. 4 and table 2, fig. 4 is a schematic diagram showing that the USB enters a sleep state. Entering sleep from high speed mode is necessarily a host initiated operation, with the software setting the host to enter sleep state at time T0, the host ceasing to send data (including SOF), after which the bus is in SE0 (a port level state defined in the USB standard protocol). For the slave, after seeing SE0 for 3ms, the slave will determine whether SE0 at this time is a reset flow or a sleep flow: if this is the reset procedure, then subsequent flows Cheng Canjian are the high-speed handshake of FIG. 3. If the sleep process is performed, the controller sets the PHY to sleep state before the T3 time and the T5 time, turns off the PLL, and switches the clock source to the external clock. For the host, the USB protocol does not specify a point in time when the host enters a sleep state, nor does the USB protocol specify that the host must enter a low power state, and the designer decides the processing mode at his discretion. In the design scheme of the invention, the host enters into dormancy 4ms after sending dormancy operation, closes the PLL and switches the clock source to the external clock.
Table 3 USB timing parameters table for high speed remote_wakeup operations
Referring to fig. 5 and table 3, fig. 5 is a schematic flow chart of a USB high-speed remote wakeup operation. When the device goes to sleep long enough, i.e., after the time point T4 in fig. 4, the software may initiate a remote wake-up operation, the controller notifies the PHY to exit from sleep state at the time T0, the PLL is not required to be started at this time even before the device goes to sleep, the xcvrsel signal is 1, the termsel signal is 1, the PHY is in full-speed mode, and the controller sets the txvalid signal high after the utmi_clk is stabilized, the PHY starts to transmit full-speed K signal at the time T1, and the K signal hold time of the slave is not less than TDRSMDN and not more than TDRSMUP. Because the host only has 15K pull-down resistor to the ground, the signal intensity sent by the device is larger, the bus is in a K state, the host recognizes the wake-up signal sent by the slave at the moment T2 after seeing the continuous K signal on the bus, and the host exits from the sleep state, starts to send the full-speed K signal, and continues to the time point T5, and the duration is not less than 20ms (TDRSMDN). As can be seen from fig. 4, if the slave PHY starts the PLL 15ms after the time T1 is transmitted, the start of the PLL operation can be completed within 50us, and there is enough time to complete the clock switching before the time point T5. The master starts the PLL 15ms after seeing the wake-up signal of the slave (theoretically, the time is within 16ms after the time point T1), the PLL start operation can be completed within 50us, and the clock switching is completed before the time point T6.
Table 4 USB timing parameters table for high speed resume operation
Referring to fig. 6 and table 4, fig. 6 is a schematic flow chart of the USB performing the high-speed wake operation. The software starts the wake-up operation at the time of T0, the controller informs the PHY to exit from the sleep state, the PLL is not required to be started at the moment even if the device is in a high-speed state before entering into the sleep state, the xcvrsel signal is 1, the termsel signal is 1, the PHY is in a full-speed mode, the controller sets the txvalid signal high after the utmi_clk is stabilized, the PHY starts to transmit a full-speed K signal at the time of T1, the wake-up signal transmitted by the PHY needs to last for at least 20ms (TDRSMDN), the slave recognizes the wake-up signal transmitted by the slave at the time of T2 after seeing the continuous K signal on the bus, and the slave exits from the sleep state. As can be seen from fig. 4, if the slave PHY starts the PLL 15ms after the time T2 is transmitted, the start of the PLL operation can be completed within 50us, and there is enough time to complete the clock switching before the time point T5. The host starts the PLL 15ms after the T moment, the start operation of the PLL can be completed within 50us, and clock switching is completed before the T6 time point.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
The above embodiments are only for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement the same, and are not intended to limit the scope of the present invention. All equivalent changes or modifications made in accordance with the essence of the present invention are intended to be included within the scope of the present invention.