Referring to fig. 3 and table 1, fig. 3 is a schematic flow chart of USB high-speed handshake. If the final arbitration result of the reset handshake is full-speed or low-speed, the PLL does not need to start, so this embodiment does not involve other reset handshake flows, and only needs to analyze the high-speed mode handshake flow. At time T0, when the host state machine is in an unconnected state, the device is seen to be present, at this time, the device DP is pulled up to 3.3V through a 1.5K resistor, and DM is pulled down to ground, the host state machine enters a reset state, the xcvrel signal is set to 0, the termsel signal is set to 0, and the 45 Ω terminating resistor is openedThe bus will become SE 0. If the device supports the high-speed mode, the device enters the high-speed mode at the time of T1 and starts to transmit Chirp K (a port signal defined in a USB standard protocol), the Chirp K length transmitted by the slave computer is maintained for at least 1ms, and the master computer starts to transmit the KJ sequence after detecting that the Chirp K transmitted by the device is finished. For the slave, the slave considers that the master supports the high-speed mode after seeing that the master sends 6 KJ sequences, and then enters the high-speed mode, at the moment, the slave can open the PLL, and after the PLL is stabilized, the clock source is switched to the PLL clock. According to USB protocol section 7.1.7.5, the device only needs to be T after time T4_WTHSIt is only necessary to complete the switching to the high-speed mode internally, T_WTHSThe maximum value is 500us, and the PLL only needs 50us from opening to stabilizing in design, so that the timing requirement of the protocol can be met. For the host, according to the USB protocol section 7.1.7.5, the interval from T6 to T7 is not less than 100us and not more than 500us, and if the host turns on the PLL at time T6, after 50us, the PLL is stable, the clock source can be switched to the PLL clock, which can meet the timing requirement of the USB protocol.

TABLE 2 timing parameter table for USB Suspend operation

Referring to fig. 4 and table 2, fig. 4 is a schematic diagram illustrating the USB entering into the sleep state. Going to sleep from the high speed mode is necessarily a host initiated operation, and at time T0 the software sets the host to go to sleep, the host stops sending data (including SOF), and the bus is thereafter in SE0 (a port level state defined in the USB standard protocol). For the slave, after seeing the SE0 for 3ms, the slave determines whether the SE0 is a reset flow or a sleep flow: if it is a reset flow, the subsequent flow refers to the high-speed handshake of fig. 3. If it is a sleep flow, the controller sets the PHY to a sleep state before the time point T3 and the time point T5, turns off the PLL, and switches the clock source to the external clock. For the host, the USB protocol does not specify the time point when the host enters the sleep state, nor does it specify the low power consumption state that the host must enter, and the designer decides the processing method at his discretion. In the design scheme of the invention, the host enters the sleep mode 4ms after the sleep operation is sent, the PLL is closed, and the clock source is switched to the external clock.

TABLE 3 timing parameter table for USB to perform high-speed remote _ wakeup operation

Referring to fig. 5 and table 3, fig. 5 is a schematic flowchart of the USB performing the high-speed remote wake-up operation. When the device enters sleep for a long enough time, that is, after time point T4 in fig. 4, the software may initiate the remote wakeup operation, and the controller at time T0 notifies the PHY to exit the sleep state, and even if the device is in the high-speed state before entering sleep and the PLL does not need to be started at this time, the xcvrel signal is 1, the termsel signal is 1, the PHY is in the full-speed mode, after utmi _ clk is stable, the controller sets the txvalid signal high, and the PHY starts to transmit the full-speed K signal at time T1, and the K signal holding time of the slave is not less than TDRSMDN and not greater than TDRSMUP. At this time, only 15K of pull-down resistors are pulled down to the ground at the host end, the signal strength sent by the device is larger, the bus is in a K state, the host recognizes a wake-up signal sent by the slave at time T2 after seeing the continuous K signal on the bus, exits from the sleep state, and starts to send a full-speed K signal, and the full-speed K signal continues to a time point T5 for a time period of not less than 20ms (tdrsmdn). As can be seen from fig. 4, if the slave PHY starts the PLL 15ms after the time T1 is transmitted, the start PLL operation can be completed within 50us, and there is enough time to complete the clock switching before the time T5. The host starts the PLL 15ms after seeing the wake-up signal of the slave (theoretically, the timing is 16ms after the time point of T1), the PLL start operation can be completed within 50us, and the clock switching is completed before the time point of T6.

TABLE 4 timing parameter table for USB high speed resume operation

Referring to fig. 6 and table 4, fig. 6 is a schematic flowchart of the USB performing the high-speed wake-up operation. At time T0, the software starts the wake-up operation, the controller notifies the PHY to exit the sleep state, even if the device is in a high-speed state before entering the sleep state, the PLL does not need to be started at this time, the xcvrel signal is 1, the termsel signal is 1, the PHY is in a full-speed mode, and after utmi _ clk is stable, the controller sets the txvalid signal high, at time T1, the PHY starts to transmit a full-speed K signal, the wake-up signal transmitted by the PHY needs to last at least 20ms (tdrsmdn), and after the slave sees the K signal that continues on the bus, the wake-up signal transmitted by the slave is recognized at time T2, and the slave exits the sleep state. As can be seen from fig. 4, if the slave PHY starts the PLL 15ms after the time T2 is transmitted, the start PLL operation can be completed within 50us, and there is enough time to complete the clock switching before the time T5. The host starts the PLL 15ms after T, and the PLL start operation is completed within 50us, and the clock switching is completed before T6.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

The above embodiments are only for illustrating the technical concept and features of the present invention, and the purpose thereof is to enable those skilled in the art to understand the contents of the present invention and implement the present invention accordingly, and not to limit the protection scope of the present invention accordingly. All equivalent changes or modifications made in accordance with the spirit of the present disclosure are intended to be covered by the scope of the present disclosure.

Claims

1. A method for reducing power consumption of USB transmission, comprising:

2. The method of claim 1, wherein the current bus state signal is obtained according to a signal level on a port of the USB.

3. The method of reducing power consumption of USB transmissions according to claim 1, wherein the current connection state comprises reset handshake, high speed idle, full speed idle, high speed sleep, full speed sleep state.

4. An electronic device for reducing power consumption of USB transmission, comprising:

a first transceiver;

a clock unit having a first clock circuit and a second clock circuit and connected to the first transceiver and the second transceiver, respectively; and the number of the first and second groups,

5. The electronic device for reducing power consumption of USB transmission according to claim 4, wherein said clock unit switches between said first clock circuit and said second clock circuit according to the instruction from said controller.

6. The electronic device for reducing power consumption of USB transmission according to claim 5, wherein when said controller determines that said USB is in a non-high speed mode or is about to enter a non-high speed mode, said controller changes the clock source of said USB from said first clock circuit to said second clock circuit.

7. The electronic device for reducing power consumption of USB transmission according to claim 5, wherein when said controller determines that said USB is in high-speed mode or is about to enter high-speed mode, the clock source of said USB is changed from said second clock circuit to said first clock circuit.

8. The electronic device for reducing power consumption of USB transmission according to claim 4, wherein the first transceiver or/and the second transceiver obtains the current bus status signal according to the signal level on the port of the USB.

9. The electronic device for reducing power consumption of USB transmissions according to claim 4, wherein said current connection state machine includes reset handshake, high speed idle, full speed idle, high speed sleep, full speed sleep states.

10. The electronic device for reducing power consumption of USB transmission according to claim 4, wherein the first transceiver is USB2.0 specification supporting 480Mbps rate; the second transceiver is USB1.1 specification supporting 12Mbps rate or/and USB1.0 specification of 1.5Mbps rate.