Disclosure of Invention
In view of the above, the present application is directed to a control circuit, an overvoltage protection circuit, a control chip and a driving power supply, so as to solve the problems of misjudgment of overvoltage protection caused by temperature change, complicated structure of the control circuit, and possible damage of temperature to a power supply system in the existing overvoltage protection circuit.
The technical scheme of the application is as follows:
The control circuit comprises a reference voltage source, a logic control module and a driving MOS tube, wherein the reference voltage source is used for providing a first reference voltage, the logic control module is used for closing the driving MOS tube based on the first reference voltage and the sampling voltage of the driving MOS tube, and in the closing state of the driving MOS tube, the logic control module is used for starting the driving MOS tube based on the gate end voltage of the driving MOS tube, wherein the first reference voltage is reduced along with the increase of the temperature after the temperature reaches an over-temperature point. The control circuit of the scheme provides an effective driving power supply control method, and is simple and effective and low in control cost.
The reference voltage source comprises a reference module and an over-temperature protection module, wherein the reference module is used for generating reference voltage which does not change along with temperature, and the over-temperature protection module is used for directly outputting or outputting the reference voltage after processing, and the voltage output by the over-temperature protection module is a first reference voltage. On the other hand, the reference voltage of the reference module is output through the temperature protection module, for example, the over-temperature protection module outputs the received reference voltage after processing or not processing according to the over-temperature protection strategy (such as over-temperature point), the output first reference voltage may be the received reference voltage, or the processed reference voltage with different magnitude from the received reference voltage, and the reference voltage (the first reference voltage) is input into other modules of the control circuit as the reference voltage or the reference voltage (such as input ends of the comparators U1 and U2). The voltage (first reference voltage) which is used as the reference voltage or the reference voltage is related to an over-temperature protection strategy, so that the control of the driving power supply can be related to the environmental temperature adaptability, and the safety of the driving power supply is protected. In addition, when the logic control module is in overvoltage protection, the reference voltage (first reference voltage) is output from the over-temperature protection module, and the value of the reference voltage is referenced with the ambient temperature, so that the chip can be prevented from being misjudged and entering an overvoltage protection mode due to the ambient temperature of the chip.
Further, when the temperature reaches the over-temperature point, the first reference voltage linearly decreases with an increase in temperature.
Further, the first reference voltage is equal to the reference voltage before the temperature reaches the over-temperature point.
The logic control module comprises a first comparator, a degaussing detection module, a logic processing unit and a logic processing unit, wherein a first input end of the first comparator inputs sampling voltage of the driving MOS tube, a second input end of the first comparator inputs the first reference voltage, when the sampling voltage of the driving MOS tube is larger than or equal to the first reference voltage, an output signal of the first comparator turns over, the degaussing detection module judges whether the degaussing of a system inductor is finished or not through detecting gate end voltage of the driving MOS tube, the degaussing detection module outputs a first signal if the degaussing of the system inductor is finished, the turning level output by the first comparator triggers the logic processing unit to generate a closing signal to close the driving MOS tube, and the first signal triggers the logic processing unit to generate an opening signal to open the driving MOS tube.
The method comprises the steps that a degaussing detection module detects the gate end voltage of a driving MOS to judge whether the inductance current of a system is zero, after the inductance current of the system is zero (namely inductance degaussing is finished), the degaussing detection module triggers a logic function module to generate a driving MOS signal to be started, when the driving MOS is started, the sampled voltage is compared with the Vcs voltage (first reference voltage) and is larger than or equal to Vcs, a first comparator turns over, and the logic function module is triggered to generate a driving MOS signal to be closed, so that the MOS is closed.
Further, the driving MOS tube is connected with a sampling resistor, and when the driving MOS tube is conducted, current flows through the sampling resistor to form the sampling voltage. The sampled voltage reflects the magnitude of the current flowing through the driving MOS, and reaches a maximum value when the current reaches a peak value. Since the voltage can be obtained by collecting the voltage at one end of the driving MOS, the sampling voltage can be called as the sampling voltage of the driving MOS tube in the application.
The application provides an overvoltage protection circuit which comprises a current source, a capacitor, a second comparator and a control circuit provided by the first aspect, wherein the current source is used for providing current, the capacitor is charged based on the current provided by the current source to form first voltage, the first voltage and the first reference voltage are input to the second comparator, when the first voltage is larger than the first reference voltage, the output signal of the second comparator is inverted, the control circuit compares the time duration of time t1 with the time duration of time t2, when t2 is shorter than t1, the control circuit triggers protection logic, the time t1 is the time when the capacitor is charged from 0 to be larger than the first reference voltage, and the time t2 is the system inductance degaussing time. Whether overvoltage is judged by judging the demagnetizing time of the inductor and the time for charging the capacitor to Vcs, the judging mode is simple, and the circuit is easy to realize. According to the scheme, the first reference voltage output by the temperature protection module is input into the second comparator to serve as a base or reference voltage, the value of the first reference voltage is referenced with the ambient temperature, and the chip can be prevented from being misjudged and entering an overvoltage protection mode due to the ambient temperature of the chip. Here, trigger protection logic refers to triggering overvoltage protection.
The current source comprises an operational amplifier, a second resistor and a current mirror, wherein a fixed current flows through the first resistor to form an overvoltage protection voltage, the operational amplifier clamps the overvoltage protection voltage to the second resistor to form a bias current, the bias current is used as an input current of the current mirror, and an output current of the current mirror is output to the capacitor to be charged to form a first voltage.
Further, when the driving MOS tube is turned on, the voltage of the capacitor is pulled down to zero, and when the driving MOS tube is turned off, the current mirror outputs current to charge the capacitor to form a first voltage.
Further, the time t2 is obtained by detecting the gate terminal voltage of the driving MOS transistor.
In a third aspect, the present application provides a control chip comprising an overvoltage protection circuit as provided in the second aspect.
In a fourth aspect, the present application provides a driving power supply including a control chip provided in the third aspect.
Compared with the prior art, the control circuit is simple, the production cost is low, the voltage provided for the system is not influenced by the ambient temperature, the reference voltages of the two comparators are adaptively changed according to the over-temperature protection strategy, the safety of a driving power supply is ensured, and the circuit is ensured not to touch over-voltage protection logic by mistake.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application.
It should be noted that like reference numerals and letters refer to like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, relational terms such as "first," "second," and the like may be used solely to distinguish one entity or action from another entity or action in the description of the application without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
In the description of the present application, it should also be noted that, unless explicitly specified and limited otherwise, the terms "connected" and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, integrally connected, electrically connected, directly connected, indirectly connected through an intermediate medium, or communicating between the two elements. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.
As shown in fig. 1, the present embodiment provides a control circuit 100, wherein the control circuit 100 is connected to a driving MOS transistor M1, and the control circuit controls the driving MOS transistor M1 to be turned off and turned on based on a reference voltage (first reference voltage), a gate voltage of the driving MOS transistor M1, and a sampling voltage of the driving MOS transistor M1. The driving MOS transistor M1 may be included in the control circuit, in addition to being independent of the control circuit as described above.
Optionally, the control circuit 100 includes a reference voltage source 1 and a logic control module 2, the reference voltage source is used for providing a reference voltage Vcs (first reference voltage), the logic control module 2 includes a first input end, a second input end, a third input end and an output end, the first input end of the logic control module is connected with the reference voltage source 1, the first reference voltage Vcs provided by the reference voltage source is input, the second input end is connected with one end (e.g., a source) of the driving MOS transistor M1, the sampling voltage (also referred to as the sampling voltage of the driving MOS transistor M1) is input, the logic control module 2 generates a control signal for closing the driving MOS transistor M1 based on the first reference voltage and the sampling voltage of the driving MOS transistor M1, the third input end of the logic control module is connected with the gate of the driving MOS transistor M1, the gate voltage of the driving MOS transistor M1 is input (detected), the logic control module generates a control signal for opening the driving MOS transistor M1 based on the gate (gate end) voltage of the driving MOS transistor M1 after the driving MOS transistor M1 is in an off state, and the logic control module outputs the control signal to the driving MOS transistor M1.
Optionally, in this embodiment, the reference voltage source includes a reference module and an over-temperature protection module, an output end of the reference module is connected to an input end of the over-temperature protection module, an output end of the over-temperature protection module is connected to a first input end of the logic control module, the reference module generates the reference voltage VREF and inputs the reference voltage VREF to the over-temperature protection module, and outputs the reference voltage VREF through the over-temperature protection module, such as the first reference voltage Vcs, specifically, the reference voltage VREF is processed into the voltage Vcs by the over-temperature protection module and then outputs the voltage Vcs to the logic control module as the reference voltage Vcs received by the logic control module. Specifically, the over-temperature protection module outputs the received reference voltage VREF after processing or not according to the over-temperature protection policy, and the output first reference voltage Vcs may be the received reference voltage VREF or the processed reference voltage different from the received reference voltage VREF, and inputs the first reference voltage Vcs into other modules of the control circuit as the reference voltage or the reference voltage (for example, the input ends of the comparators U1 and U2). The control (such as the closing of MOS) of the driving power supply can be related to the adaptability of the ambient temperature, and the safety of the driving power supply is protected. As shown in fig. 2, when the temperature reaches the over-temperature point, the voltage Vcs output through the temperature protection module forms a monotonically downward curve (also referred to as a monotonically downward negative temperature curve), that is, the first reference voltage Vcs output to the first input terminal by the over-temperature protection module decreases with an increase in temperature. The negative temperature curve may be a straight line with a negative slope, i.e. the first reference voltage Vcs output to the first input terminal by the over-temperature protection module decreases linearly with increasing temperature. In some embodiments, the voltage Vcs output by the temperature protection module is a constant value, preferably the constant value is the reference voltage VREF output by the reference module, before the temperature reaches the over-temperature point. That is, vcs=vref.
The reference voltage VREF provided in the present embodiment does not vary with temperature. Optionally, the reference module is BANDGAP (bandgap reference).
Optionally, the logic control module includes a first comparator U1, a logic processing unit (dashed line box in fig. 3), and a degaussing detection module, where a second input end of the first comparator U1 is connected to an output end of the reference voltage source (such as an output end of the over-temperature protection module), receives the voltage Vcs, a first input end of the first comparator is connected to one end (such as a source) of the driving MOS tube, an output end of the first comparator is connected to the logic processing unit, the sampled voltage and the voltage Vcs are input through the first input end and the second input end of the first comparator, the first comparator compares the voltage Vcs with the sampled voltage, and when the sampled voltage is greater than or equal to the voltage Vcs, an output signal of the first comparator is flipped (such as flipped from a low level to a high level, or flipped from a high level to a low level, in which is related to a specific case that two input signals are input to the in-phase end and the inverting end), and the logic processing unit is triggered to generate the shutdown signal, so that the driving MOS tube M1 is turned off. That is, when the sampling voltage is greater than or equal to the voltage Vcs, the inversion level output by the first comparator U1 triggers the logic processing unit to generate a closing signal to close the driving MOS transistor. The input end of the degaussing detection module is connected with the grid electrode of the driving MOS tube, the output end of the degaussing detection module is connected to the logic processing unit, after the driving MOS tube is closed, the degaussing detection module detects the grid electrode voltage of the driving MOS tube M1 to judge whether the degaussing of the system is finished (namely, whether the inductance current of the system is zero or not) or not, and if the degaussing of the inductance of the system is finished (namely, the inductance current of the system is zero), the degaussing detection module outputs a first signal to the logic processing unit, and the logic processing unit is triggered to generate an opening signal, so that the driving MOS tube is opened. It will be appreciated that the first and second inputs of the first comparator U1 are the second and first inputs of the logic control module 2.
In one possible embodiment, the driving MOS tube is connected to a sampling resistor Rcs, and the other end of the sampling resistor is grounded, and when the driving MOS tube is opened, a current flows through the sampling resistor to form the sampling voltage described in the embodiment. Optionally, a source electrode of the driving MOS tube is connected to the sampling resistor Rcs.
In one possible embodiment, the logic processing unit specifically includes logic modules and a driver, as shown in fig. 3. The driving outputs a driving signal for driving the driving MOS according to a control signal.
As shown in fig. 3, the present embodiment further provides an overvoltage protection circuit, which includes a current source, a capacitor C1, a second comparator U2, and the control circuit 100, wherein when an output terminal of the current source is connected to the capacitor C1, the current source outputs a current to charge the capacitor C1, so as to form a first voltage on the capacitor C1. The first input end of the second comparator U2 is connected with a reference voltage source, receives the voltage Vcs output by the reference voltage source, the second input end is connected with the capacitor C1, the first voltage is input, when the first voltage is larger than the voltage Vcs, the output signal of the second comparator U2 is turned over, the output end of the second comparator is connected to the control circuit 100, the control circuit compares the time duration of time t1 with the time t2, and when the time t2 is shorter than the time t1, the protection logic (overvoltage protection) is triggered. Optionally, when the protection logic is triggered, the driving MOS transistor is turned off, or in other words, the driving MOS transistor is kept turned off, that is, cannot be turned on. In other words, after the protection logic is triggered, the driving MOS transistor is in an off state, which cannot be turned on until the overvoltage protection state is released. The time t1 is a time from 0 to a time greater than the first reference voltage Vcs, and the time t2 is a degaussing time (i.e., a degaussing time of L1 in fig. 4, or a freewheel time of the freewheel diode D1, specifically a time from when the driving MOS is turned off to when the current flowing through the L1 is zero), which may be obtained by detecting a gate terminal voltage of the driving MOS transistor. Specifically, when the driving MOS tube is turned on, the voltage of the capacitor C1 is pulled down to zero, and when the driving MOS tube is turned off, the current source outputs a current to charge the capacitor to form a first voltage. It can be understood that the control circuit records the time Tovp from the closing of the driving MOS transistor to the turning of the second comparator U2 (ovp indicates overvoltage protection), the logic processing unit in the control circuit compares the time Tovp with the length of the degaussing time Td, when the degaussing time Td is longer than the time Tovp, the circuit (chip) works normally without triggering the overvoltage protection logic, and when the degaussing time Td is shorter than the time Tovp, the overvoltage protection logic is triggered. In one embodiment, the circuit (chip) operates normally when the overvoltage protection logic is not triggered, and the driving MOS may be normally turned on. It will be appreciated that time t1 is actually time Tovp, i.e., the time that the capacitor charges from 0 to greater than the first reference voltage is actually equivalent to the time from the turn-off of the driving MOS transistor to the inversion of the second comparator, and the time that the capacitor charges to greater than the first reference voltage is actually considered to be the time to charge to the first reference voltage. The logic processing unit may compare the time Tovp with the degaussing time Td by performing a logic operation (e.g., an and operation) on the received signal output by the degaussing detection module (e.g., when D1 or L current is detected as 0, a high level is output) and the signal output by the second comparator. When the output of the degaussing detection module is high, if the result is 0, the overvoltage protection is triggered, and if not, the degaussing detection module works normally.
The time t2, i.e., the degaussing time Td, may be obtained by detecting the gate terminal voltage of the driving MOS transistor. It will be appreciated that the degaussing time Td, i.e. the time after the MOS is turned off until the current of the system inductance (inductance L1 in fig. 4) is 0, can be detected by the degaussing detection module. For example, when the degaussing detection module detects that the current of the system inductor (inductor L1 in fig. 4) is 0, its output level is inverted, and the moment of inversion represents the moment when the inductor current is 0.
In an alternative embodiment, the current source includes an operational amplifier U3, a second resistor Rb, and a current mirror, where a first input terminal of the operational amplifier U3 receives a voltage, a second input terminal of the operational amplifier U3 is connected to a first terminal of the second resistor Rb and a first terminal of a switching tube M4 (for example, a MOS tube, hereinafter referred to as a MOS tube M4), and a second terminal of the second resistor Rb is grounded. The first terminal of the second resistor Rb is also connected to the input of the current mirror. In one embodiment, as shown in fig. 3, a first end of the second resistor Rb is connected to a first end of the MOS transistor M4, and a second end of the MOS transistor is connected to an input end of the current mirror. The output end of the operational amplifier U3 is connected with the control end of the MOS tube. It should be noted that the MOS transistor may not be required. I.e. the output of U3 is directly connected to the first terminal of Rb and to the input of the current mirror.
Alternatively, the voltage received at the first input terminal of the operational amplifier U3 may be provided through the first resistor Rovp and a fixed current, as shown in fig. 3. It should be noted that the first resistor Rovp is usually arranged externally, not included in the overvoltage protection circuit, and is called an overvoltage protection arrangement resistor outside the control chip for adjusting the voltage of the first end of the U3, and of course, it may also be included in the overvoltage protection circuit or be arranged inside the chip.
Specifically, a fixed current I b (which may be provided by a constant current source) flows through the first resistor Rovp to generate a voltage Vovp (ovp represents overvoltage protection), and the voltage Vovp is clamped to the second resistor Rb by the operational amplifier U3, so as to form a bias current Vovp/Rb, where the bias current is used as an input current of the current mirror, and an output current of the current mirror is output to the capacitor C1, so as to charge the capacitor C1, so as to form a first voltage. In addition, as shown in fig. 3, the current mirror of the present embodiment is formed by two MOS transistors, and in practice, there are many ways to form the current mirror, and the present application is not particularly limited herein. It should be clear that the output current of the current mirror is proportional to its input current, with a proportionality coefficient K (output to input) which is related to the selected MOS transistors.
The output end of the current mirror can be selectively connected to the capacitor C1, or the charge and discharge of the capacitor C1 can be controlled. The application employs a switch module. The output end of the current source is connected with the first end of the switch module, the second end of the switch module is commonly connected with the second end of the second comparator and the first end of the capacitor C1 (the three terminals are commonly connected together in an understandable way), the third end of the switch module and the second end of the capacitor C1 are grounded, and the control end of the switch module is connected with the control end of the driving MOS tube M1.
Optionally, as shown in fig. 3, the switching module includes a first switching tube M2 (e.g., a MOS tube, such as an NMOS tube), and a second switching tube M3 (e.g., a MOS tube), where control ends of the first switching tube and the second switching tube are connected to the control end of the driving MOS tube M1 (may also be considered as being connected to an output end of the logic control module of the control circuit), a first end of the first switching tube is connected to an output end of the current mirror, a second end of the first switching tube, a first end of the second switching tube, a first end of the capacitor C1, and a second end of the second comparator are commonly connected, and a second end of the second switching tube is grounded. The present solution proposes a specific switch module, which can determine the state of the driving MOS according to the gate terminal voltage of the driving MOS, so as to determine whether to charge or discharge the capacitor C1.
Optionally, the first switching tube M2 and the second switching tube M3 are different types of MOS tubes, which receive the same control signal and respectively present opposite on-off states. That is, M2 and M3 are not turned on or off simultaneously, but one is on and the other is off. If M2 is PMOS, M3 is NMOS, and if M2 is NMOS, M3 is PMOS. For example, M1, M3 are selected as NMOS, M2 is selected as PMOS, or M1, M3 are selected as PMOS, M2 is selected as NMOS.
The principle of the overvoltage protection circuit is described below in connection with fig. 3.
From the volt-second characteristic of the inductance, it can be known that:
L*Ip=Vout*Td
wherein L is inductance of L1, ip is peak current, vout is output voltage, and Td is degaussing time;
And ip=vcs/Rcs
Thereby:
Vout=(L*Vcs)/(Rcs*Td)
assuming that Td is a fixed time constant, the voltage of Vout is also fixed, and the smaller Td is, the larger Vout is, so the overvoltage protection logic of the present application detects Td, and when Td is compared with a parameter, and the Td time is smaller than the parameter, the logic processing unit is triggered to enter a protection state, so that Vout is limited to a reference value.
When the driving MOS transistor is turned on, the control terminals (gates) of M2 and M3 are both connected to the gate of the driving MOS transistor M1 (i.e., the output terminal of the logic control module of the aforementioned control circuit). Therefore, M2 is turned off, M3 is turned on, at this time, when M2 is turned off, the output end of the current mirror cannot output current to the capacitor C1 to charge the capacitor C1, and when M3 is turned on, the capacitor C1 discharges through M3, and the voltage of the capacitor C1 is pulled down to zero. When the driving MOS tube is closed, M2 is opened, M3 is closed, at the moment, a discharging loop of the capacitor C1 is disconnected, and the output end of the current mirror is connected to the capacitor C1 through M2, so that the current output by the current mirror charges the capacitor C1 to form a first voltage. When the voltage is larger than the Vcs voltage, the comparator turns over, the period from the closing of the driving MOS to the turning over of the comparator is recorded as Tovp, the chip logic function module compares the time length of Tovp and Td, when the Td is longer than Tovp, the chip works normally and cannot trigger protection, and when the Td is shorter than Tovp, the chip triggers overvoltage protection logic.
The output of the driving power supply is determined by a first resistor Rovp, and the principle is as follows (the ratio K of the input and the output of the current mirror is 1 is exemplified):
Ib*Rovp/Rb=Ic1
C1*Vcs=(Ib*Rovp*Tovp)/Rb
wherein Ic1 is the charging current of the capacitor C1, and C1 is the capacity of the capacitor C1;
thereby:
Tovp=(C1*Vcs*Rb)/(Ib*Rovp)
when Tovp =td, then there is
Vout=(L*Vcs)/(Rcs*Td)=((L*Vcs)/Rcs)*((Ib*Rovp)/(C1*Vcs*Rb))
Thereby having the following characteristics
Vout=(L*Ib*Rovp)/(Rcs*C1*Rb)。
The application can set the voltage value of the output voltage Vout by setting the resistance value of the first resistor Rovp, and other parameters are all fixed parameters and are irrelevant to temperature.
The embodiment also provides a control chip, which comprises the overvoltage protection circuit.
The embodiment also provides a control chip, which comprises the control circuit.
As shown in fig. 4, the present embodiment further provides a driving power source, which includes a rectifier bridge, a capacitor E1, a resistor R1, a capacitor E2, an inductor L1, a diode D1, and the control chip.
Specifically, in this embodiment, the resistor R1 and the capacitor E1 are connected in parallel to form a filter circuit, the output end of the rectifier bridge is connected to the filter circuit, specifically, the output end of the rectifier bridge is connected to the first end of the resistor R1 and the first end of the capacitor E1, the second end of the resistor R1 and the second end of the capacitor E1 are grounded, and the filter circuit filters the voltage output by the rectifier bridge to a constant voltage. In addition, the output end of the rectifier bridge is also connected with the first end of the diode D1 and the first end of the capacitor E2, and the first end and the second end of the capacitor E2 are also respectively used as the output ends (VOUT+, VOUT-) of the driving power supply. The second end of the capacitor E2 is connected to the first end of the inductor L1, and the second end of the inductor L1 is connected to the second end of the diode D1 and the control chip. In one embodiment, the second end of the inductor L1 is connected to a control chip, specifically a drain electrode of a driving MOS in the control chip.
It should be noted that, in the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described as different from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.