CN114530118A - Display panel - Google Patents
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- CN114530118A CN114530118ACN202210158199.5ACN202210158199ACN114530118ACN 114530118 ACN114530118 ACN 114530118ACN 202210158199 ACN202210158199 ACN 202210158199ACN 114530118 ACN114530118 ACN 114530118A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Crystallography & Structural Chemistry (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
- Liquid Crystal (AREA)
Abstract
Description
Technical Field
The application relates to the technical field of display, in particular to a display panel.
Background
With the increasing demand of people for precise display, the high resolution of the display panel is also higher; the increase in resolution of the display device means an increase in the number of data lines and data driving circuits, and in order to reduce costs, data signals are generally time-divided and then sequentially applied to the data lines using a demultiplexer circuit.
However, such a capacitive coupling between adjacent data lines may cause a variation in data voltage stored in the data lines, thereby affecting pixel voltages to cause a degradation or distortion in image quality.
Disclosure of Invention
Embodiments of the present disclosure provide a display panel, which can improve the situation that the capacitive coupling between the adjacent data lines causes the data voltage stored in the data lines to change.
An embodiment of the present application provides a display panel, including:
n groups of data signal input ends, wherein each group of data signal input ends comprises two data signal input ends, each data signal input end is used for inputting signals to the pixels, and N is a natural number greater than 1;
the multi-column pixels comprise a plurality of groups of pixel groups, each group of pixel groups comprises M columns of pixels connected with the same data signal input end, and the multi-column pixels connected with the two data signal input ends of the same group of data signal input ends are arranged in a crossed manner, so that the pixels in adjacent columns are connected with different data signal input ends;
at least one data line group, wherein each data line group comprises M data lines, the ith data line in each data line group is connected with the ith row of pixels in a pixel group, and i is a natural number between 1 and M;
the time-sharing multiplexing signal input module is used for selectively connecting two data signal input ends of each group of data signal input ends with M data lines in each data line group one by one so as to enable different signal lines to receive the time-sharing multiplexing signals in a time-sharing manner, the data signal input ends input signals to the pixels in different columns in a time-sharing manner, and M is a natural number greater than 1;
and the capacitors are arranged between the adjacent data lines connected with the same data signal input end.
Optionally, the two data signal input terminals include a first data signal input terminal and a second data signal input terminal for inputting different signals;
the signal lines comprise first signal lines and second signal lines which are arranged at intervals;
the time division multiplexing signal input module further comprises: a plurality of first transistors provided on the first signal line and a plurality of second transistors provided on the second signal line;
the plurality of data lines connected to the first signal line simultaneously turn on the first data signal input terminal through the plurality of first transistors, and the plurality of data lines connected to the second signal line simultaneously turn on the second data signal input terminal through the plurality of second transistors.
Optionally, the pixel group includes a first column pixel group connected to the first data signal input terminal and a second column pixel group connected to the second data signal input terminal, the first column pixel group includes a first column of pixels and a second column of pixels, the second column pixel group includes a third column of pixels and a fourth column of pixels, and the first column of pixels, the third column of pixels, the second column of pixels and the fourth column of pixels are sequentially arranged;
the data lines comprise a first group of data lines and a second group of data lines, the first group of data lines comprise a first data line connected with the first column of pixels and a second data line connected with the second column of pixels, and the second group of data lines comprise a third data line connected with the third column of pixels and a fourth data line connected with the fourth column of pixels;
the first data line and the third data line are connected with the first transistor, the second data line and the fourth data line are connected with the second transistor, a first capacitor is arranged between the first data line and the second data line, and a second capacitor is arranged between the third data line and the fourth data line.
Optionally, a first electrode of the first transistor is connected to the first data line, a second electrode of the first transistor is connected to the first data signal input terminal, a gate of the first transistor is connected to the first signal line, and the first transistor is configured to connect or disconnect the first data line and the first data signal input terminal;
a first electrode of the second transistor is connected to the second data line, a second electrode of the second transistor is connected to the first data signal input terminal, a gate of the second transistor is connected to the second signal line, and the second transistor is used to connect or disconnect the second data line and the first data signal input terminal.
Optionally, a coupling capacitor is present between adjacent data lines connected to the same signal line;
when the first signal line is disconnected and the second signal line is connected, the first data line and the third data line are respectively disconnected from the data signal input end, the second data line and the fourth data line are respectively connected with the data signal input end, a first coupling capacitor is arranged between the first data line and the second data line, and the first capacitor at least offsets part of the first coupling capacitor.
Optionally, the data signal input end includes a first data signal input end, a second data signal input end, a third data signal input end and a fourth data signal input end;
the signal lines comprise first signal lines and second signal lines which are arranged at intervals;
the pixel group comprises a first column pixel group connected with the first data signal input end, a second column pixel group connected with the second data signal input end, a third column pixel group connected with the third data signal input end and a fourth column pixel group connected with the fourth data signal input end, wherein the first column pixel group comprises a first column pixel and a second column pixel, the second column pixel group comprises a third column pixel and a fourth column pixel, the third column pixel group comprises a fifth column pixel and a sixth column pixel, the fourth column pixel group comprises a seventh column pixel and an eighth column pixel, and the first column pixel, the third column pixel, the second column pixel, the fourth column pixel, the fifth pixel, the seventh pixel, the sixth pixel and the eighth pixel are sequentially arranged;
the data lines comprise a first group of data lines, a second group of data lines, a third group of data lines and a fourth group of data lines, wherein the first group of data lines comprises a first data line connected with the first column of pixels and a third data line connected with the third column of pixels, the second group of data lines comprises a second data line connected with the second column of pixels and a fourth data line connected with the fourth column of pixels, the third group of data lines comprises a fifth data line connected with the fifth column of pixels and a seventh data line connected with the seventh column of pixels, and the fourth group of data lines comprises a sixth data line connected with the sixth column of pixels and an eighth data line connected with the eighth column of pixels;
a first capacitor is arranged between the first data line and the third data line, a second capacitor is arranged between the second data line and the fourth data line, a third capacitor is arranged between the fifth data line and the seventh data line, and a fourth capacitor is arranged between the sixth data line and the eighth data line.
Optionally, the data signal input terminal includes a first data signal input terminal and a second data signal input terminal;
the signal lines comprise a first signal line, a second signal line and a third signal line which are arranged at intervals;
the pixel group comprises a first column of pixel group connected with the first data signal input end and a second column of pixel group connected with the second data signal input end, the first column of pixel group comprises a first column of pixels, a second column of pixels and a third column of pixels, the second column of pixel group comprises a fourth column of pixels, a fifth column of pixels and a sixth column of pixels, and the first column of pixels, the fifth column of pixels, the third column of pixels, the fourth column of pixels, the second column of pixels and the sixth column of pixels are sequentially arranged;
the data lines comprise a first group of data lines and a second group of data lines, wherein the first group of data lines comprises a first data line connected with the first column of pixels, a second data line connected with the second column of pixels and a third data line connected with the third column of pixels, and the second group of data lines comprises a fourth data line connected with the fourth column of pixels, a fifth data line connected with the fifth column of pixels and a sixth data line connected with the sixth column of pixels;
a first capacitor is arranged between the first data line and the second data line, a second capacitor is arranged between the second data line and the third data line, a third capacitor is arranged between the fourth data line and the fifth data line, and a fourth capacitor is arranged between the fifth data line and the sixth data line
Optionally, the electrical property of the coupling capacitor is opposite to the electrical property of the capacitor.
Optionally, the capacitance of the capacitor is between 1fF and 1 pF.
Optionally, the number of the signal lines is equal to the number of columns of the pixels in each pixel group.
The beneficial effect of this application lies in: the display panel provided by the embodiment of the application comprises N data signal input ends, a plurality of pixel groups, a plurality of signal lines and data lines, wherein adjacent N columns of pixels are in one group, the data lines are used for connecting the signal lines and the pixels, and the capacitance coupling generated between at least part of adjacent data lines can be offset by arranging capacitance between the data lines of two adjacent pixels in the pixel groups, so that the data voltage stored in the data lines is prevented from changing, and the problem of image quality reduction or distortion can be solved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings used in the description of the embodiments will be briefly introduced below. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
For a more complete understanding of the present application and its advantages, reference is now made to the following descriptions taken in conjunction with the accompanying drawings. Wherein like reference numerals refer to like parts in the following description.
Fig. 1 is a first schematic diagram of a driving circuit according to an embodiment of the present disclosure.
Fig. 2 is a second schematic diagram of a driving circuit according to an embodiment of the present disclosure.
Fig. 3 is a third schematic diagram of a driving circuit according to an embodiment of the present application.
Fig. 4 is a signal timing diagram of a driving circuit according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In current Active Matrix (AM) displays, including AMLCD, AMOLED, AM-MiniLED, AM-MicroLED, etc., these types of displays include a scan driver for supplying scan signals through scan lines and a data driver for supplying data signals through data lines. In order to improve the resolution of the display device, the number of data lines and data driving circuits is increased, which leads to an increase in cost. In order that the number of data driving circuits can be reduced, data signals are time-divided and then sequentially applied to data lines using a demultiplexer circuit. Such a display device may simultaneously connect one external data signal to two data lines of the display panel.
However, this technique has some disadvantages, one of which is that the charging time of each pixel is halved, and higher requirements are put on the on-state current and carrier mobility of the TFT therein, for which Oxide TFT or LTPS TFT can be used to drive the pixel; a second disadvantage is that while signals are input to adjacent data lines, Pixel TFTs corresponding to another row of data lines are not turned off, so that the data voltage stored in the floating data line is changed due to the capacitive coupling between the adjacent data lines, thereby affecting the Pixel voltage and causing degradation or distortion of the image quality. This problem is not solved by Oxide TFTs and LTPS TFTs.
Therefore, in order to solve the above problems, the present application proposes a display panel. The present application will be further described with reference to the accompanying drawings and embodiments.
Referring to fig. 1, fig. 1 is a first schematic diagram of a driving circuit according to an embodiment of the present disclosure. The embodiment of the present application provides adisplay panel 100, where thedisplay panel 100 includes N groups of data signalinput terminals 10, a plurality of columns ofpixels 40, a time-division multiplexingsignal input module 20, adata line 30, and a capacitor. Where each data signalinput 10 is for inputting a signal to a pixel, each set of data signalinputs 10 includes two data signal inputs, for example, a first data signal input D1 and a second data signal input D2, N being a natural number greater than 1. Themulti-column pixels 40 comprise a plurality of groups of pixel groups, themulti-column pixels 40 are arranged in a matrix, and the M columns of pixels connected with the same data signal input end are one pixel group, wherein each group of pixel groups comprises the M columns ofpixels 40 connected with the same data signal input end, and the multi-column pixels connected with the two data signal input ends of the same group of data signal input ends are arranged in a crossed manner, so that the pixels of adjacent columns are connected with the different data signal input ends in the pixel groups. I.e. the pixels of the first data signalinput 10 are arranged across the pixels of the group of pixels to which the second data signal input is connected, so that adjacent pixels are connected to different data signal inputs. The time-division multiplexingsignal input module 20 includes M signal lines for inputting time-division multiplexing signals, and different signal lines receive the time-division multiplexing signals in a time-division manner, so that the data signalinput terminal 10 inputs signals to pixels in different columns in a time-division manner, where the time-division multiplexingsignal input module 20 is configured to selectively connect two data signal input terminals of each group of data signal input terminals with the M data lines in each data line group one by one, so that the different signal lines receive the time-division multiplexing signals in a time-division manner, and the data signal input terminals input signals to the pixels in different columns in a time-division manner. For example, M signal lines are connected to M columns of pixels in each pixel group one by one, and M is a natural number greater than 1. The data line group comprises M data lines, the ith data line in each data line group is connected with the ith column of pixels in a pixel group, i is a natural number between 1 and M, one end of eachdata line 30 is connected with the ith signal line, the other end of eachdata line 30 is used for connecting the ith column of pixels in a pixel group, and i is a natural number between 1 and M. The capacitor is arranged between adjacent data lines connected with the same data signal input end. By providing a capacitor between twoadjacent data lines 30 connected to the same data signal input terminal, the capacitive coupling generated between theadjacent data lines 30 can be cancelled, thereby preventing the data voltage stored in the data lines 30 from being changed, and further solving the problem of image quality degradation or distortion.
It should be noted that, a coupling capacitor exists between theadjacent data lines 30 connected to the same signal line, and the electrical property of the coupling capacitor is opposite to the electrical property of the capacitor, in some embodiments, the capacitance of the coupling capacitor is the same as the capacitance of the capacitor, so that the capacitor can completely cancel the coupling capacitor, cancel the pulling of the coupling capacitor on the voltage of thepixel 40, and avoid the voltage change in the data lines 30, thereby maintaining the voltage of thepixel 40 at the predetermined voltage value, and ensuring the image quality.
In some embodiments, the capacitance of the capacitor is between 1fF and 1 pF. It is understood that the specific value of the capacitance of the capacitor is set according to the actual situation, and is not limited to the specific value, so long as the capacitor can at least partially cancel out the coupling capacitor.
Each set ofdata lines 30 includes an equal number of data lines 30. Each group ofdata lines 30 includes a plurality ofdata lines 30 arranged at intervals, and the number of the data lines 30 arranged at intervals between the data lines 30 is equal.
In some embodiments, the number of signal lines in thedisplay panel 100 is the same as the number of data signalinput terminals 10, and the number of data signalinput terminals 10 is the same as the number of groups of pixel groups. Referring to fig. 1, the data signalinput terminal 10 includes a first data signal input terminal D1 and a second data signal input terminal D2. The pixel group includes a first column pixel group connected to the first data signal input terminal D1 and a second column pixel group connected to the second data signal input terminal D2, the first column pixel group includes a first column ofpixels 410 and a second column ofpixels 420, the second column pixel group includes a third column ofpixels 430 and a fourth column ofpixels 440, wherein the first column ofpixels 410, the third column ofpixels 430, the second column ofpixels 420 and the fourth column ofpixels 440 are sequentially arranged.
The data lines 30 include a first group of data lines including afirst data line 310 connected to a first column ofpixels 410 and asecond data line 320 connected to a second column ofpixels 420. The second group of data lines includes athird data line 330 connected to a third column ofpixels 430 and afourth data line 340 connected to a fourth column ofpixels 440, thefirst data line 310 and thesecond data line 320 are connected to thefirst transistor 230, thethird data line 330 and thefourth data line 340 are connected to thesecond transistor 240, a first capacitor C (1) is disposed between the first column ofpixels 410 and the second column ofpixels 420, and a second capacitor C (2) is disposed between the third column ofpixels 430 and the fourth column ofpixels 440.
The signal lines include afirst signal line 210 and asecond signal line 220 which are arranged at intervals, the time division multiplexingsignal input module 20 further includes a plurality offirst transistors 230 and a plurality ofsecond transistors 240, the plurality offirst transistors 230 are arranged on thefirst signal line 210, and the plurality ofsecond transistors 240 are arranged on thesecond signal line 220. A first electrode of thefirst transistor 230 is connected to thefirst data line 310, a second electrode of thefirst transistor 230 is connected to the first data signal input terminal D1, a gate of thefirst transistor 230 is connected to thefirst signal line 210, and thefirst transistor 230 is used to connect or disconnect thefirst data line 310 and the first data signal input terminal D1. A first electrode of thesecond transistor 240 is connected to thethird data line 330, a second electrode of thesecond transistor 240 is connected to the first data signal input terminal D1, a gate of thesecond transistor 240 is connected to thesecond signal line 220, and thesecond transistor 240 is used to connect or disconnect thethird data line 330 and the first data signal input terminal D1.
Wherein, the plurality ofdata lines 30 connected to thefirst signal line 210 simultaneously turn on the first data signal input terminal D1 through the plurality offirst transistors 230; the plurality ofdata lines 30 connected to thesecond signal line 220 simultaneously turn on the second data signal input terminal D2 through the plurality ofsecond transistors 240. That is, thepixels 40 connected to thefirst transistor 230 in the pixels in the plurality of columns are not simultaneously turned on with thepixels 40 connected to thesecond transistor 240, and thepixels 40 connected to thefirst transistor 230 in one pixel group are simultaneously turned on with the pixels connected to thefirst transistor 230 in the adjacent pixel group. So that thepixels 40 arranged in the array are turned on at intervals, and the data signals can be applied todifferent data lines 30 in a time-sharing manner, thereby saving the cost.
When thefirst signal line 210 is disconnected and thesecond signal line 220 is turned on, thefirst data line 310 connected to the first column ofpixels 410 and thethird data line 330 connected to the third column ofpixels 430 are respectively disconnected from the data signalinput terminal 10, thesecond data line 320 connected to the second column ofpixels 420 and thefourth data line 340 connected to the fourth column ofpixels 440 are respectively turned on from the data signalinput terminal 10, a first coupling capacitance exists between thesecond data line 320 and thefirst data line 310, and the first capacitance C (1) at least partially cancels the first coupling capacitance.
When thesecond signal line 220 is disconnected and thefirst signal line 210 is turned on, thesecond data line 320 connected to the second column ofpixels 420 and thefourth data line 340 connected to the fourth column ofpixels 440 are respectively disconnected from the data signalinput terminal 10, thefirst data line 310 connected to the first column ofpixels 410 and thethird data line 330 connected to the third column ofpixels 430 are respectively turned on from the data signalinput terminal 10, a second coupling capacitance exists between thethird data line 330 and thefourth data line 340, and the second capacitance C (2) at least partially cancels the second coupling capacitance.
In some other embodiments, the number of signal lines in thedisplay panel 100 is different from the number of the data signalinput terminals 10, and the number of signal lines in thedisplay panel 100 is smaller than the number of the data signalinput terminals 10. Referring to fig. 2, fig. 2 is a second schematic view of a display panel according to an embodiment of the present disclosure. The data signalinput terminal 10 includes a first data signal input terminal D1, a second data signal input terminal D2, a third data signal input terminal D3 and a fourth data signal input terminal D4. The pixel group includes a first column pixel group connected to the first data signal input terminal D1, a second column pixel group connected to the second data signal input terminal D2, a third column pixel group connected to the third data signal input terminal D3, and a fourth column pixel group connected to the fourth data signal input terminal D4, wherein the first column pixel group includes thefirst column pixel 410 and thesecond column pixel 420. The second column pixel group includes athird column pixel 430 and afourth column pixel 440. The third column pixel group includes afifth pixel 450 and asixth pixel 460. The fourth column pixel group includes aseventh pixel 470 and aneighth pixel 480.
The signal lines include afirst signal line 210 and asecond signal line 220 which are arranged at intervals, the time division multiplexingsignal input module 20 further includes a plurality offirst transistors 230 and a plurality ofsecond transistors 240, the plurality offirst transistors 230 are arranged on thefirst signal line 210, and the plurality ofsecond transistors 240 are arranged on thesecond signal line 220.
The data lines 30 include a first group of data lines including afirst data line 310 connected to the first column ofpixels 410 and athird data line 330 connected to thethird pixel 430, a second group of data lines, a third group of data lines, and a fourth group of data lines. The second group of data lines includes asecond data line 320 connected to the second column ofpixels 420 and afourth data line 340 connected to the fourth column ofpixels 440. The third group of data lines includes afifth data line 350 connected to the fifth column ofpixels 450 and aseventh data line 370 connected to the seventh column ofpixels 470. The fourth set of data lines includes asixth data line 360 connected to the sixth column ofpixels 460 and aneighth data line 380 connected to the eighth column ofpixels 480. The first, third, fifth andseventh data lines first signal line 210, and the second, fourth, sixth andeighth data lines second signal line 220.
A first capacitor C (1) is disposed between thefirst data line 310 and thethird data line 330, a second capacitor C (2) is disposed between thesecond data line 320 and thefourth data line 340, a third capacitor C (3) is disposed between thethird data line 330 and thefifth data line 350, and a fourth capacitor C (4) is disposed between thesixth data line 360 and theeighth data line 380.
In other embodiments, the number of signal lines is equal to the number ofpixels 40 in each pixel group. Referring to fig. 3, fig. 3 is a third schematic view of a display panel according to an embodiment of the present disclosure. The data signalinput terminal 10 includes a first data signal input terminal D1 and a second data signal input terminal D2.
The pixel group comprises a first column pixel group connected with a first data signal input end and a second column pixel group connected with a second data signal input end, the first column pixel group comprises afirst column pixel 410, asecond column pixel 420 and athird column pixel 430, the second column pixel group comprises afourth column pixel 440, afifth column pixel 450 and asixth column pixel 460, and thefirst column pixel 410, thefifth column pixel 450, thethird column pixel 430, thefourth column pixel 440, thesecond column pixel 420 and thesixth column pixel 460 are sequentially arranged. The signal lines include afirst signal line 210, asecond signal line 220, and athird signal line 250 that are arranged at intervals, the time-division multiplexingsignal input module 20 further includes a plurality offirst transistors 230, a plurality ofsecond transistors 240, and a plurality ofthird transistors 260, the plurality offirst transistors 230 are arranged on thefirst signal line 210, the plurality ofsecond transistors 240 are arranged on thesecond signal line 220, and the plurality ofthird transistors 260 are arranged on thethird signal line 250.
The data lines 30 include a first group of data lines including afirst data line 310 connected to the first column ofpixels 410, asecond data line 320 connected to the second column ofpixels 420, and athird data line 330 connected to thethird pixel 430. The second group of data lines includes afourth data line 340 connected to the fourth column ofpixels 440, afifth data line 350 connected to thefifth pixel 450, and asixth data line 360 connected to thesixth pixel 460. The first andfourth data lines first signal line 210, the second andfifth data lines second signal line 220, and the third andsixth data lines third signal line 250.
A first capacitor C (1) is disposed between thefirst data line 310 and thesecond data line 320, a second capacitor C (2) is disposed between thesecond data line 320 and thethird data line 330, a third capacitor C (3) is disposed between thefourth data line 340 and thefifth data line 350, and a fourth capacitor C (4) is disposed between thefifth data line 350 and thesixth data line 360.
It is understood that in some other embodiments, the first, second, third, fourth, fifth and sixth columns ofpixels pixels 410, the fourth column ofpixels 440, the second column ofpixels 420, the fifth column ofpixels 450, the third column ofpixels 430 and the sixth column ofpixels 460 are arranged in sequence. The specific arrangement is set according to actual conditions, and is not particularly limited herein.
Referring to fig. 4, fig. 4 is a signal timing diagram of a display panel according to an embodiment of the disclosure. It can be seen from the figure that P is detailed in the ideal case without considering the capacitive coupling1(N, 2-1) at t0When thefirst signal line 210 is turned on, the second data signal input terminal D2 inputs a signal to thepixel 40 at point P (N, 2-1), at t1When thefirst signal line 210 is disconnected, the second data signal input terminal D2 is disconnected from D (2-1), and the voltage D (1-2) is maintained; at t2When the ground line G (N) is closed, the transistor is closed, the P (N, 2-1) signal is disconnected with the D (2-1), and the voltage is always kept unchanged.
However, in practice,adjacent data lines 30 are capacitively coupled. For details see P2(N, 2-1) at t1At this time, thefirst signal line 210 is turned off,d (1-2) and D (2) are disconnected, the voltage of D (1-2) is unchanged, but D (2-1) is changed due to the fact that thesecond signal line 220 is opened to be connected into D (1), the voltage of D (2-1) is influenced through capacitive coupling betweenadjacent data lines 30, G (N) is started at the moment, and therefore the voltage of P (N, 2-1) is influenced, and at t2G (N) is turned off, and P (N, 2-1) maintains the voltage unchanged, and the voltage is different from the preset voltage, so that deviation is generated.
In the present proposal, by adding the capacitor C (2), the interlaced data lines 30D (2-2) and D (2-1) can also generate coupling at t1, and because D (1-2) and D (2-2) are respectively in the positive frame and the negative frame at t1, the pulling of the capacitive coupling on the D (2-1) voltage is in opposite directions, and the two are offset, the influence on the D (2-1) voltage can be greatly reduced, so that the influence on the P (N, 2-1) voltage is reduced, and the P (N, 2-1) voltage is closer to the ideal preset state.
In some embodiments, a potential control module is disposed between the transistors of each group ofdata lines 30 and the time division multiplexing signal output terminal.
The display panel provided in the embodiments of the present application is described in detail above. The principles and implementations of the present application are described herein using specific examples, which are presented only to aid in understanding the present application. Meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. A display panel, comprising:
n groups of data signal input ends, wherein each group of data signal input ends comprises two data signal input ends, each data signal input end is used for inputting signals to the pixels, and N is a natural number greater than 1;
the multi-column pixels comprise a plurality of groups of pixel groups, each group of pixel groups comprises M columns of pixels connected with the same data signal input end, and the multi-column pixels connected with the two data signal input ends of the same group of data signal input ends are arranged in a crossed manner, so that the pixels in adjacent columns are connected with different data signal input ends;
at least one data line group, wherein each data line group comprises M data lines, the ith data line in each data line group is connected with the ith row of pixels in a pixel group, and i is a natural number between 1 and M;
the time-sharing multiplexing signal input module is used for selectively connecting two data signal input ends of each group of data signal input ends with M data lines in each data line group one by one so as to enable different signal lines to receive the time-sharing multiplexing signals in a time-sharing manner, the data signal input ends input signals to the pixels in different columns in a time-sharing manner, and M is a natural number greater than 1;
and the capacitors are arranged between the adjacent data lines connected with the same data signal input end.
2. The display panel according to claim 1,
the two data signal input ends comprise a first data signal input end and a second data signal input end for inputting different signals;
the signal lines comprise first signal lines and second signal lines which are arranged at intervals;
the time division multiplexing signal input module further comprises: a plurality of first transistors provided on the first signal line and a plurality of second transistors provided on the second signal line;
the plurality of data lines connected to the first signal line simultaneously turn on the first data signal input terminal through the plurality of first transistors, and the plurality of data lines connected to the second signal line simultaneously turn on the second data signal input terminal through the plurality of second transistors.
3. The display panel according to claim 2, wherein the pixel group comprises a first column pixel group connected to the first data signal input terminal and a second column pixel group connected to the second data signal input terminal, the first column pixel group comprises a first column of pixels and a second column of pixels, the second column pixel group comprises a third column of pixels and a fourth column of pixels, and the first column of pixels, the third column of pixels, the second column of pixels and the fourth column of pixels are arranged in sequence;
the data lines comprise a first group of data lines and a second group of data lines, the first group of data lines comprise a first data line connected with the first column of pixels and a second data line connected with the second column of pixels, and the second group of data lines comprise a third data line connected with the third column of pixels and a fourth data line connected with the fourth column of pixels;
the first data line and the third data line are connected with the first transistor, the second data line and the fourth data line are connected with the second transistor, a first capacitor is arranged between the first data line and the second data line, and a second capacitor is arranged between the third data line and the fourth data line.
4. The display panel according to claim 3,
a first electrode of the first transistor is connected with the first data line, a second electrode of the first transistor is connected with the first data signal input end, a grid electrode of the first transistor is connected with the first signal line, and the first transistor is used for connecting or disconnecting the first data line and the first data signal input end;
a first electrode of the second transistor is connected to the second data line, a second electrode of the second transistor is connected to the first data signal input terminal, a gate of the second transistor is connected to the second signal line, and the second transistor is used to connect or disconnect the second data line and the first data signal input terminal.
5. The display panel according to claim 4, wherein a coupling capacitance exists between the adjacent data lines connected to the same signal line;
when the first signal line is disconnected and the second signal line is connected, the first data line and the third data line are respectively disconnected from the data signal input end, the second data line and the fourth data line are respectively connected with the data signal input end, a first coupling capacitor is arranged between the first data line and the second data line, and the first capacitor at least offsets part of the first coupling capacitor.
6. The display panel of claim 1, wherein the data signal input comprises a first data signal input, a second data signal input, a third data signal input, and a fourth data signal input;
the signal lines comprise first signal lines and second signal lines which are arranged at intervals;
the pixel group comprises a first column pixel group connected with the first data signal input end, a second column pixel group connected with the second data signal input end, a third column pixel group connected with the third data signal input end and a fourth column pixel group connected with the fourth data signal input end, wherein the first column pixel group comprises a first column pixel and a second column pixel, the second column pixel group comprises a third column pixel and a fourth column pixel, the third column pixel group comprises a fifth column pixel and a sixth column pixel, the fourth column pixel group comprises a seventh column pixel and an eighth column pixel, and the first column pixel, the third column pixel, the second column pixel, the fourth column pixel, the fifth pixel, the seventh pixel, the sixth pixel and the eighth pixel are sequentially arranged;
the data lines comprise a first group of data lines, a second group of data lines, a third group of data lines and a fourth group of data lines, wherein the first group of data lines comprises a first data line connected with the first column of pixels and a third data line connected with the third column of pixels, the second group of data lines comprises a second data line connected with the second column of pixels and a fourth data line connected with the fourth column of pixels, the third group of data lines comprises a fifth data line connected with the fifth column of pixels and a seventh data line connected with the seventh column of pixels, and the fourth group of data lines comprises a sixth data line connected with the sixth column of pixels and an eighth data line connected with the eighth column of pixels;
a first capacitor is arranged between the first data line and the third data line, a second capacitor is arranged between the second data line and the fourth data line, a third capacitor is arranged between the fifth data line and the seventh data line, and a fourth capacitor is arranged between the sixth data line and the eighth data line.
7. The display panel according to claim 1,
the data signal input terminals comprise a first data signal input terminal and a second data signal input terminal;
the signal lines comprise a first signal line, a second signal line and a third signal line which are arranged at intervals;
the pixel group comprises a first column of pixel group connected with the first data signal input end and a second column of pixel group connected with the second data signal input end, the first column of pixel group comprises a first column of pixels, a second column of pixels and a third column of pixels, the second column of pixel group comprises a fourth column of pixels, a fifth column of pixels and a sixth column of pixels, and the first column of pixels, the fifth column of pixels, the third column of pixels, the fourth column of pixels, the second column of pixels and the sixth column of pixels are sequentially arranged;
the data lines comprise a first group of data lines and a second group of data lines, wherein the first group of data lines comprises a first data line connected with the first column of pixels, a second data line connected with the second column of pixels and a third data line connected with the third column of pixels, and the second group of data lines comprises a fourth data line connected with the fourth column of pixels, a fifth data line connected with the fifth column of pixels and a sixth data line connected with the sixth column of pixels;
a first capacitor is arranged between the first data line and the second data line, a second capacitor is arranged between the second data line and the third data line, a third capacitor is arranged between the fourth data line and the fifth data line, and a fourth capacitor is arranged between the fifth data line and the sixth data line.
8. The display panel according to claim 6, wherein the coupling capacitor has an opposite electrical property from the capacitor.
9. The display panel according to claim 1,
the capacitance of the capacitor is between 1fF and 1 pF.
10. The display panel according to claim 1, wherein the number of the signal lines is equal to the number of columns of the pixels in each of the pixel groups.
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