CN114519320B - Lookup table circuit and configuration method thereof - Google Patents

Abstract

Translated fromChinese

本发明的实施例提供一种查找表电路及其配置方法。该查找表电路包括二个第一地址输入端口、第二至第n+1地址输入端口、进位输入端口、进位输出端口、第一输出端口和第二输出端口、六个多路选择器、二个n输入查找表和二个加法器等。通过分别控制多路选择器的输出，该查找表电路可以选择性地应用为二个n输入查找表、一个n+1输入查找表、二位宽的算术进位逻辑模块以及一位宽的算术进位逻辑模块中的一者。

An embodiment of the present invention provides a lookup table circuit and a configuration method thereof. The lookup table circuit includes two first address input ports, second to n+1th address input ports, a carry input port, a carry output port, a first output port and a second output port, six multiplexers, two n-input lookup tables and two adders. By controlling the outputs of the multiplexers respectively, the lookup table circuit can be selectively applied as one of two n-input lookup tables, one n+1-input lookup table, a two-bit wide arithmetic carry logic module and a one-bit wide arithmetic carry logic module.

Description

Lookup table circuit and configuration method thereof

Technical Field

The present invention relates to the field of integrated circuits, and in particular, to a lookup table circuit and a configuration method thereof.

Background

Programmable logic devices include field programmable gate arrays (Field Programmable GATE ARRAY, FPGA) and complex programmable logic devices (Complex Programmable Logic Device, CPLD), among others. The programmable logic device includes Look-Up Table (LUT) circuitry, which can implement combinational logic for any n variables through an n-input Look-Up Table.

The lookup table circuit may include two n-input lookup tables and a selector, the two input terminals of the selector are respectively connected to the two output terminals of the two n-input lookup tables, the control terminal is connected to the most significant address port, and the selector may selectively output a signal received by one of the two input terminals based on a signal received by the control terminal, thereby implementing an n+1-input lookup table.

As shown IN fig. 1, the lookup table circuit 100 includes a first five-input lookup table LUT (5) -a, a second five-input lookup table LUT (5) -B, and a selector MUX, wherein input ends of the first five-input lookup table LUT (5) -a and the second five-input lookup table LUT (5) -B are commonly connected to five address input ports IN (1) -IN (5), output ends are respectively connected to first and second input ends of the selector MUX, a control end of the selector MUX is connected to a sixth address input port IN (6), an output end is connected to a second output port OUT6, and an output end of the first five-input lookup table LUT (5) -a is connected to the first output port OUT5. When the selector MUX receives the most significant address signal from the sixth bit address input port through its control terminal, it may output a signal received by one of the first terminal and the second terminal.

Disclosure of Invention

The technical problem solved by the invention is that a circuit comprising two n-input lookup tables needs to be improved to be applied to various scenes and the like.

To solve the above technical problem, an embodiment of the present invention provides a lookup table circuit, including: two first address input ports, second to n+1th address input ports, a carry input port, a carry output port, a first output port and a second output port, wherein n is an integer greater than or equal to 5; a first n-input lookup table and a second n-input lookup table sharing second to nth address input ports, the first n-input lookup table using one of the two first address input ports alone, the second n-input lookup table using the other of the two first address input ports alone; three input ends of the first multiplexer are respectively connected with one of two first address input ports, a power supply voltage and ground; the three input ends of the second multiplexer are respectively connected with the other of the two first address input ports, the power supply voltage and the ground; the first input end of the third multiplexer is connected with the output end of the first n-input lookup table, the second input end of the third multiplexer is connected with the output end of the second n-input lookup table, and the control end of the third multiplexer is connected with the n+1th address input port; the first input end of the fourth multiplexer is connected with the output end of the third multiplexer, and the output end is connected with the second output port; the first input end of the fifth multiplexer is connected with the output end of the first n-input lookup table, and the output end is connected with the first output port; the first input end of the sixth multiplexer is connected with the power supply voltage, and the second input end of the sixth multiplexer is connected with the output end of the first n-input lookup table; the first input end of the first adder is connected with a carry input port, the second input end of the first adder is connected with the output end of the first multiplexer, the third input end of the first adder is connected with the output end of the sixth multiplexer, and the first output end of the first adder is connected with the second input end of the fifth multiplexer; the first input end of the second adder is connected with the second output end of the first adder, the second input end is connected with the output end of the second multiplexer, the third input end is connected with the output end of the second n-input lookup table, the first output end is connected with the second input end of the fourth multiplexer, and the second output end is connected with the carry output port.

Optionally, the fourth multiplexer has a control terminal comprising a first static memory connected to the control terminal of the fourth multiplexer, which is adapted to be configured to a first value or a second value, the fourth multiplexer being adapted to output a signal received at its first input terminal based on the first value and to output a signal received at its second input terminal based on the second value.

Optionally, the n+1th address input port is adapted to receive a high level signal or a highest order address signal, and the third multiplexer is adapted to output a signal received at its second input terminal based on the high level signal and to output a signal received at one of its first input terminal and second input terminal based on the highest order address signal.

Optionally, the second adder is adapted to receive the carry input signal, the carry generation signal and the carry propagation signal, respectively, and to derive a sum output signal and a carry output signal based thereon, the first output of the second adder being adapted to output the sum output signal, and the second output of the second adder being adapted to output the carry output signal.

Optionally, the other of the two first address input ports is adapted to input a first addend a_i, one of the second to nth address input ports is adapted to input a second addend B_i, the second n-input look-up table is adapted to derive a carry propagate signal based on the first addend a_i and the second addend B_i and output the carry propagate signal to a third input of the second adder, and the second multiplexer is adapted to output a carry generate signal corresponding to the carry propagate signal to a second input of the second adder.

Optionally, the carry input port is adapted to output a carry input signal, the first multiplexer is adapted to select its first input to ground and output a low level signal, the sixth multiplexer is adapted to select its first input and output a high level signal, and the first adder is adapted to output the carry input signal to the first input of the second adder via its second output based on the carry input signal, the low level signal and the high level signal.

Optionally, the fifth multiplexer is adapted to select its first input to output the output signal of the first n-input look-up table.

Optionally, the second adder is adapted to receive the first carry output signal, the second carry generation signal and the second carry propagation signal, and to derive a second sum output signal and a second carry output signal based thereon, the first output of the second adder being adapted to output the second sum output signal, and the second output of the second adder being adapted to output the second carry output signal.

Optionally, the other of the two first address input ports is adapted to input a high-order first addend a_i+1, the other of the second to nth address input ports is adapted to input a high-order second addend B_i+1, the second n-input lookup table is adapted to obtain a second carry propagation signal based on the high-order first addend a_i+1 and the second addend B_i+1 and output the second carry propagation signal to the third input of the second adder, and the second multiplexer is adapted to output a second carry generation signal corresponding to the second carry propagation signal to the second input of the second adder.

Optionally, the carry input port is adapted to output a carry input signal, the sixth multiplexer is adapted to select the second input terminal thereof to output a first carry propagate signal, the first multiplexer is adapted to output a first carry generate signal corresponding to the first carry propagate signal, the first adder is adapted to derive a first sum output signal and a first carry output signal based on the carry input signal, the first carry generate signal and the first carry propagate signal, the first output terminal of the first adder is adapted to output the first sum output signal, and the second output terminal of the second adder is adapted to output the first carry output signal to the first input terminal of the second adder.

Optionally, one of the two first address input ports is adapted to input a low order first addend a_i, one of the second to nth address input ports is adapted to input a low order second addend B_i, the first n-input look-up table is adapted to obtain a first carry propagate signal based on the low order first addend a_i and the second addend B_i and output the first carry propagate signal to the second input of the sixth multiplexer, and the first multiplexer is adapted to output a first carry generate signal corresponding to the first carry propagate signal to the second input of the first adder.

Optionally, the fifth multiplexer and the sixth multiplexer each have a control terminal, comprising a second static memory connected to the control terminals of each of the fifth multiplexer and the sixth multiplexer, which is adapted to be configured to a first value or a second value, the fifth multiplexer being adapted to output a signal received at its first input terminal based on the first value and to output a signal received at its second input terminal based on the second value, the sixth multiplexer being adapted to output a signal received at its first input terminal based on the first value and to output a signal received at its second input terminal based on the second value.

Alternatively, the first value is one of 0 or 1 and the second value is the other of 0 or 1.

Optionally, the look-up table circuit comprises a third static memory, and the first multiplexer is adapted to output the corresponding carry generation signal based on a configuration of the third static memory.

Optionally, the look-up table circuit comprises a fourth static memory, and the second multiplexer is adapted to output a corresponding carry generation signal based on a configuration of the fourth static memory.

The embodiment of the invention also provides a method for configuring the lookup table circuit, which comprises the following steps: outputting the second value to a sixth multiplexer; a sixth multiplexer outputting the first carry propagate signal to the first adder based on the second value; the first adder receives the carry input signal, the first carry generation signal, and the first carry propagation signal and generates a first carry output signal and a first sum output signal based thereon; the second adder receives the first carry output signal, the second carry generation signal, and the second carry propagation signal and generates a second carry output signal and a second sum output signal based thereon; the second adder provides a second carry output signal to the carry output port; the first adder and the second adder respectively provide the first and second output signals to the fifth multiplexer and the fourth multiplexer; outputting respective second values to the fourth multiplexer and the fifth multiplexer, respectively; the fourth multiplexer and the fifth multiplexer output the second sum output signal and the first sum output signal to the second output port and the first output port, respectively, based on the respective received second values.

Optionally, the method comprises: outputting the first value to a sixth multiplexer; the sixth multiplexer outputs a high level signal to the first adder based on the first value; the first adder receives a carry input signal, a low level signal, and a high level signal, and outputs a carry input signal based thereon; the second adder receives the carry input signal, the carry generation signal, and the carry propagation signal and generates a carry output signal sum and output signal based thereon; the second adder provides a carry output signal to the carry output port and a sum output signal to the fourth multiplexer; outputting the second value to a fourth multiplexer; the fourth multiplexer outputs and outputs a signal based on the second value it receives and outputs a signal to the second output port.

Optionally, the method comprises: outputting the first value to a fifth multiplexer; the fifth multiplexer outputs the output signal of the first n-input look-up table to the first output port based on the first value.

Optionally, the method comprises: outputting the first value to a fourth multiplexer; the fourth multiplexer outputs the signal received at its first input to the second output port based on the first value.

Optionally, the method comprises: the high level signal is provided to the control end of the third multiplexer through the n+1th address input port; the third multiplexer selects the second input terminal thereof based on the high level signal and outputs the output signal of the second n-input lookup table to the first input terminal of the fourth multiplexer.

Optionally, the method comprises: the highest address signal is provided to the control end of the third multiplexer through the n+1th address input port; the third multiplexer outputs a signal received by one of its first input terminal and second input terminal to the first input terminal of the fourth multiplexer based on the most significant address signal.

Compared with the prior art, the technical scheme of the embodiment of the invention has the beneficial effects. For example, the lookup table circuit provided by the embodiment of the invention comprises two n-input lookup tables, six multiplexers, two adders and a plurality of input ports, and can be selectively applied to one of two n-input lookup tables, one n+1-input lookup table, a two-bit-wide arithmetic carry logic module and a one-bit-wide arithmetic carry logic module by respectively controlling the outputs of the multiplexers.

For another example, the lookup table circuit provided by the embodiment of the invention not only improves the high efficiency and flexibility of the arithmetic carry logic, but also improves the resource utilization rate of the lookup table by embedding the arithmetic carry logic which can be configured to be two-bit wide or one-bit wide.

For another example, in the lookup table circuit provided by the embodiment of the invention, the first adder and the second adder respectively realizing low-order and high-order operations respectively multiplex one address input port and the other address input port of the two n-input lookup tables, without additionally increasing the input ports of the lookup table circuit, thereby saving the port resources of the lookup table circuit.

For another example, when the lookup table circuit provided by the embodiment of the invention realizes the binary-width arithmetic carry logic, the two output ports and the output signal of the lookup table can be multiplexed with the first output port and the second output port of the lookup table respectively, and under the same lookup table resource, although the length of the arithmetic carry logic is doubled, the number of the output ports is not increased, and the influence of the increase of the length of the arithmetic carry logic on the number of the output ports is reduced to the greatest extent.

For another example, when the lookup table circuit provided by the embodiment of the invention realizes arithmetic carry logic with one bit width, the first n-input lookup table can be independently used, and when the first n-input lookup table is independently used, the newly added and independently used address input port can increase the flexibility of realizing logic functions of the n-input lookup table.

For another example, when the lookup table circuit provided by the embodiment of the invention realizes the arithmetic carry logic with two bit widths or one bit width, the output of the lookup table circuit can be freely selected to be registered and output or directly output, so that the number of output ports can be effectively ensured not to be increased under the same lookup table resource.

Drawings

FIG. 1 is a schematic diagram of a six-output lookup table implemented by two five-input lookup tables according to the prior art;

FIG. 2 is a schematic diagram of a lookup table circuit including two n-input lookup tables in an embodiment of the invention;

FIG. 3 is a schematic diagram of a portion of the logic of a look-up table circuit in which a first adder is illustrated and a first multiplexer is not illustrated in an embodiment of the present invention;

FIG. 4 is a schematic diagram of a look-up table circuit including two five-input look-up tables in an embodiment of the invention;

FIG. 5 is a first flowchart of a method of configuring a lookup table circuit in an embodiment of the invention;

fig. 6 is a second flowchart of a method of configuring a look-up table circuit in an embodiment of the invention.

Detailed Description

In an embodiment of the present invention, the adder may add one addend and another addend of its ith bit according to the following formula,

And (3) making:

G_i＝A_i*B_i (3)

Then:

C_i+1＝G_i+P_i*C_i (5)

Wherein A_i is one addend of the ith bit, B_i is the other addend of the ith bit, C_i is the carry input signal of the ith bit, S_i is the sum of the addition of the ith bit, G_i is the carry generation signal of the ith bit, P_i is the carry propagation signal of the ith bit, C_i+1 is the carry output signal of the ith bit, i.e. the carry input signal of the (i+1) th bit, and i is an integer greater than or equal to 1.

A one-bit wide arithmetic carry logic block may be implemented by two look-up tables, for example, the existing look-up table circuit structure shown in fig. 1 may be changed to a one-bit wide arithmetic carry logic block. Specifically, one addend a_i and the other addend B_i are transferred from two of the five address input ports IN (1) -IN (5) to the first five input look-up table LUT (5) -a, which generates a carry generation signal G_i and outputs to the first output port OUT5; one addend a_i and the other addend B_i are transferred from two of the five address input ports IN (1) -IN (5) to a second five input look-up table LUT (5) -B which generates a carry propagate signal P_i which is output via a selector MUX to a second output port OUT6.

In an embodiment of the present invention, the lookup table circuit includes two n-input lookup tables, six multiplexers, two adders, and a plurality of input ports, and the lookup table circuit can be selectively applied as one of two n-input lookup tables, one n+1-input lookup table, a two-bit-wide arithmetic carry logic module, and a one-bit-wide arithmetic carry logic module by controlling outputs of the multiplexers, respectively.

In embodiments of the present invention, the look-up table circuitry may be implemented as an arithmetic carry logic block, thereby reducing the reliance of small scale operations on Digital Signal Processing (DSP) resources.

In embodiments of the present invention, the look-up table circuit may be implemented as an arithmetic carry logic block and may perform a bit-wide or one-bit-wide carry operation.

Compared with an arithmetic carry logic module with one bit width realized by two lookup tables, the lookup table circuit provided by the embodiment of the invention can realize carry operation with two bits width based on the same number of lookup tables, thereby not only having more efficient arithmetic carry logic function, but also improving the utilization rate of the lookup tables.

In the embodiment of the invention, the first adder and the second adder which respectively realize low-order and high-order operations in the lookup table circuit respectively multiplex one address input port and the other address input port of the two n-input lookup tables without additionally increasing the input ports of the lookup table circuit, thereby saving the port resources of the lookup table circuit.

In the embodiment of the invention, the lookup table circuit outputs the second carry output signal through the existing port output signal, for example, outputs the second carry output signal through the carry output port, outputs the first and output signals through the first output port and outputs the second and output signals through the second output port, so that two-bit wide carry operation is realized, and the signals can be selectively output to a register or other calculation modules without additionally increasing the output port of the lookup table circuit, thereby saving the port resources of the lookup table circuit.

In the embodiment of the invention, the lookup table circuit can also realize one-bit-width carry operation, and when the one-bit-width carry operation is realized, the first n-input lookup table can be independently used, and when the first n-input lookup table is independently used, the newly added and independently used address input port can increase the flexibility of the n-input lookup table to realize logic functions.

In order to make the above objects, features and advantages of the embodiments of the present invention more comprehensible, the following detailed description of specific embodiments of the present invention with reference to the accompanying drawings is provided.

Fig. 2 is a schematic diagram of a lookup table circuit including two n-input lookup tables in an embodiment of the invention.

As shown IN fig. 2, the lookup table circuit 200 includes two first address input ports IN (1A) and IN (1B), second to n+1th address input ports IN (2), … …, IN (n), IN (n+1), a carry input port CIN, a carry output port COUT, a first output port OUT1, and a second output port OUT2, wherein the first address input port has two, the second to n+1th address input ports have one, respectively, and n is an integer greater than or equal to 5.

The lookup table circuit 200 further includes first to sixth multiplexers MUX1, MUX2, MUX3, MUX4, MUX5, and MUX6, first and second n-input lookup table LUTs (n) -1 and LUT (n) -2, and first and second adders adder [0] and adder [1].

The first n-input lookup table LUT (n) -1 and the second n-input lookup table LUT (n) -2 both share the second to n-th address input ports IN (2), … …, IN (n), the first n-input lookup table LUT (n) -1 solely uses one IN (1A) of the two first address input ports IN (1A) and IN (1B) as its address input port, and the second n-input lookup table LUT (n) -2 solely uses the other IN (1B) of the two first address input ports IN (1A) and IN (1B) as its address input port.

The first to nth address input ports IN (1A)/IN (1B), IN (2), … …, IN (n) may receive address signals arranged from low to high, respectively; the received address signals may be input signals of a first n-input look-up table LUT (n) -1 and a second n-input look-up table LUT (n) -2, respectively; the first address input port IN (1A) may be input to the first adder adder [0] via the first multiplexer MUX1, and the first address input port IN (1B) may be input to the second adder adder [1] via the second multiplexer MUX 2; the n+1 address input port IN (n+1) is adapted to receive a high level signal or an address signal and to supply it to the control terminal of the third multiplexer MUX 3.

Carry input port CIN is adapted to receive a carry input signal and provide to first adder adder [0] for calculating a carry output signal and a sum output signal. The carry output port COUT is adapted to output a carry output signal, which may be used as a carry input signal for a next stage of arithmetic logic block.

The first output port OUT1 and the second output port OUT2 output different signals based on different applications of the look-up table circuit 200. When the lookup table circuit 200 is applied as two n-input lookup tables, the first output port OUT1 and the second output port OUT2 may be output ports of the first n-input lookup table LUT (n) -1 and the second n-input lookup table LUT (n) -2, respectively; when the lookup table circuit 200 is applied as an n+1 input lookup table, the second output port OUT2 may be used as the output port of the n+1 input lookup table; when the lookup table circuit 200 is applied as a two-bit wide arithmetic carry logic block, the first output port OUT1 and the second output port OUT2 may be used as output ports for neutralizing the output signal of the first adder adder [0] and the second adder adder [1], respectively; when the lookup table circuit 200 is applied as a one-bit-wide arithmetic carry logic module, the second output port OUT2 can be used as an output port for the neutralization output signal of the second adder adder [1], and at this time, the first n-input lookup table can be independently used, and the first output port OUT1 can be used as an output port of the first n-input lookup table LUT (n) -1.

The first multiplexer MUX1 has three inputs and one output, wherein the first input is grounded, the second input is connected to a power supply voltage, the third input is connected to one IN (1A) of two first address input ports IN (1A) and IN (1B), and the output is connected to the second input of the first adder adder [0 ].

The second multiplexer MUX2 has three inputs and one output, wherein the first input is grounded, the second input is connected to the supply voltage, the third input is connected to the other IN (1B) of the two first address input ports IN (1A) and IN (1B), and the output is connected to the second input of the second adder adder [1].

The third multiplexer MUX3 has two inputs, a control and an output, wherein the first input is connected to the output of the first n-input look-up table LUT (n) -1, the second input is connected to the output of the second n-input look-up table LUT (n) -2, the control is connected to the n+1th address input port IN (n+1), and the output is connected to the first input of the fourth multiplexer MUX 4.

The fourth multiplexer MUX4 has two inputs and an output, wherein the first input is connected to the output of the third multiplexer MUX3, the second input is connected to the first output of the second adder adder [1], and the output is connected to the second output OUT2.

The fifth multiplexer MUX5 has two inputs and one output, wherein a first input is connected to the output of the first n-input look-up table LUT (n) -1, a second input is connected to the first output of the first adder adder [0], and an output is connected to the first output port OUT1.

The sixth multiplexer MUX6 has two inputs and an output, wherein the first input is connected to the supply voltage, the second input is connected to the output of the first n-input look-up table LUT (n) -1, and the output is connected to the third input of the first adder adder [0 ].

The first adder adder has three inputs and two outputs, wherein the first input is connected to the carry input port CIN, the second input is connected to the output of the first multiplexer MUX1, the third input is connected to the output of the sixth multiplexer MUX6, the first output is connected to the second input of the fifth multiplexer MUX5 to output and output the carry output signal, and the second output is connected to the first input of the second adder adder [1 ].

The second adder adder [1] has three input terminals and two output terminals, wherein the first input terminal is connected to the second output terminal of the first adder adder [0], the second input terminal is connected to the output terminal of the second multiplexer MUX2, the third input terminal is connected to the output terminal of the second n-input lookup table LUT (n) -2, the first output terminal is connected to the second input terminal of the fourth multiplexer MUX4 to output and output signals, and the second output terminal is connected to the carry output port COUT to output carry output signals.

In an implementation, the fourth multiplexer MUX4 further has a control terminal, and the look-up table circuit 200 further includes a first static memory SRAM0 connected to the control terminal of the fourth multiplexer MUX 4. The first static memory SRAM0 is adapted to store configuration information, which may comprise a first value or a second value, according to an indication of the control module. The fourth multiplexer MUX4 is adapted to output a signal received at its first input based on the first value and to output a signal received at its second input based on the second value.

Specifically, the first value is one of 0 or 1, and the second value is the other of 0 or 1. For example, the first value may be 0 and the second value may be 1.

When the first static memory SRAM0 is configured to a first value, the fourth multiplexer MUX4 is adapted to output the signal output by the output of the third multiplexer MUX3 received at its first input based on the first value. When the first static memory SRAM0 is configured to a second value, the fourth multiplexer MUX4 is adapted to output the signal output by the first output of the second adder adder [1] received by its second input based on the second value.

In an implementation, the fifth multiplexer MUX5 and the sixth multiplexer MUX6 also have control terminals, respectively, and the look-up table circuit 200 further includes a second static memory SRAM1 connected to the control terminals of both the fifth multiplexer MUX5 and the sixth multiplexer MUX 6. The second static memory SRAM1 is adapted to store configuration information, which may comprise a first value or a second value, according to an indication of the control module. The fifth multiplexer MUX5 is adapted to output a signal received at its first input based on a first value and to output a signal received at its second input based on a second value. The sixth multiplexer MUX6 is adapted to output the signal received at its first input based on the first value and to output the signal received at its second input based on the second value.

Specifically, the first value is one of 0 or 1, and the second value is the other of 0 or 1. For example, the first value may be 0 and the second value may be 1.

When the second static memory SRAM1 is configured to a first value, the fifth multiplexer MUX5 is adapted to output a signal output by the first n-input look-up table LUT (n) -1 received at its first input based on the first value, and the sixth multiplexer MUX6 is adapted to output a high level signal (data "1") received at its first input based on the first value.

When the second static memory SRAM1 is configured to a second value, the fifth multiplexer MUX5 is adapted to output the sum output signal output by the first output terminal of the first adder adder [0] received at its second input terminal based on the second value, and the sixth multiplexer MUX6 is adapted to output the signal output by the first n-input look-up table LUT (n) -1 received at its second input terminal based on the second value.

In an embodiment of the present invention, the lookup table circuit 200 may be selectively applied as one of two n-input lookup tables, one n+1-input lookup table, a two-bit wide arithmetic carry logic module, and a one-bit wide arithmetic carry logic module.

Specifically, the application of the lookup table circuit 200 depends on the configuration of the first static memory SRAM0, the second static memory SRAM1, and the n+1th address input port IN (n+1).

IN an implementation, the look-up table circuit 200 may be applied as two n-input look-up tables when the first static memory SRAM0 is configured to a first value, the second static memory SRAM1 is configured to a first value, and the n+1th address input port IN (n+1) is configured to a high level signal.

When the first static memory SRAM0 is configured to a first value and the n+1 th address input port IN (n+1) is configured to the most significant address signal, the lookup table circuit 200 may be applied as an n+1 input lookup table. Further, when the second static memory SRAM1 is configured to the first value, the lookup table circuit 200 may also be applied as the first n-input lookup table.

When the first static memory SRAM0 is configured to a first value, the second static memory SRAM1 is configured to a second value, and the n+1th address input port IN (n+1) is configured to a high level signal, the lookup table circuit 200 may be applied as a one-bit wide arithmetic carry logic module. At this time, the second n-input lookup table LUT (n) -2 is no longer used alone, and outputs a high level signal (data "1"); and a second input terminal of the second adder adder [1] receives a low-level signal (data "0"), and a third input terminal thereof receives a high-level signal (data "1") output from the second n-input lookup table LUT (n) -2. Thus, the carry output signal output from the first adder adder [0] may be transferred to the carry output port COUT through the second adder adder [1 ].

When the first static memory SRAM0 is configured to a second value and the second static memory SRAM1 is configured to a second value, the look-up table circuit 200 may be applied as a two-bit wide arithmetic carry logic block.

When the first static memory SRAM0 is configured to the second value and the second static memory SRAM1 is configured to the first value, the look-up table circuit 200 may be applied as a one-bit wide arithmetic carry logic block, and a first n-input look-up table.

Five of these are illustrated below.

IN the first case, when the first static memory SRAM0 is configured to a first value (e.g., the first value is 0), the second static memory SRAM1 is configured to a first value (e.g., the first value is 0), and the n+1th address input port IN (n+1) receives a high level signal, the lookup table circuit 200 may be applied as two n-input lookup tables.

Specifically, the first address input port IN (1A), the second to n-th address input ports IN (2), … …, IN (n) are commonly used as address input ports of the first n-input look-up table LUT (n) -1, and the fifth multiplexer MUX5 selects a signal received at its first input terminal, i.e., a signal output by the first n-input look-up table LUT (n) -1, based on the first value configured by the second static memory SRAM1, and outputs the signal to the first output port OUT1.

The first address input port IN (1B), the second to nth address input ports IN (2), … …, IN (n) are commonly used as address input ports of the second n-input lookup table LUT (n) -2, the third multiplexer MUX3 selects a signal received at its second input terminal based on a high level signal received at its control terminal, that is, a signal output by the second n-input lookup table LUT (n) -2, and outputs the signal to the first input terminal of the fourth multiplexer MUX4, and the fourth multiplexer MUX4 selects a signal received at its first input terminal, that is, a signal output by the second n-input lookup table LUT (n) -2, based on a first value configured by the first static memory SRAM0 and outputs the signal to the second output port OUT2.

IN the second case, when the first static memory SRAM0 is configured to a first value (e.g., the first value is 0) and the n+1th address input port IN (n+1) receives the most significant address signal, the lookup table circuit 200 may be applied as an n+1 input lookup table.

Specifically, the first address input port IN (1A), the second to n-th address input ports IN (2), … …, IN (n) are commonly used as address input ports of the first n-input lookup table LUT (n) -1, the first address input port IN (1B), the second to n-th address input ports IN (2), … …, IN (n) are commonly used as address input ports of the second n-input lookup table LUT (n) -2, the third multiplexer MUX3 forms one n+1 input lookup table LUT (n+1) together with the highest bit address signal received by the n+1-th address input port IN (n+1) and the second n-input lookup table LUT (n) -2, and outputs the signal output by the n+1 input lookup table LUT (n+1) to the first input terminal of the fourth multiplexer MUX4, and the fourth multiplexer MUX4 selects the signal received by the first input terminal thereof, that is, the n+1 input LUT (n+1), to the second input LUT (n+1) output signal output by the fourth multiplexer MUX4 based on the first value of the first static memory 0 configuration.

In a third scenario, when the first static memory SRAM0 is configured to a second value (e.g., the second value is 1) and the second static memory SRAM1 is configured to the second value (e.g., the second value is 1), the look-up table circuit 200 may be applied as a two-bit wide arithmetic carry logic module.

When the lookup table circuit 200 is applied as a two-bit wide arithmetic carry logic module, for an addition carry operation of two binary numbers, the two binary numbers may be represented as a first addend a and a second addend B, respectively, wherein the first addend a includes a low-order first addend a_i and a high-order first addend a_i+1, and the second addend B includes a low-order second addend B_i and a high-order second addend B_i+1.

Specifically, carry input signal C_i is input to a first input to first adder adder [0] through carry input port CIN.

The lower first addend a_i (IN other embodiments, the lower second addend B_i may be) inputs the first n-input look-up table LUT (n) -1 through one of the two first address input ports IN (1A) and IN (1B), and the lower second addend B_i (IN other embodiments, the lower first addend a_i may be) inputs the first n-input look-up table LUT (n) -1 through one of the second through n-th address input ports IN (2), … …, IN (n). The first n-input lookup table LUT (n) -1 obtains a first carry propagation signal P_i according to equation (4) based on the low-order first addend a_i and the second addend B_i, and outputs it to the second input of the sixth multiplexer MUX 6. The sixth multiplexer MUX6 selects the first carry propagate signal P_i received at its second input based on the second value configured by the second static memory SRAM1 for output to the third input of the first adder adder [0 ].

IN some embodiments, the first multiplexer MUX1 may select the lower first addend a_i (IN other embodiments, the lower second addend B_i) received at the third input terminal thereof and input to the first address input port IN (1A) as the first carry generation signal G_i, and output to the second input terminal of the first adder adder [0 ].

FIG. 3 is a schematic diagram of a portion of the logic of a look-up table circuit in which a first adder is illustrated and a first multiplexer is not illustrated in an embodiment of the present invention; the second adder has a similar structure and operation principle.

As shown in fig. 3, the first adder adder [0] includes a seventh multiplexer MUX7. The seventh multiplexer MUX7 has two inputs, a control terminal and an output terminal, wherein the first input is configured to receive the low-order first addend a_i as the first carry generation signal G_i, the second input is configured to receive the carry input signal C_i, the control terminal is configured to receive the first carry propagation signal P_i, and the output terminal is configured to output the first carry output signal C_i+1.

In an implementation, the seventh multiplexer MUX7 may select the lower first addend a_i or the carry input signal C_i as the first carry output signal C_i+1 output based on the first carry propagate signal P_i received at its control terminal.

Specifically, when the lower first addend a_i and the lower second addend B_i take different values, the first carry generation signal G_i =0, the first carry propagation signal P_i =1, and the first carry output signal C_i+1＝C_i are obtained according to formulas (3), (4), and (5). Thus, when the first carry propagate signal P_i =1, the seventh multiplexer MUX7 may select the carry input signal C_i received at its second input terminal as the first carry output signal C_i+1 output.

When both the first addend a_i and the second addend B_i of the lower order take "1" entirely, the first carry generation signal G_i =1, the first carry propagation signal P_i =0, and the first carry output signal C_i+1 =1 are obtained according to formulas (3), (4), and (5). Thus, when the first carry propagate signal P_i =0, the seventh multiplexer MUX7 may select the first addend a_i of the lower order received at the first input terminal thereof as the first carry output signal C_i+1 to output.

When both the first addend a_i and the second addend B_i of the lower order take "0" entirely, the first carry generation signal G_i =0, the first carry propagation signal P_i =0, and the first carry output signal C_i+1 =0 are obtained according to formulas (3), (4), and (5). Thus, when the first carry propagate signal P_i =0, the seventh multiplexer MUX7 may select the first addend a_i of the lower order received at the first input terminal thereof as the first carry output signal C_i+1 to output.

Thus, IN the embodiment of the present invention, the first multiplexer MUX1 may select the lower first addend a_i (IN other embodiments, the lower second addend B_i) received at the third input terminal of the first multiplexer MUX1 as the first carry generating signal G_i, and output the first carry generating signal to the second input terminal of the first adder adder [0 ].

In other embodiments, the look-up table circuit 200 further comprises a third static memory SRAM2 connected to the first multiplexer MUX1, the third static memory SRAM2 being adapted to store configuration information according to an instruction of the control module. The first multiplexer MUX1 is adapted to output a corresponding first carry generation signal G_i based on configuration information of the third static memory SARM 2.

In particular, the configuration information may comprise a first value or a second value. The first value is one of 0 or 1 and the second value is the other of 0 or 1. For example, the first value may be 0 and the second value may be 1.

When the third static memory SRAM2 is configured to a first value, the first multiplexer MUX1 is adapted to output the low level signal (data "0") received at its first input terminal as the first carry generation signal G_i based on the first value. When the third static memory SRAM2 is configured to a second value, the first multiplexer MUX1 is adapted to output the power supply voltage VDD signal (data "1") received at the second input terminal as the first carry generation signal G_i based on the second value.

In an embodiment of the present invention, when the first carry generation signal G_i is a constant "0", the third static memory SRAM2 may be configured to a first value, so that the first multiplexer MUX1 may output the low-level signal (data "0") received at the first input terminal thereof as the first carry generation signal G_i based on the first value, and the first addend a_i of the low bits is 0; when the first carry generation signal G_i is a constant "1", the third static memory SRAM2 may be configured to a second value such that the first multiplexer MUX1 may output the power voltage VDD signal (data "1") received at its second input terminal as the first carry generation signal G_i based on the second value, and the first addend a_i of the lower bits is 1.

First adder adder [0] may derive first sum output signal S_i and first carry output signal C_i+1 according to formulas (5) and (6) based on carry input signal C_i, first carry generation signal G_i, and first carry propagation signal P_i. The first sum output signal S_i is output to the second input terminal of the fifth multiplexer MUX5 through the first output terminal of the first adder adder [0], the fifth multiplexer MUX5 selects the first sum output signal S_i received by the second input terminal thereof based on the second value configured by the second static memory SRAM1 to output to the first output port OUT1, and the first carry output signal C_i+1 is output to the first input terminal of the second adder adder [1] through the second output terminal of the first adder adder [0], and can be used as the carry input signal of the high-order arithmetic logic.

The higher first addend a_i+1 (IN other embodiments, the higher second addend B_i+1 may also be) inputs the second n-input look-up table LUT (n) -2 through the other one IN (1B) of the two first address input ports IN (1A) and IN (1B), and the higher second addend B_i+1 (IN other embodiments, the higher first addend a_i+1 may also be) inputs the second n-input look-up table LUT (n) -2 through the other one of the second through n-th address input ports IN (2), … …, IN (n) which is not occupied. The second n-input lookup table LUT (n) -2 obtains a second carry propagation signal P_i+1 according to equation (4) based on the first addend A_i+1 and the second addend B_i+1 of the high order bits and outputs the second carry propagation signal P_i+1 to the third input of the second adder adder [1 ].

In some embodiments, the structure of the second adder adder [1] may refer to the first adder adder [0] as shown in FIG. 3. Thus, the second multiplexer MUX2 may also select the high-order first addend a_i+1 (IN other embodiments, the high-order second addend B_i+1) received at the third input terminal thereof and input to the first address input port IN (1B) as the second carry generation signal G_i+1, and output the second carry generation signal G_i+1 to the second input terminal of the second adder adder [1 ].

In other embodiments, the look-up table circuit 200 further comprises a fourth static memory SRAM3 connected to the second multiplexer MUX2, the fourth static memory SRAM3 being adapted to store configuration information according to an instruction of the control module. The second multiplexer MUX2 is adapted to output a corresponding second carry generation signal G_i+1 based on configuration information of the third static memory SARM 2.

In particular, the configuration information may comprise a first value or a second value. The first value is one of 0 or 1 and the second value is the other of 0 or 1. For example, the first value may be 0 and the second value may be 1.

When the fourth static memory SRAM3 is configured to a first value, the second multiplexer MUX2 is adapted to output the low level signal (data "0") received at its first input terminal as the second carry generation signal G_i+1 based on the first value. When the fourth static memory SRAM3 is configured to a second value, the second multiplexer MUX2 is adapted to output the power supply voltage VDD signal (data "1") received at the second input terminal as the second carry generation signal G_i+1 based on the second value.

In the embodiment of the present invention, when the second carry generation signal G_i+1 is a constant "0", the fourth static memory SRAM3 may be configured to a first value so that the second multiplexer MUX2 may output the low level signal (data "0") received at the first input terminal thereof as the second carry generation signal G_i+1 based on the first value, and the high first addend a_i+1 is 0; when the second carry generation signal G_i+1 is a constant "1", the fourth static memory SRAM3 may be configured to a second value such that the second multiplexer MUX2 may output the power voltage VDD signal (data "1") received at its second input terminal as the second carry generation signal G_i+1 based on the second value, and the high first addend a_i+1 is 1.

The second adder adder [1] may obtain the second sum output signal S_i+1 and the second carry output signal C_i+2 according to formulas (5) and (6) based on the first carry output signal C_i+1, the second carry generation signal G_i+1, and the second carry propagation signal P_i+1. The second sum output signal S_i+1 is output to the second input terminal of the fourth multiplexer MUX4 through the first output terminal of the second adder adder [1], the fourth multiplexer MUX4 selects the second sum output signal S_i+1 received by the second input terminal thereof based on the second value configured by the first static memory SRAM0 to output to the second output port OUT2, and the second carry output signal C_i+2 is output to the carry output port COUT through the second output terminal of the second adder adder [1] and can be used as the carry input signal of the next arithmetic logic module.

In a fourth scenario, when the first static memory SRAM0 is configured to a second value (e.g., the second value is 1) and the second static memory SRAM1 is configured to a first value (e.g., the first value is 0), the look-up table circuit 200 may be applied as a one-bit wide arithmetic carry logic module.

When the lookup table circuit 200 is applied as a one-bit wide arithmetic carry logic block, for an addition carry operation of two binary numbers, the two binary numbers may be represented as a first addend a_i and a second addend B_i, respectively.

Specifically, carry input signal C_i is input to a first input to first adder adder [0] through carry input port CIN.

The third static memory SRAM2 is configured to a first value, and the first multiplexer MUX1 selects a low level signal (data "0") received at a first input terminal thereof based on the first value configured by the third static memory SRAM2 and outputs the low level signal (data "0") to a second input terminal of the first adder adder [0], that is, outputs the carry-in-space generation signal g=0 to the first adder adder [0].

The sixth multiplexer MUX6 selects a high level signal (data "1") received at its first input based on the first value of the second static memory SRAM1 configuration and outputs the high level signal to the third input of the first adder adder [0], i.e., outputs the carry-in-space propagation signal p=1 to the first adder adder [0].

The first adder derives a carry-in signal C, i.e., c=c_i, according to equation (5) based on the carry-in signal C_i, the carry-in generation signal G, and the carry-in propagation signal P. The carry-out signal C, C_i, is output to the first input of the second adder adder [1] via the second output of the first adder adder [0] and serves as the carry-in signal for the second adder adder [1 ].

Wherein, the empty bit indicates that the two addend inputs of the first adder adder [0] are empty, which is not used for the logical operation of the two addends, but is used only for transferring the carry input signal C_i.

Thus, when the lookup table circuit 200 is applied as a one-bit wide arithmetic carry logic block, the carry input signal C_i input to the first adder adder [0] through the carry input port CIN can be directly used as the carry input signal of the second adder adder [1 ].

The first addend a_i (IN other embodiments, the second addend B_i may be) inputs the second n-input look-up table LUT (n) -2 through the other IN (1B) of the two first address input ports IN (1A) and IN (1B), and the second addend B_i (IN other embodiments, the first addend a_i may be) inputs the second n-input look-up table LUT (n) -2 through one of the second through n-th address input ports. The second n-input lookup table LUT (n) -2 obtains the carry propagation signal P_i according to equation (4) based on the first addend A_i and the second addend B_i, and outputs the carry propagation signal P_i to the third input of the second adder adder [1 ].

When the carry generation signal G_i is not always "1" or not always "0", the second multiplexer MUX2 may select the first addend a_i (IN other embodiments, the second addend B_i) inputted from the first address input port IN (1B) received by the third input terminal thereof as the carry generation signal G_i, and output the carry generation signal G_i to the second input terminal of the second adder adder [1 ].

When the carry generation signal G_i is a constant "0", the fourth static memory SRAM3 may be configured to a first value so that the second multiplexer MUX2 may output a low-level signal (data "0") received at a first input terminal thereof as the carry generation signal G_i based on the first value.

When the carry generation signal G_i is a constant "1", the fourth static memory SRAM3 may be configured to a second value so that the second multiplexer MUX2 may output the power voltage VDD signal (data "1") received at its second input terminal as the carry generation signal G_i based on the second value.

When the lookup table circuit 200 is applied as a one-bit wide arithmetic carry logic module, one-bit wide arithmetic carry logic operation can be implemented by the second adder adder [1 ]. The second adder adder [1] may derive a sum output signal S_i and a carry output signal C_i+1 according to formulas (5) and (6) based on the carry input signal C_i, the carry generation signal G_i, and the carry propagation signal P_i. Wherein the sum output signal S_i is output to the second input terminal of the fourth multiplexer MUX4 through the first output terminal of the second adder adder [1], and the fourth multiplexer MUX4 selects the sum output signal S_i received by the second input terminal thereof based on the second value configured by the first static memory SRAM0 and outputs the selected sum output signal to the second output port OUT2; the carry output signal C_i+1 is output to the carry output port COUT through the second output terminal of the second adder adder [1], and can be used as a carry input signal of the next stage arithmetic logic module.

When the look-up table circuit 200 is implemented as a one-bit wide arithmetic carry logic block, the first n-input look-up table LUT (n) -1 may be used independently. The fifth multiplexer MUX5 selects the signal output from the first n-input lookup table LUT (n) -1 received at the first input terminal thereof based on the first value configured by the second static memory SRAM1, and outputs the signal to the first output port OUT1.

IN a fifth case, when the first static memory SRAM0 is configured to a first value (e.g., the first value is 0), the second static memory SRAM1 is configured to a second value (e.g., the second value is 1), and the n+1th address input port IN (n+1) is configured to a high level signal, the lookup table circuit 200 may be applied as a one-bit-wide arithmetic carry logic module.

When the lookup table circuit 200 is applied as a one-bit wide arithmetic carry logic block, for an addition carry operation of two binary numbers, the two binary numbers may be represented as a first addend a_i and a second addend B_i, respectively.

Specifically, carry input signal C_i is input to a first input to first adder adder [0] through carry input port CIN.

The first addend a_i (IN other embodiments, the second addend B_i may be input to the first n-input look-up table LUT (n) -1 through one IN (1A) of the two first address input ports IN (1A) and IN (1B), and the second addend B_i (IN other embodiments, the first addend a_i may be input to the first n-input look-up table LUT (n) -1 through one of the second through n-th address input ports IN (2), … …, IN (n). The first n-input lookup table LUT (n) -1 obtains the carry propagation signal P_i according to equation (4) based on the first addend a_i and the second addend B_i, and outputs it to the second input of the sixth multiplexer MUX 6. The sixth multiplexer MUX6 selects the carry propagate signal P_i received at its second input based on the second value of the second static memory SRAM1 configuration and outputs it to the third input of the first adder adder [0 ].

IN some embodiments, the first multiplexer MUX1 may select the first addend a_i (IN other embodiments, the second addend B_i) input from the first address input port IN (1A) received at the third input terminal thereof as the carry generation signal G_i, and output the carry generation signal G_i to the second input terminal of the first adder adder [0 ].

First adder adder [0] may derive sum output signal S_i and carry output signal C_i+1 according to formulas (5) and (6) based on carry input signal C_i, carry generation signal G_i, and carry propagate signal P_i. The sum output signal S_i is output to the second input terminal of the fifth multiplexer MUX5 through the first output terminal of the first adder adder [0], the fifth multiplexer MUX5 selects the sum output signal S_i received by the second input terminal thereof to output to the first output port OUT1 based on the second value configured by the second static memory SRAM1, and the carry output signal C_i+1 is output to the first input terminal of the second adder adder [1] through the second output terminal of the first adder adder [0 ].

At this time, the fourth static memory SRAM3 is configured to a first value (e.g., the first value is 0), and the second multiplexer MUX2 outputs a low-level signal (data "0") received at its first input terminal based on the configured first value; the second n-input look-up table LUT (n) -2 is no longer used alone and outputs a high level signal (data "1"). A second input terminal of the second adder adder [1] receives the low-level signal (data "0") output from the second multiplexer MUX2, and a third input terminal thereof receives the high-level signal (data "1") output from the second n-input lookup table LUT (n) -2. Thus, the carry output signal C_i+1 output from the first adder adder [0] can be transferred to the carry output port COUT through the second adder adder [1 ].

Fig. 4 is a schematic diagram of a lookup table circuit including two five-input lookup tables in an embodiment of the invention.

As shown IN fig. 4, the lookup table circuit 200 includes two first address input ports IN (1A) and IN (1B), second to sixth address input ports IN (2), IN (3), IN (4), IN (5), IN (6), a carry input port CIN, a carry output port COUT, a first output port OUT1, and a second output port OUT2, wherein the first address input port has two, the second to sixth address input ports have one, respectively, and n is an integer greater than or equal to 5.

The lookup table circuit 200 further includes first to sixth multiplexers MUX1, MUX2, MUX3, MUX4, MUX5, and MUX6, first and second five-input lookup tables LUT (5) -1 and LUT (5) -2, and first and second adders adder [0] and adder [1].

The first five-input lookup table LUT (5) -1 and the second five-input lookup table LUT (5) -2 both share the second to fifth address input ports IN (2), IN (3), IN (4), IN (5), the first five-input lookup table LUT (5) -1 individually using one IN (1A) of the two first address input ports IN (1A) and IN (1B) as its address input port, the second five-input lookup table LUT (5) -2 individually using the other IN (1B) of the two first address input ports IN (1A) and IN (1B) as its address input port.

The first to fifth address input ports IN (1A)/IN (1B), IN (2), IN (3), IN (4), IN (5) may receive address signals arranged from low to high, respectively; the received address signals may be input signals of the first five-input look-up table LUT (5) -1 and the second five-input look-up table LUT (5) -2, respectively; the first address input port IN (1A) may be input to the first adder adder [0] via the first multiplexer MUX1, and the first address input port IN (1B) may be input to the second adder adder [1] via the second multiplexer MUX 2; the sixth address input port IN (6) is adapted to receive a high level signal or an address signal and to supply it to the control terminal of the third multiplexer MUX 3.

Carry input port CIN is adapted to receive a carry input signal and provide to first adder adder [0] for calculating a carry output signal and a sum output signal. The carry output port COUT is adapted to output a carry output signal, which may be used as a carry input signal for a next stage of arithmetic logic block.

The first output port OUT1 and the second output port OUT2 output different signals based on different applications of the look-up table circuit 200. When the lookup table circuit 200 is applied as two five-input lookup tables, the first output port OUT1 and the second output port OUT2 can be respectively used as the output ports of the first five-input lookup table LUT (5) -1 and the second five-input lookup table LUT (5) -2; when the look-up table circuit 200 is applied as a six-input look-up table, the second output port OUT2 may be used as the output port of the six-input look-up table; when the lookup table circuit 200 is applied as a two-bit wide arithmetic carry logic block, the first output port OUT1 and the second output port OUT2 may be used as output ports for neutralizing the output signal of the first adder adder [0] and the second adder adder [1], respectively; when the lookup table circuit 200 is applied as a one-bit-wide arithmetic carry logic module, the second output port OUT2 can be used as an output port for the neutralization output signal of the second adder adder [1], and at this time, the first five-input lookup table can be independently used, and the first output port OUT1 can be used as an output port of the first five-input lookup table LUT (5) -1.

The first multiplexer MUX1 has three inputs and one output, wherein the first input is grounded, the second input is connected to a power supply voltage, the third input is connected to one IN (1A) of two first address input ports IN (1A) and IN (1B), and the output is connected to the second input of the first adder adder [0 ].

The second multiplexer MUX2 has three inputs and one output, wherein the first input is grounded, the second input is connected to the supply voltage, the third input is connected to the other IN (1B) of the two first address input ports IN (1A) and IN (1B), and the output is connected to the second input of the second adder adder [1].

The third multiplexer MUX3 has two inputs, a control and an output, wherein the first input is connected to the output of the first five-input look-up table LUT (5) -1, the second input is connected to the output of the second five-input look-up table LUT (5) -2, the control is connected to the sixth address input port IN (6), and the output is connected to the first input of the fourth multiplexer MUX 4.

The fourth multiplexer MUX4 has two inputs and an output, wherein the first input is connected to the output of the third multiplexer MUX3, the second input is connected to the first output of the second adder adder [1], and the output is connected to the second output OUT2.

The fifth multiplexer MUX5 has two inputs and one output, wherein a first input is connected to the output of the first five-input look-up table LUT (5) -1, a second input is connected to the first output of the first adder adder [0], and an output is connected to the first output port OUT1.

The sixth multiplexer MUX6 has two inputs and an output, wherein the first input is connected to the supply voltage, the second input is connected to the output of the first five-input look-up table LUT (5) -1, and the output is connected to the third input of the first adder adder [0 ].

The first adder adder has three inputs and two outputs, wherein the first input is connected to the carry input port CIN, the second input is connected to the output of the first multiplexer MUX1, the third input is connected to the output of the sixth multiplexer MUX6, the first output is connected to the second input of the fifth multiplexer MUX5 to output and output the carry output signal, and the second output is connected to the first input of the second adder adder [1 ].

The second adder adder [1] has three input terminals and two output terminals, wherein the first input terminal is connected to the second output terminal of the first adder adder [0], the second input terminal is connected to the output terminal of the second multiplexer MUX2, the third input terminal is connected to the output terminal of the second five-input lookup table LUT (5) -2, the first output terminal is connected to the second input terminal of the fourth multiplexer MUX4 to output and output signals, and the second output terminal is connected to the carry output port COUT to output carry output signals.

In an implementation, the fourth multiplexer MUX4 further has a control terminal, and the look-up table circuit 200 further includes a first static memory SRAM0 connected to the control terminal of the fourth multiplexer MUX 4. The first static memory SRAM0 is adapted to store configuration information, which may comprise a first value or a second value, according to an indication of the control module. The fourth multiplexer MUX4 is adapted to output a signal received at its first input based on the first value and to output a signal received at its second input based on the second value.

Specifically, the first value is one of 0 or 1, and the second value is the other of 0 or 1. For example, the first value may be 0 and the second value may be 1.

When the first static memory SRAM0 is configured to a first value, the fourth multiplexer MUX4 is adapted to output the signal output by the output of the third multiplexer MUX3 received at its first input based on the first value. When the first static memory SRAM0 is configured to a second value, the fourth multiplexer MUX4 is adapted to output the signal output by the first output of the second adder adder [1] received by its second input based on the second value.

In an implementation, the fifth multiplexer MUX5 and the sixth multiplexer MUX6 also have control terminals, respectively, and the look-up table circuit 200 further includes a second static memory SRAM1 connected to the control terminals of both the fifth multiplexer MUX5 and the sixth multiplexer MUX 6. The second static memory SRAM1 is adapted to store configuration information, which may comprise a first value or a second value, according to an indication of the control module. The fifth multiplexer MUX5 is adapted to output a signal received at its first input based on a first value and to output a signal received at its second input based on a second value. The sixth multiplexer MUX6 is adapted to output the signal received at its first input based on the first value and to output the signal received at its second input based on the second value.

Specifically, the first value is one of 0 or 1, and the second value is the other of 0 or 1. For example, the first value may be 0 and the second value may be 1.

When the second static memory SRAM1 is configured to a first value, the fifth multiplexer MUX5 is adapted to output a signal output by the first five-input look-up table LUT (5) -1 received at its first input based on the first value, and the sixth multiplexer MUX6 is adapted to output a high-level signal (data "1") received at its first input based on the first value.

When the second static memory SRAM1 is configured to a second value, the fifth multiplexer MUX5 is adapted to output the sum output signal output by the first output terminal of the first adder adder [0] received at its second input terminal based on the second value, and the sixth multiplexer MUX6 is adapted to output the signal output by the first five-input look-up table LUT (5) -1 received at its second input terminal based on the second value.

In an embodiment of the present invention, the lookup table circuit 200 may be selectively applied as one of two five-input lookup tables, one six-input lookup table, two-bit wide arithmetic carry logic modules, and one-bit wide arithmetic carry logic modules.

IN an implementation, when the first static memory SRAM0 is configured to a first value (e.g., the first value is 0), the second static memory SRAM1 is configured to a first value (e.g., the first value is 0), and the sixth address input port IN (6) receives a high level signal, the lookup table circuit 200 may be applied as two five-input lookup tables.

Specifically, the first address input port IN (1A), the second to fifth address input ports IN (2), IN (3), IN (4), IN (5) are commonly used as address input ports of the first five-input lookup table LUT (5) -1, and the fifth multiplexer MUX5 selects a signal received at its first input terminal, that is, a signal output by the first five-input lookup table LUT (5) -1, based on the first value configured by the second static memory SRAM1, and outputs the signal to the first output port OUT1.

The first address input port IN (1B), the second to fifth address input ports IN (2), IN (3), IN (4), IN (5) are commonly used as address input ports of the second five-input lookup table LUT (5) -2, the third multiplexer MUX3 selects a signal received at the second input terminal thereof, that is, a signal output by the second five-input lookup table LUT (5) -2, based on a high level signal received at the control terminal thereof, and outputs the signal to the first input terminal of the fourth multiplexer MUX4, and the fourth multiplexer MUX4 selects a signal received at the first input terminal thereof, that is, a signal output by the second five-input lookup table LUT (5) -2, based on a first value configured by the first static memory SRAM0 and outputs the signal to the second output port OUT2.

IN an implementation, when the first static memory SRAM0 is configured to a first value (e.g., the first value is 0), the sixth address input port IN (6) receives the most significant address signal, the look-up table circuit 200 may be implemented as a six-input look-up table.

Specifically, the first address input port IN (1A), the second to fifth address input ports IN (2), IN (3), IN (4), IN (5) are commonly used as address input ports of the first five input lookup table LUT (5) -1, the first address input port IN (1B), the second to fifth address input ports IN (2), IN (3), IN (4), IN (5) are commonly used as address input ports of the second five input lookup table LUT (5) -2, the third multiplexer MUX3 forms a six input lookup table LUT6 together with the first five input lookup table LUT (5) -1, the second five input lookup table LUT (5) -2 based on the most significant address signal received by the sixth address input port IN (6), and outputs the signal output by the six input lookup table LUT6 to the first input terminal of the fourth multiplexer MUX4, the fourth multiplexer MUX4 selects the signal received by the first input terminal thereof based on the first value of the first static memory SRAM0, that is, and outputs the signal output by the six input table LUT6 to the second output port 2.

IN an implementation, when the first static memory SRAM0 is configured to a second value (e.g., the second value is 1), the second static memory SRAM1 is configured to a second value (e.g., the second value is 1), and the sixth address input port IN (6) receives a high level signal, the lookup table circuit 200 may be applied as a two-bit wide arithmetic carry logic module.

When the lookup table circuit 200 is applied as a two-bit wide arithmetic carry logic module, for an addition carry operation of two binary numbers, the two binary numbers may be represented as a first addend a and a second addend B, respectively, wherein the first addend a includes a low-order first addend a_i and a high-order first addend a_i+1, and the second addend B includes a low-order second addend B_i and a high-order second addend B_i+1.

Specifically, carry input signal C_i is input to a first input to first adder adder [0] through carry input port CIN.

The first lower addend a_i (IN other embodiments, the second lower addend B_i may be) is input to the first five-input lookup table LUT (5) -1 through one IN (1A) of the two first address input ports IN (1A) and IN (1B), and the second lower addend B_i (IN other embodiments, the first lower addend a_i may be input to the first five-input lookup table LUT (5) -1 through one of the second to fifth address input ports IN (2), IN (3), IN (4), IN (5). The first five-input lookup table LUT (5) -1 obtains a first carry propagation signal P_i according to equation (4) based on the low-order first addend a_i and the second addend B_i, and outputs it to the second input of the sixth multiplexer MUX 6. The sixth multiplexer MUX6 selects the first carry propagate signal P_i received at its second input based on the second value configured by the second static memory SRAM1 for output to the third input of the first adder adder [0 ].

When the first carry generation signal G_i is not always "1" or not always "0", the first multiplexer MUX1 may select the low-order first addend a_i (IN other embodiments, the low-order second addend B_i) inputted by the first address input port IN (1A) received by the third input terminal thereof as the first carry generation signal G_i, and output the first carry generation signal G_i to the second input terminal of the second adder adder [1 ].

When the first carry generation signal G_i is a constant "0", the third static memory SRAM2 may be configured to a first value such that the first multiplexer MUX1 may output the low level signal (data "0") received at its first input terminal as the first carry generation signal G_i based on the first value, when the first addend a_i of the low order bits is 0; when the first carry generation signal G_i is a constant "1", the third static memory SRAM2 may be configured to a second value such that the first multiplexer MUX1 may output the power voltage VDD signal (data "1") received at its second input terminal as the first carry generation signal G_i based on the second value, and the first addend a_i of the lower bits is 1.

First adder adder [0] obtains first sum output signal S_i and first carry output signal C_i+1 according to formulas (5) and (6) based on carry input signal C_i, first carry generation signal G_i, and first carry propagation signal P_i. The first sum output signal S_i is output to the second input terminal of the fifth multiplexer MUX5 through the first output terminal of the first adder adder [0], the fifth multiplexer MUX5 selects the first sum output signal S_i received by the second input terminal thereof based on the second value configured by the second static memory SRAM1 to output to the first output port OUT1, and the first carry output signal C_i+1 is output to the first input terminal of the second adder adder [1] through the second output terminal of the first adder adder [0], and can be used as the carry input signal of the high-order arithmetic logic.

The higher first addend a_i+1 (IN other embodiments, the higher second addend B_i+1 may be) inputs the second five-input lookup table LUT (5) -2 through the other IN (1B) of the two first address input ports IN (1A) and IN (1B), and the higher second addend B_i+1 (IN other embodiments, the higher first addend a_i+1 may be) inputs the second five-input lookup table LUT (5) -2 through the other unoccupied address input port of the second through fifth address input ports IN (2), IN (3), IN (4), IN (5). The second five-input lookup table LUT (5) -2 obtains a second carry propagation signal P_i+1 according to equation (4) based on the first addend A_i+1 and the second addend B_i+1 of the high order bits and outputs the second carry propagation signal P_i+1 to the third input of the second adder adder [1 ].

When the second carry generation signal G_i+1 is not always "1" or not always "0", the second multiplexer MUX2 may also select the high-order first addend a_i+1 (IN other embodiments, the high-order second addend B_i+1) inputted from the first address input port IN (1B) received by the third input terminal thereof as the second carry generation signal G_i+1, and output the second carry generation signal G_i+1 to the second input terminal of the second adder adder [1 ].

When the second carry generation signal G_i+1 is a constant "0", the fourth static memory SRAM3 may be configured to a first value such that the second multiplexer MUX2 may output the low level signal (data "0") received at its first input terminal as the second carry generation signal G_i+1 based on the first value, when the first addend a_i+1 of the high order is 0; when the second carry generation signal G_i+1 is a constant "1", the fourth static memory SRAM3 may be configured to a second value such that the second multiplexer MUX2 may output the power voltage VDD signal (data "1") received at its second input terminal as the second carry generation signal G_i+1 based on the second value, and the high first addend a_i+1 is 1.

The second adder adder [1] generates a second sum output signal S_i+1 and a second carry output signal C_i+2 according to formulas (5) and (6) based on the first carry output signal C_i+1, the second carry generation signal G_i+1, and the second carry propagation signal P_i+1. The second sum output signal S_i+1 is output to the second input terminal of the fourth multiplexer MUX4 through the first output terminal of the second adder adder [1], the fourth multiplexer MUX4 selects the second sum output signal S_i+1 received by the second input terminal thereof based on the second value configured by the first static memory SRAM0 to output to the second output port OUT2, and the second carry output signal C_i+2 is output to the carry output port COUT through the second output terminal of the second adder adder [1] and can be used as the carry input signal of the next arithmetic logic module.

IN an implementation, when the first static memory SRAM0 is configured to a second value (e.g., the second value is 1), the second static memory SRAM1 is configured to a first value (e.g., the first value is 0), and the sixth address input port IN (6) receives a high level signal, the lookup table circuit 200 may be applied as a one-bit-wide arithmetic carry logic module.

When the lookup table circuit 200 is applied as a one-bit wide arithmetic carry logic block, for an addition carry operation of two binary numbers, the two binary numbers may be represented as a first addend a_i and a second addend B_i, respectively.

Specifically, carry input signal C_i is input to a first input to first adder adder [0] through carry input port CIN.

The third static memory SRAM2 is configured to a first value, and the first multiplexer MUX1 selects a low level signal (data "0") received at a first input terminal thereof based on the first value configured by the third static memory SRAM2 and outputs the low level signal (data "0") to a second input terminal of the first adder adder [0], that is, outputs the carry-in-space generation signal g=0 to the first adder adder [0].

The sixth multiplexer MUX6 selects a high level signal (data "1") received at its first input based on the first value of the second static memory SRAM1 configuration and outputs the high level signal to the third input of the first adder adder [0], i.e., outputs the carry-in-space propagation signal p=1 to the first adder adder [0].

The first adder derives a carry-in signal C, i.e., c=c_i, according to equation (5) based on the carry-in signal C_i, the carry-in generation signal G, and the carry-in propagation signal P. The carry-out signal C, C_i, is output to the first input of the second adder adder [1] via the second output of the first adder adder [0] and serves as the carry-in signal for the second adder adder [1 ].

Wherein, the empty bit indicates that the two addend inputs of the first adder adder [0] are empty, which is not used for the logical operation of the two addends, but is used only for transferring the carry input signal Ci.

Thus, when the lookup table circuit 200 is applied as a one-bit wide arithmetic carry logic block, the carry input signal C_i input to the first adder adder [0] through the carry input port CIN can be directly used as the carry input signal of the second adder adder [1 ].

The first addend a_i (IN other embodiments, the second addend B_i) inputs the second five-input look-up table LUT (5) -2 through the other IN (1B) of the two first address input ports IN (1A) and IN (1B), and the second addend B_i (IN other embodiments, the first addend a_i) inputs the second five-input look-up table LUT (5) -2 through one of the second through n-th address input ports. The second five-input lookup table LUT (5) -2 obtains the carry propagation signal P_i according to equation (4) based on the first addend A_i and the second addend B_i, and outputs the carry propagation signal P_i to the third input of the second adder adder [1 ].

When the carry generation signal G_i is not always "1" or not always "0", the second multiplexer MUX2 may select the first addend a_i (IN other embodiments, the second addend B_i) inputted from the first address input port IN (1B) received by the third input terminal thereof as the carry generation signal G_i, and output the carry generation signal G_i to the second input terminal of the second adder adder [1 ].

When the carry generation signal G_i is a constant "0", the fourth static memory SRAM3 may be configured to a first value such that the second multiplexer MUX2 may output a low level signal (data "0") received at its first input terminal as the carry generation signal G_i based on the first value, when the first addend a_i is 0; when the carry generation signal G_i is a constant "1", the fourth static memory SRAM3 may be configured to a second value such that the second multiplexer MUX2 may output the power voltage VDD signal (data "1") received at its second input terminal as the carry generation signal G_i based on the second value, and the first addend a_i is 1.

When the lookup table circuit 200 is applied as a one-bit wide arithmetic carry logic module, one-bit wide arithmetic carry logic operation is implemented by the second adder adder [1 ]. The second adder adder [1] obtains the sum output signal S_i and the carry output signal C_i+1 according to formulas (5) and (6) based on the carry input signal C_i, the carry generation signal G_i, and the carry propagation signal P_i. Wherein the sum output signal S_i is output to the second input terminal of the fourth multiplexer MUX4 through the first output terminal of the second adder adder [1], and the fourth multiplexer MUX4 selects the sum output signal S_i received by the second input terminal thereof based on the second value configured by the first static memory SRAM0 and outputs the selected sum output signal to the second output port OUT2; the carry output signal C_i+1 is output to the carry output port COUT through the second output terminal of the second adder adder [1], and can be used as a carry input signal of the next stage arithmetic logic module.

The first five-input look-up table LUT (5) -1 may be used independently when the look-up table circuit 200 is applied as a one-bit wide arithmetic carry logic block. The fifth multiplexer MUX5 selects the signal output from the first five-input lookup table LUT (5) -1 received at the first input terminal thereof based on the first value configured by the second static memory SRAM1, and outputs the signal to the first output port OUT1.

IN an implementation, when the first static memory SRAM0 is configured to a first value (e.g., the first value is 0), the second static memory SRAM1 is configured to a second value (e.g., the second value is 1), and the sixth address input port IN (6) is configured to a high level signal, the lookup table circuit 200 may be applied as a one-bit wide arithmetic carry logic module.

When the lookup table circuit 200 is applied as a one-bit wide arithmetic carry logic block, for an addition carry operation of two binary numbers, the two binary numbers may be represented as a first addend a_i and a second addend B_i, respectively.

Specifically, carry input signal C_i is input to a first input to first adder adder [0] through carry input port CIN.

The first addend a_i (IN other embodiments, the second addend B_i) inputs the first five-input lookup table LUT (5) -1 through one IN (1A) of the two first address input ports IN (1A) and IN (1B), and the second addend B_i (IN other embodiments, the first addend a_i) inputs the first five-input lookup table LUT (5) -1 through one of the second to fifth address input ports IN (2), … …, IN (5). The first five-input lookup table LUT (5) -1 obtains the carry propagation signal P_i according to equation (4) based on the first addend a_i and the second addend B_i, and outputs it to the second input of the sixth multiplexer MUX 6. The sixth multiplexer MUX6 selects the carry propagate signal P_i received at its second input based on the second value of the second static memory SRAM1 configuration and outputs it to the third input of the first adder adder [0 ].

IN some embodiments, the first multiplexer MUX1 may select the first addend a_i (IN other embodiments, the second addend B_i) input from the first address input port IN (1A) received at the third input terminal thereof as the carry generation signal G_i, and output the carry generation signal G_i to the second input terminal of the first adder adder [0 ].

First adder adder [0] may derive sum output signal S_i and carry output signal C_i+1 according to formulas (5) and (6) based on carry input signal C_i, carry generation signal G_i, and carry propagate signal P_i. The sum output signal S_i is output to the second input terminal of the fifth multiplexer MUX5 through the first output terminal of the first adder adder [0], the fifth multiplexer MUX5 selects the sum output signal S_i received by the second input terminal thereof to output to the first output port OUT1 based on the second value configured by the second static memory SRAM1, and the carry output signal C_i+1 is output to the first input terminal of the second adder adder [1] through the second output terminal of the first adder adder [0 ].

At this time, the fourth static memory SRAM3 is configured to a first value (e.g., the first value is 0), and the second multiplexer MUX2 outputs a low-level signal (data "0") received at its first input terminal based on the configured first value; the second five-input lookup table LUT (5) -2 is no longer used alone and outputs a high level signal (data "1"). A second input terminal of the second adder adder [1] receives the low-level signal (data "0") output from the second multiplexer MUX2, and a third input terminal thereof receives the high-level signal (data "1") output from the second five-input lookup table LUT (5) -2. Thus, the carry output signal C_i+1 output from the first adder adder [0] can be transferred to the carry output port COUT through the second adder adder [1 ].

The embodiment of the invention also provides a method for configuring the lookup table circuit. The lookup table circuit provided by the embodiment of the invention can be selectively applied to one of two n-input lookup tables, one n+1-input lookup table, a two-bit-wide arithmetic carry logic module and a one-bit-wide arithmetic carry logic module through the method.

Specifically, the application of the lookup table circuit 200 depends on the configuration of the first static memory SRAM0, the second static memory SRAM1, and the n+1th address input port IN (n+1).

IN an implementation, when the first static memory SRAM0 is configured to a first value, the second static memory SRAM1 is configured to a first value, and the n+1th address input port IN (n+1) is configured to a high level signal, the lookup table circuit 200 may be applied as two n-input lookup tables.

When the first static memory SRAM0 is configured to a first value and the n+1 th address input port IN (n+1) is configured to the most significant address signal, the lookup table circuit 200 may be applied as an n+1 input lookup table. Further, when the second static memory SRAM1 is configured to the first value, the lookup table circuit 200 may also be applied as the first n-input lookup table.

When the first static memory SRAM0 is configured to a first value, the second static memory SRAM1 is configured to a second value, and the n+1th address input port IN (n+1) is configured to a high level signal, the lookup table circuit 200 may be applied as a one-bit wide arithmetic carry logic module, and a second n-input lookup table or n+1-input lookup table.

When the first static memory SRAM0 is configured to a second value and the second static memory SRAM1 is configured to a second value, the look-up table circuit 200 may be applied as a two-bit wide arithmetic carry logic block.

When the first static memory SRAM0 is configured to the second value and the second static memory SRAM1 is configured to the first value, the look-up table circuit 200 may be applied as a one-bit wide arithmetic carry logic block, and a first n-input look-up table.

Fig. 5 is a first flowchart of a method of configuring a look-up table circuit in an embodiment of the invention.

As shown in fig. 5, the method 400 includes:

S401, outputting a second value to a sixth multiplexer;

S402, outputting a first carry propagation signal to a first adder by a sixth multiplexer based on the second value;

S403, the first adder receives the carry input signal, the first carry generation signal, and the first carry propagation signal, and generates a first carry output signal and a first sum output signal based thereon;

S404, the second adder receives the first carry output signal, the second carry generation signal and the second carry propagation signal and generates a second carry output signal and a second sum output signal based thereon;

s405, the second adder provides the second carry output signal to the carry output port;

S406, the first adder and the second adder respectively provide the first and the second output signals to the fifth multiplexer and the fourth multiplexer;

s407, outputting respective second values to the fourth multiplexer and the fifth multiplexer;

S408, the fourth multiplexer and the fifth multiplexer output the second and the output signals to the second and the first output ports, respectively, based on the second values received by each.

In the execution of step S401, a second value (for example, the second value is 1) may be output to the sixth multiplexer MUX6 through the second static memory SRAM 1.

In the execution of step S402, the sixth multiplexer MUX6 selects the first carry propagate signal P_i received at its second input based on the second value and outputs it to the first adder adder [0]. The first carry propagate signal P_i is obtained by a first n-input look-up table LUT (n) -1.

In the execution of step S403, the first adder adder [0] receives the carry input signal CIN, the first carry generation signal G_i, and the first carry propagation signal P_i through its three inputs, respectively, and generates the first carry output signal C_i+1 and the first sum output signal S_i based on the three inputs. The first carry generation signal G_i is obtained from the first multiplexer MUX 1.

In the execution of step S404, the second adder adder [1] receives the first carry output signal C_i+1, the second carry generation signal G_i+1, and the second carry propagation signal P_i+1 through its three inputs, respectively, and generates the second carry output signal C_i+2 and the second sum output signal S_i+1 based thereon. The second carry generation signal G_i+1 is obtained through the second multiplexer MUX2, and the second carry propagation signal P_i+1 is obtained through the second n-input lookup table LUT (n) -2.

In the execution of step S405, the second adder adder [1] provides the second carry output signal C_i+2 to the carry output port COUT.

In the execution of step S406, the first adder adder [0] and the second adder adder [1] supply the first and output signals S_i and the second and output signals S_i+1, respectively, to the fifth multiplexer MUX5 and the fourth multiplexer MUX4.

In the execution of step S407, the respective second values are output to the fourth multiplexer MUX4 and the fifth multiplexer MUX5, respectively.

In the execution of step S408, the fourth multiplexer MUX4 and the fifth multiplexer MUX5 output the second sum output signal S_i+1 and the first sum output signal S_i to the second output port OUT2 and the first output port OUT1, respectively, based on the second values received respectively.

When the first static memory SRAM0 is configured to a second value (e.g., the second value is 1), the second static memory SRAM1 is configured to a first value (e.g., the first value is 0), and the n+1th address input port IN (n+1) receives a high level signal, the lookup table circuit 200 may be applied as a one-bit-wide arithmetic carry logic module.

Fig. 6 is a second flowchart of a method of configuring a look-up table circuit in an embodiment of the invention.

As shown in fig. 6, the method 500 includes:

s501, outputting a first value to a sixth multiplexer;

S502, the sixth multiplexer outputs a high level signal to the first adder based on the first value;

S503, the first adder receives the carry input signal, the low level signal, and the high level signal, and outputs the carry input signal based thereon;

S504, the second adder receives the carry input signal, the carry generation signal and the carry propagation signal and generates a carry output signal sum and output signal based thereon;

s505, the second adder provides a carry output signal to the carry output port and a sum output signal to the fourth multiplexer;

S506, outputting a second value to the fourth multiplexer;

S507, the fourth multiplexer outputs and outputs a signal based on the second value it receives, and outputs the signal to the second output port.

In the execution of step S501, the first value is output to the sixth multiplexer MUX6 through the second static memory SRAM 1.

In the execution of step S502, the sixth multiplexer MUX6 outputs a high level signal to the first adder adder [0] based on the first value. Wherein the high level signal is taken through a first input of a sixth multiplexer MUX 6.

In the execution of step S503, the first adder adder [0] receives the carry input signal CIN, the low-level signal, and the high-level signal through its three inputs, respectively, and outputs the carry input signal CIN based on the three inputs. Wherein the low level signal is obtained by the first multiplexer MUX 1.

In the execution of step S504, the second adder adder [1] receives the carry input signal CIN, the carry generation signal G_i, and the carry propagation signal P_i through its three inputs, respectively, and generates the carry output signal C_i+1 and the sum output signal S_i based on the three inputs. The carry generation signal G_i is obtained through the second multiplexer MUX2, and the carry propagation signal P_i is obtained through the second n-input lookup table LUT (n) -2.

In the execution of step S505, the second adder adder [1] supplies the carry output signal C_i+1 to the carry output port COUT, and supplies the sum output signal S_i to the fourth multiplexer MUX4.

In the execution of step S506, the second value is output to the fourth multiplexer MUX4 through the first static memory SRAM 0.

In the execution of step S507, the fourth multiplexer MUX4 outputs and outputs the signal S_i to the second output port OUT2 based on the second value it receives.

When the look-up table circuit 200 is implemented as a one-bit wide arithmetic carry logic block, the first n-input look-up table LUT (n) -1 may be used independently. The fifth multiplexer MUX5 may select the signal output by the first n-input lookup table LUT (n) -1 received at the first input terminal thereof based on the first value configured by the second static memory SRAM1, and output the signal to the first output port OUT1.

In an implementation, the method 500 further includes:

S508, outputting a first value to a fifth multiplexer;

s509, the fifth multiplexer outputs the output signal of the first n-input lookup table to the first output port based on the first value.

In the execution of step S508, the first value is output to the fifth multiplexer MUX5 through the second static memory SRAM 1.

In the execution of step S509, the fifth multiplexer MUX5 selects the output signal of the first n-input look-up table LUT (n) -1 received at its first input terminal based on the first value, and outputs it to the first output port OUT1.

When the first static memory SRAM0 is configured to a first value (e.g., the first value is 0), the second static memory SRAM1 is configured to a first value (e.g., the first value is 0), and the n+1th address input port IN (n+1) receives a high level signal, the lookup table circuit provided by the embodiment of the present invention may be applied as two n-input lookup tables.

Based thereon, the method 400 or 500 further comprises:

s601, a high level signal is provided to a control end of the third multiplexer through an n+1th address input port;

S602, based on the high level signal, enabling the third multiplexer to output the output signal of the second n-input lookup table to the fourth multiplexer;

S603, outputting a first value to a fourth multiplexer and a fifth multiplexer;

s604, the fourth multiplexer and the fifth multiplexer output the output signal of the second n-input lookup table and the output signal of the first n-input lookup table, respectively, based on the first value;

s605 outputs the output signal of the first n-input lookup table and the output signal of the second n-input lookup table to the first output port and the second output port, respectively.

IN the execution of step S601, a high level signal is input to the n+1th address input port IN (n+1) and output to the control terminal of the third multiplexer MUX 3.

In the execution of step S602, the third multiplexer MUX3 outputs the output signal of the second n-input lookup table LUT (n) -2 received at its second input to the first input of the fourth multiplexer MUX4 based on the high level signal received at its control terminal.

In the execution of step S603, a first value (e.g., a first value of 0) is output to the fourth multiplexer MUX4 through the first static memory SRAM0, and a first value (e.g., a first value of 0) is output to the fifth multiplexer MUX5 through the second static memory SRAM 1.

In the execution of step S604, the fourth multiplexer MUX4 outputs the output signal of the second n-input look-up table LUT (n) -2 received at its first input based on the first value, and the fifth multiplexer MUX5 outputs the output signal of the first n-input look-up table LUT (n) -1 received at its first input based on the first value.

In the execution of step S605, the output signal of the first n-input look-up table LUT (n) -1 is output to the first output port OUT1 through the fifth multiplexer MUX5, and the output signal of the second n-input look-up table LUT (n) -2 is output to the second output port OUT2 through the fourth multiplexer MUX 4.

When the first static memory SRAM0 is configured to a first value (e.g., the first value is 0), the n+1-th address input port IN (n+1) receives the most significant address signal, the lookup table circuit provided by the embodiment of the present invention may be applied as one n+1-input lookup table.

Based thereon, the method 400 or 500 further comprises:

S701, the highest address signal is provided to the control end of the third multiplexer through the n+1th address input port;

S702, enabling the third multiplexer to output a signal received by one of the first input terminal and the second input terminal based on the most significant address signal;

S703 outputting the first value to the fourth multiplexer;

S704, the fourth multiplexer outputs the signal received by the first input terminal thereof to the second output port based on the first value.

IN the execution of step S701, the most significant address signal is input to the n+1th address input port IN (n+1), and output to the control terminal of the third multiplexer MUX 3.

IN the execution of step S702, the third multiplexer MUX3 forms an n+1 input lookup table LUT (n+1) together with the first n input lookup table LUT (n) -1 and the second n input lookup table LUT (n) -2 based on the most significant address signal received from the n+1 address input port IN (n+1), and outputs the output signal of the n+1 input lookup table LUT (n+1).

In the execution of step S703, a first value (for example, a first value of 0) is output to the fourth multiplexer MUX4 through the first static memory SRAM 0.

In the execution of step S704, the fourth multiplexer MUX4 outputs the output signal of the n+1 input look-up table LUT (n+1) to the second output port OUT2 based on the first value.

The method for configuring the lookup table circuit according to the embodiment of the present invention may be implemented based on the foregoing description and the lookup table circuit described in connection with fig. 2 to 4, and therefore, the execution of each step and the relationship between each step in the method may also refer to the foregoing description about the lookup table circuit, which is not repeated herein.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (21)

Translated fromChinese

1.一种查找表电路，其特征在于，包括：1. A lookup table circuit, comprising:二个第一地址输入端口、第二至第n+1地址输入端口、进位输入端口、进位输出端口、第一输出端口和第二输出端口，其中，n为大于或等于5的整数；two first address input ports, second to n+1th address input ports, a carry input port, a carry output port, a first output port, and a second output port, wherein n is an integer greater than or equal to 5;第一n输入查找表和第二n输入查找表，其共用第二至第n地址输入端口，所述第一n输入查找表单独使用所述二个第一地址输入端口中的一者，所述第二n输入查找表单独使用所述二个第一地址输入端口中的另一者；A first n-input lookup table and a second n-input lookup table, which share the second to n-th address input ports, wherein the first n-input lookup table uses only one of the two first address input ports, and the second n-input lookup table uses only the other of the two first address input ports;第一多路选择器的三个输入端分别连接所述二个第一地址输入端口中的一者、电源电压和地；The three input terminals of the first multiplexer are respectively connected to one of the two first address input ports, a power supply voltage and a ground;第二多路选择器的三个输入端分别连接所述二个第一地址输入端口中的另一者、电源电压和地；The three input terminals of the second multiplexer are respectively connected to the other of the two first address input ports, the power supply voltage and the ground;第三多路选择器的第一输入端连接所述第一n输入查找表的输出端，第二输入端连接所述第二n输入查找表的输出端，控制端连接所述第n+1地址输入端口；A first input terminal of the third multiplexer is connected to the output terminal of the first n-input lookup table, a second input terminal is connected to the output terminal of the second n-input lookup table, and a control terminal is connected to the n+1th address input port;第四多路选择器的第一输入端连接所述第三多路选择器的输出端，输出端连接所述第二输出端口；A first input terminal of a fourth multiplexer is connected to an output terminal of the third multiplexer, and an output terminal of the fourth multiplexer is connected to the second output port;第五多路选择器的第一输入端连接所述第一n输入查找表的输出端，输出端连接所述第一输出端口；A first input terminal of a fifth multiplexer is connected to an output terminal of the first n-input lookup table, and an output terminal of the fifth multiplexer is connected to the first output port;第六多路选择器的第一输入端连接电源电压，第二输入端连接所述第一n输入查找表的输出端；A first input terminal of the sixth multiplexer is connected to a power supply voltage, and a second input terminal is connected to an output terminal of the first n-input lookup table;第一加法器的第一输入端连接所述进位输入端口，第二输入端连接所述第一多路选择器的输出端，第三输入端连接所述第六多路选择器的输出端，第一输出端连接所述第五多路选择器的第二输入端；The first adder has a first input terminal connected to the carry input port, a second input terminal connected to the output terminal of the first multiplexer, a third input terminal connected to the output terminal of the sixth multiplexer, and a first output terminal connected to the second input terminal of the fifth multiplexer;第二加法器的第一输入端连接所述第一加法器的第二输出端，第二输入端连接所述第二多路选择器的输出端，第三输入端连接所述第二n输入查找表的输出端，第一输出端连接所述第四多路选择器的第二输入端，第二输出端连接所述进位输出端口。The first input end of the second adder is connected to the second output end of the first adder, the second input end is connected to the output end of the second multiplexer, the third input end is connected to the output end of the second n-input lookup table, the first output end is connected to the second input end of the fourth multiplexer, and the second output end is connected to the carry output port.2.根据权利要求1所述的查找表电路，其特征在于，所述第四多路选择器具有控制端，包括与所述第四多路选择器的控制端连接的第一静态存储器，其适于配置为第一值或第二值，所述第四多路选择器适于基于所述第一值而输出其第一输入端接收的信号、以及基于所述第二值而输出其第二输入端接收的信号。2. The lookup table circuit according to claim 1 is characterized in that the fourth multiplexer has a control end, including a first static memory connected to the control end of the fourth multiplexer, which is suitable for being configured as a first value or a second value, and the fourth multiplexer is suitable for outputting a signal received at its first input end based on the first value, and outputting a signal received at its second input end based on the second value.3.根据权利要求2所述的查找表电路，其特征在于，所述第n+1地址输入端口适于接收高电平信号或者接收最高位地址信号，所述第三多路选择器适于基于所述高电平信号而输出其第二输入端接收的信号、以及基于所述最高位地址信号而输出其第一输入端和第二输入端中的一者所接收的信号。3. The lookup table circuit according to claim 2 is characterized in that the n+1th address input port is suitable for receiving a high-level signal or receiving a highest-order address signal, and the third multiplexer is suitable for outputting a signal received by its second input terminal based on the high-level signal, and outputting a signal received by one of its first input terminal and the second input terminal based on the highest-order address signal.4.根据权利要求2所述的查找表电路，其特征在于，所述第二加法器适于分别接收进位输入信号、进位产生信号和进位传播信号，并基于其得到和输出信号和进位输出信号，所述第二加法器的第一输出端适于输出所述和输出信号，所述第二加法器的第二输出端适于输出所述进位输出信号。4. The lookup table circuit according to claim 2 is characterized in that the second adder is suitable for receiving a carry input signal, a carry generation signal and a carry propagation signal respectively, and obtaining a sum output signal and a carry output signal based thereon, the first output terminal of the second adder is suitable for outputting the sum output signal, and the second output terminal of the second adder is suitable for outputting the carry output signal.5.根据权利要求4所述的查找表电路，其特征在于，所述二个第一地址输入端口中的另一者适于输入第一加数A_i，所述第二至第n地址输入端口中的一个地址输入端口适于输入第二加数B_i，所述第二n输入查找表适于基于所述第一加数A_i和第二加数B_i得到所述进位传播信号并输出至所述第二加法器的第三输入端，所述第二多路选择器适于输出与所述进位传播信号对应的所述进位产生信号至所述第二加法器的第二输入端。5. The lookup table circuit according to claim 4, characterized in that the other of the two first address input ports is suitable for inputting a first addend_Ai , one of the second to n-th address input ports is suitable for inputting a second addend_Bi , the second n-input lookup table is suitable for obtaining the carry propagation signal based on the first addend_Ai and the second addend_Bi and outputting it to the third input terminal of the second adder, and the second multiplexer is suitable for outputting the carry generation signal corresponding to the carry propagation signal to the second input terminal of the second adder.6.根据权利要求4所述的查找表电路，其特征在于，所述进位输入端口适于输出所述进位输入信号，所述第一多路选择器适于选择其接地的第一输入端而输出低电平信号，所述第六多路选择器适于选择其第一输入端而输出高电平信号，所述第一加法器适于基于所述进位输入信号、所述低电平信号和所述高电平信号将所述进位输入信号通过其第二输出端输出至所述第二加法器的第一输入端。6. The lookup table circuit according to claim 4 is characterized in that the carry input port is suitable for outputting the carry input signal, the first multiplexer is suitable for selecting its first input terminal connected to ground and outputting a low level signal, the sixth multiplexer is suitable for selecting its first input terminal and outputting a high level signal, and the first adder is suitable for outputting the carry input signal to the first input terminal of the second adder through its second output terminal based on the carry input signal, the low level signal and the high level signal.7.根据权利要求4所述的查找表电路，其特征在于，所述第五多路选择器适于选择其第一输入端而输出所述第一n输入查找表的输出信号。7 . The lookup table circuit according to claim 4 , wherein the fifth multiplexer is adapted to select its first input terminal to output the output signal of the first n-input lookup table.8.根据权利要求2所述的查找表电路，其特征在于，所述第二加法器适于接收第一进位输出信号、第二进位产生信号和第二进位传播信号，并基于其得到第二和输出信号和第二进位输出信号，所述第二加法器的第一输出端适于输出所述第二和输出信号，所述第二加法器的第二输出端适于输出所述第二进位输出信号。8. The lookup table circuit according to claim 2 is characterized in that the second adder is suitable for receiving a first carry output signal, a second carry generation signal and a second carry propagation signal, and obtaining a second sum output signal and a second carry output signal based thereon, a first output terminal of the second adder is suitable for outputting the second sum output signal, and a second output terminal of the second adder is suitable for outputting the second carry output signal.9.根据权利要求8所述的查找表电路，其特征在于，所述二个第一地址输入端口中的另一者适于输入高位的第一加数A_i+1，所述第二至第n地址输入端口中的另一个地址输入端口适于输入高位的第二加数B_i+1，所述第二n输入查找表适于基于所述高位的第一加数A_i+1和第二加数B_i+1得到所述第二进位传播信号并输出至所述第二加法器的第三输入端，所述第二多路选择器适于输出与所述第二进位传播信号对应的所述第二进位产生信号至所述第二加法器的第二输入端。9. The lookup table circuit according to claim 8 is characterized in that the other of the two first address input ports is suitable for inputting the high-order first addend A_i+1 , the other address input port of the second to n-th address input ports is suitable for inputting the high-order second addend B_i+1 , the second n-input lookup table is suitable for obtaining the second carry propagation signal based on the high-order first addend A_i+1 and the second addend B_i+1 and outputting it to the third input terminal of the second adder, and the second multiplexer is suitable for outputting the second carry generation signal corresponding to the second carry propagation signal to the second input terminal of the second adder.10.根据权利要求8所述的查找表电路，其特征在于，所述进位输入端口适于输出进位输入信号，所述第六多路选择器适于选择其第二输入端而输出第一进位传播信号，所述第一多路选择器适于输出与所述第一进位传播信号对应的第一进位产生信号，所述第一加法器适于基于所述进位输入信号、所述第一进位产生信号和所述第一进位传播信号而得到第一和输出信号和所述第一进位输出信号，所述第一加法器的第一输出端适于输出所述第一和输出信号，所述第二加法器的第二输出端适于输出所述第一进位输出信号至所述第二加法器的第一输入端。10. The lookup table circuit according to claim 8, characterized in that the carry input port is suitable for outputting a carry input signal, the sixth multiplexer is suitable for selecting its second input terminal and outputting a first carry propagation signal, the first multiplexer is suitable for outputting a first carry generation signal corresponding to the first carry propagation signal, the first adder is suitable for obtaining a first sum output signal and the first carry output signal based on the carry input signal, the first carry generation signal and the first carry propagation signal, the first output terminal of the first adder is suitable for outputting the first sum output signal, and the second output terminal of the second adder is suitable for outputting the first carry output signal to the first input terminal of the second adder.11.根据权利要求10所述的查找表电路，其特征在于，所述二个第一地址输入端口中的一者适于输入低位的第一加数A_i，所述第二至第n地址输入端口中的一个地址输入端口适于输入低位的第二加数B_i，所述第一n输入查找表适于基于所述低位的第一加数A_i和第二加数B_i得到所述第一进位传播信号并输出至所述第六多路选择器的第二输入端，所述第一多路选择器适于输出与所述第一进位传播信号对应的所述第一进位产生信号至所述第一加法器的第二输入端。11. The lookup table circuit according to claim 10, characterized in that one of the two first address input ports is suitable for inputting a low-order first addend A_i , one of the second to n-th address input ports is suitable for inputting a low-order second addend B_i , the first n-input lookup table is suitable for obtaining the first carry propagation signal based on the low-order first addend A_i and second addend B_i and outputting it to the second input terminal of the sixth multiplexer, and the first multiplexer is suitable for outputting the first carry generation signal corresponding to the first carry propagation signal to the second input terminal of the first adder.12.根据权利要求6、7、10和11中任一项所述的查找表电路，其特征在于，所述第五多路选择器和所述第六多路选择器分别具有控制端，包括与所述第五多路选择器和所述第六多路选择器的控制端均连接的第二静态存储器，其适于配置为第一值或第二值，所述第五多路选择器适于基于所述第一值而输出其第一输入端接收的信号、以及基于所述第二值而输出其第二输入端接收的信号，所述第六多路选择器适于基于所述第一值而输出其第一输入端接收的信号、以及基于所述第二值而输出其第二输入端接收的信号。12. The lookup table circuit according to any one of claims 6, 7, 10 and 11 is characterized in that the fifth multiplexer and the sixth multiplexer respectively have a control end, including a second static memory connected to the control ends of the fifth multiplexer and the sixth multiplexer, which is suitable for being configured as a first value or a second value, the fifth multiplexer is suitable for outputting a signal received at its first input end based on the first value, and outputting a signal received at its second input end based on the second value, and the sixth multiplexer is suitable for outputting a signal received at its first input end based on the first value, and outputting a signal received at its second input end based on the second value.13.根据权利要求2或12所述的查找表电路，其特征在于，所述第一值为0或1中的一者，所述第二值为0或1中的另一者。13 . The lookup table circuit according to claim 2 , wherein the first value is one of 0 and 1, and the second value is the other of 0 and 1.14.根据权利要求6、10和11中任一项所述的查找表电路，其特征在于，包括第三静态存储器，所述第一多路选择器适于基于所述第三静态存储器的配置而输出相应的进位产生信号。14. The look-up table circuit according to any one of claims 6, 10 and 11, characterized in that it comprises a third static memory, and the first multiplexer is adapted to output a corresponding carry generation signal based on a configuration of the third static memory.15.根据权利要求5或9所述的查找表电路，其特征在于，包括第四静态存储器，所述第二多路选择器适于基于所述第四静态存储器的配置而输出相应的进位产生信号。15 . The lookup table circuit according to claim 5 , further comprising a fourth static memory, wherein the second multiplexer is adapted to output a corresponding carry generation signal based on a configuration of the fourth static memory.16.一种配置如权利要求1至14中任一项所述的查找表电路的方法，其特征在于，包括：16. A method for configuring a lookup table circuit according to any one of claims 1 to 14, comprising:向所述第六多路选择器输出第二值；outputting a second value to the sixth multiplexer;所述第六多路选择器基于所述第二值而向所述第一加法器输出第一进位传播信号；the sixth multiplexer outputting a first carry propagate signal to the first adder based on the second value;所述第一加法器接收进位输入信号、第一进位产生信号和所述第一进位传播信号，并且基于其产生第一进位输出信号和第一和输出信号；The first adder receives a carry input signal, a first carry generate signal, and the first carry propagate signal, and generates a first carry output signal and a first sum output signal based thereon;所述第二加法器接收所述第一进位输出信号、第二进位产生信号和第二进位传播信号，并且基于其产生第二进位输出信号和第二和输出信号；the second adder receiving the first carry output signal, the second carry generate signal and the second carry propagate signal, and generating a second carry output signal and a second sum output signal based thereon;所述第二加法器将所述第二进位输出信号提供至所述进位输出端口；The second adder provides the second carry output signal to the carry output port;所述第一加法器和所述第二加法器分别将所述第一和输出信号和所述第二和输出信号提供至所述第五多路选择器和所述第四多路选择器；The first adder and the second adder provide the first sum output signal and the second sum output signal to the fifth multiplexer and the fourth multiplexer, respectively;向所述第四多路选择器和所述第五多路选择器分别输出各自的第二值；Outputting respective second values to the fourth multiplexer and the fifth multiplexer;所述第四多路选择器和所述第五多路选择器基于各自接收的第二值而分别向所述第二输出端口和所述第一输出端口输出所述第二和输出信号和所述第一和输出信号。The fourth multiplexer and the fifth multiplexer output the second sum output signal and the first sum output signal to the second output port and the first output port, respectively, based on the second values received respectively.17.一种配置如权利要求1至14中任一项所述的查找表电路的方法，其特征在于，包括：17. A method for configuring a lookup table circuit according to any one of claims 1 to 14, comprising:向所述第六多路选择器输出第一值；Outputting the first value to the sixth multiplexer;所述第六多路选择器基于所述第一值而向所述第一加法器输出高电平信号；The sixth multiplexer outputs a high level signal to the first adder based on the first value;所述第一加法器接收所述进位输入信号、低电平信号和所述高电平信号，并且基于其输出所述进位输入信号；The first adder receives the carry-in signal, the low-level signal, and the high-level signal, and outputs the carry-in signal based thereon;所述第二加法器接收所述进位输入信号、进位产生信号和进位传播信号，并且基于其产生进位输出信号和和输出信号；The second adder receives the carry-in signal, the carry-generate signal and the carry-propagate signal, and generates a carry-out signal and a sum-out signal based thereon;所述第二加法器将所述进位输出信号提供至所述进位输出端口，并且将所述和输出信号提供至所述第四多路选择器；The second adder provides the carry output signal to the carry output port and provides the sum output signal to the fourth multiplexer;向所述第四多路选择器输出第二值；outputting a second value to the fourth multiplexer;所述第四多路选择器基于其接收的第二值而输出所述和输出信号，并且向所述第二输出端口输出所述和输出信号。The fourth multiplexer outputs the sum output signal based on the second value received therefrom, and outputs the sum output signal to the second output port.18.根据权利要求17所述的方法，其特征在于，包括：18. The method according to claim 17, characterized in that it comprises:向所述第五多路选择器输出第一值；outputting the first value to the fifth multiplexer;所述第五多路选择器基于所述第一值而向所述第一输出端口输出所述第一n输入查找表的输出信号。The fifth multiplexer outputs an output signal of the first n-input lookup table to the first output port based on the first value.19.根据权利要求16至18种任一项所述的方法，其特征在于，包括：19. The method according to any one of claims 16 to 18, characterized in that it comprises:向所述第四多路选择器输出第一值；outputting the first value to the fourth multiplexer;所述第四多路选择器基于第一值而向所述第二输出端口输出其第一输入端接收的信号。The fourth multiplexer outputs the signal received at its first input terminal to the second output port based on the first value.20.根据权利要求19所述的方法，其特征在于，包括：20. The method according to claim 19, comprising:高电平信号经所述第n+1地址输入端口提供至所述第三多路选择器的控制端；The high level signal is provided to the control terminal of the third multiplexer via the n+1th address input port;基于所述高电平信号使所述第三多路选择器选择其第二输入端而输出所述第二n输入查找表的输出信号至所述第四多路选择器的第一输入端。The third multiplexer selects its second input terminal based on the high level signal and outputs the output signal of the second n-input lookup table to the first input terminal of the fourth multiplexer.21.根据权利要求19所述的方法，其特征在于，包括：21. The method according to claim 19, comprising:最高位地址信号经所述第n+1地址输入端口提供至所述第三多路选择器的控制端；The highest address signal is provided to the control terminal of the third multiplexer via the n+1th address input port;基于所述最高位地址信号而使所述第三多路选择器输出其第一输入端和第二输入端中的一者所接收的信号至所述第四多路选择器的第一输入端。The third multiplexer outputs a signal received at one of its first input terminal and second input terminal to the first input terminal of the fourth multiplexer based on the highest address signal.