Disclosure of Invention
The invention aims at overcoming the defects of the prior art, and provides a method and a system for realizing the shaping of gigabit Ethernet data traffic by FPGA, receiving data for gigabit Ethernet receiving end, and when the data is forwarded, the data sent to the output end needs to be subjected to flow control, and the method for shaping the instant bandwidth flow of the data in output according to the requirement of the output side.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
A system for realizing gigabit Ethernet data traffic shaping through FPGA comprises an FPGA module, a DDR3 memory module, a user side gigabit Ethernet GEPHY access module and a system side gigabit Ethernet GEPHY access module; the FPGA module is respectively connected with the DDR3 storage module, the user side gigabit Ethernet GEPHY access module and the system side gigabit Ethernet GEPHY access module;
the user side gigabit Ethernet GEPHY access module is used for receiving the Ethernet data input by the user port and converting the received Ethernet data into RGMII format data identified by the FPGA module;
The FPGA module is used for acquiring data in an RGMII format, carrying out flow shaping processing on the acquired data, and caching the processed data into the DDR3 memory module;
The DDR3 storage module is used for receiving and storing the data processed by the FPGA module;
And the system side gigabit Ethernet GEPHY access module is used for reading the data in the DDR3 memory module through the FPGA module and outputting the read data.
Further, the system side gigabit Ethernet GEPHY access module is further configured to receive data input by a system port, and convert the received data into RGMII format data identified by the FPGA module;
the user side gigabit Ethernet GEPHY access module is also used for reading the data in the DDR3 memory module through the FPGA module and outputting the read data.
Further, the FPGA module comprises an RGMII module, an Ethernet data processing module and a memory gating module; the Ethernet data processing module is respectively connected with the RGMII module and the memory gating module;
the RGMII module is used for analyzing the Ethernet data according to the standard Ethernet protocol to obtain the Ethernet data message and judging whether the obtained Ethernet data message is a correct message or not;
the Ethernet data processing module synchronizes data to a local processing clock by adopting the FIFO memory if the data is a correct message, and reads the Ethernet data in the FIFO memory after receiving a complete Ethernet data message;
and the memory gating module is used for storing the read Ethernet data.
Furthermore, the ethernet data processing module is further configured to record the length of the data frame, and record the address cached by the DDR3 memory module.
Further, the FPGA module further comprises a DDR control interface module, and the DDR control interface module is respectively connected with the memory gating module and the DDR3 storage module;
And the DDR control interface module is used for reading or writing data.
Further, the system also comprises a management control CPU module which is connected with the FPGA module and is used for carrying out configuration management on the FPGA module.
Furthermore, the gigabit Ethernet GEPHY access module at the user side and the gigabit Ethernet GEPHY access module at the system side in the system are all 4 paths.
Further, the FPGA module adopts a chip with the model of GW 2A-18; the DDR3 memory module adopts a chip with the model of H5TQ2G 63.
Correspondingly, a method for realizing gigabit Ethernet data traffic shaping through the FPGA is also provided, which comprises the following steps:
S1, after a gigabit Ethernet GEPHY access module at a user side receives Ethernet data input by a user port, converting the received Ethernet data into RGMII format data identified by an FPGA module;
s2, the FPGA module acquires data in an RGMII format, performs flow shaping processing on the acquired data, and caches the processed data into the DDR3 memory module;
S3, the DDR3 storage module receives and stores the data processed by the FPGA module;
S4, the system side gigabit Ethernet GEPHY access module reads data in the DDR3 memory module through the FPGA module and outputs the read data.
Further, the method further comprises the following steps:
After receiving data input by a system port, the system side gigabit Ethernet GEPHY access module converts the received data into RGMII format data identified by the FPGA module;
And the user side gigabit Ethernet GEPHY access module reads the data in the DDR3 memory module through the FPGA module and outputs the read data.
Compared with the prior art, the invention can realize the flow shaping control of the multi-gigabit Ethernet input interface, equalize the data burst in short time, reduce the instantaneous bandwidth pressure, lead the Ethernet data, especially can relieve the bandwidth pressure of the Ethernet data interface for video transmission and solve the instantaneous data pressure.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
The invention aims at overcoming the defects of the prior art, and provides a method and a system for realizing gigabit Ethernet data traffic shaping through an FPGA, which realize the bandwidth use condition of input port network access data, and simultaneously combine with the configuration management of a CPU (Central processing Unit), dynamically adjust the occupation of the output port network bandwidth, and ensure that the output data is balanced under the condition of not discarding the data.
Example 1
The embodiment provides a system for realizing gigabit Ethernet data traffic shaping through an FPGA, as shown in FIG. 1, which comprises an FPGA module 11, a DDR3 storage module 12, a plurality of user side gigabit Ethernet GEPHY access modules 13, a plurality of system side gigabit Ethernet GEPHY access modules 14 and a management control CPU module 15; the FPGA module 11 is respectively connected with the DDR3 storage module 12, the plurality of user side gigabit Ethernet GEPHY access modules 13, the plurality of system side gigabit Ethernet GEPHY access modules 14 and the management control CPU module 15.
The system for realizing gigabit ethernet data traffic shaping through FPGA of the embodiment may be configured to receive data input by a user terminal and output the data from the system terminal; or the data input by the system end can be received and output from the user end.
In this embodiment, data input from the user terminal is received, and output from the system terminal is taken as an example to describe in detail.
And the user side gigabit Ethernet GEPHY access module 13 is used for receiving the Ethernet data input by the user port and converting the received Ethernet data into RGMII format data identified by the FPGA module.
The gigabit ethernet GEPHY access module 13 at the user side in this embodiment is the same 4-path gigabit ethernet interface at the user side, and the transmission mode and the processing mode of each path are the same, so as to provide an independent 4-path gigabit ethernet access function; the present embodiment is specifically described by taking one of them as an example.
The user access port #1 in fig. 1 receives ethernet data, and after receiving the ethernet data, the ethernet data is converted into interface data in RGMII format that can be identified by the FPGA module 11 through the gigabit ethernet GEPHY access module 13 at the user side.
The FPGA module 11 is configured to obtain RGMII format data, perform traffic shaping processing on the obtained data, and cache the processed data in the DDR3 memory module.
As shown in fig. 2, the FPGA module 11 includes a plurality of RGMII modules, a plurality of ethernet data processing modules, and a memory gating module; the Ethernet data processing module is respectively connected with the RGMII module and the memory gating module.
In this embodiment, the number of RGMII modules is twice that of ethernet data processing modules, and the number of ethernet data processing modules is the same as that of gigabit ethernet GEPHY access modules on the user side and that of gigabit ethernet GEPHY access modules on the system side; each gigabit Ethernet GEPHY access module at the user side is connected with one RGMII module, and each gigabit Ethernet GEPHY access module at the system side is also connected with one RGMII module.
The RGMII module is used for analyzing the Ethernet data according to the standard Ethernet protocol to obtain the Ethernet data message and judging whether the obtained Ethernet data message is a correct message or not;
When the received data is processed through an RGMII module connected with a gigabit Ethernet GEPHY access module at the user side, the received data corresponding to the data is analyzed according to a standard Ethernet protocol; judging whether the analyzed Ethernet message is a correct message or not, if not, discarding the message if the error occurs in the transmission process; if the message is correct, the message is transmitted to an Ethernet data processing module to realize further processing.
The Ethernet data processing module synchronizes data to a local processing clock by adopting the FIFO memory if the data is a correct message, and reads the Ethernet data in the FIFO memory after receiving a complete Ethernet data message;
After the Ethernet data processing module receives the message input by the RGMII module, an on-chip FIFO memory is adopted first) synchronizes the data to a local processing clock, and after a complete data message is received, the data is read out from the FIFO memory and output to the memory gating module, so that the cache of the on-board DDR3 memory module is realized. Meanwhile, the Ethernet data processing module records the length of a data frame and is used for referring to the data quantity when the data is read out from the DDR3 memory module. And recording the address cached by the DDR3 memory module, and preparing for shaping the data output bandwidth control flow during transmission.
And the memory gating module is used for storing the read Ethernet data.
In this embodiment, the FPGA module further includes a DDR control interface module, where the DDR control interface module is connected to the memory strobe module and the DDR3 memory module, respectively;
And the DDR control interface module is used for reading or writing data.
In order to reduce the time sequence pressure of designing the FPGA, the DDR control interface module adopts 128 bits for the internal data bit width, namely, realizes that 16 bytes of data are read and written by 1 clock. The memory gating module completes the selection and switching functions of the 4-way Ethernet processing module when the DDR3 memory module is accessed in a read-write mode. The method is characterized in that the operation authority of the DDR control interface module is endowed to a certain path determined in the 4-path Ethernet processing module at a certain moment in a gating mode.
For writing operation, a writing instruction, a writing address and writing data of data are simultaneously transmitted to the DDR3 control interface module in the same direction, and after receiving the operation instruction, the DDR3 control interface module writes the data into the DDR3 storage module.
For a read operation, a read command and a read address are output, and then data is given from the DDR3 memory module.
Through testing, the maximum clock delay is 90 clocks from the time the read command is given to the time the data is received. In a read operation, if 512 bytes of data are read, the data operation valid clocks are 32, but the total clocks of the operation will be as many as 112, in which case the bandwidth utilization of the DDR3 memory module is less than 28%, and in which case the data operation bandwidth in the DDR3 memory module will not reach the 75% minimum bandwidth utilization previously described. Therefore, the channel can not be switched after the data is read and written, but the switching operation of the channel issued by the read instruction is separated from the switching operation of the data reading and outputting.
The specific implementation mode is as follows: the memory gating module adopts a state machine to round 4 paths of read-write instructions of the Ethernet processing module, when the state machine turns to detect that a read-write request exists on a certain path, the state machine is locked, and the DDR3 control interface module is endowed with the operation authority of the channel. When the read-write instruction is sent, the Ethernet processing module immediately releases the read-write operation authority, and the state machine enters the operation of the next path. If the operation is a read operation, the actual read data is not returned to the DDR3 control interface module. The processing mechanism for reading the returned data is now enabled. When no read operation instruction exists in 128 clocks and the DDR3 control interface module does not return effective read effective data, the data return state machine enters an idle state, all counters are cleared, and even if abnormality occurs in operation, the method can return to normal. Then if the memory gating module receives the read command, recording which module the read command is sent by, and recording the data needing to read out a plurality of clocks at the same time; continuously, the memory gating module continues to receive the read command, continues to record which module the read command is issued by, needs to read data of multiple clocks, and so on. At the same time, the memory strobe module stores the read command requests and the data quantity of the requests of the multiple channels, and the DDR3 control interface module finally reads the data from the DDR3 memory module and then transmits the data to the DDR3 control interface module. The DDR3 control interface module returns read data to the appointed channel in sequence according to the recorded channel number and the requested data quantity. Therefore, the actual use data bandwidth of DDR3 is effectively improved.
By the method, the traffic shaping control of the 4-path gigabit Ethernet interface can be realized through the FPGA.
The FPGA module of the embodiment adopts a chip with the model of GW2A-18, and the FPGA chip is a core component of the scheme, so that the access of 4 paths of gigabit Ethernet at a user side, the access of 4 paths of Ethernet at a system side, the control management of DDR3 interfaces and the processing of all services are completed.
The DDR3 memory module 12 is used for receiving and storing the data processed by the FPGA module.
The DDR3 memory module adopts a chip with the model of H5TQ2G63 to realize on-chip cache of the received Ethernet service data.
The DDR3 memory module has capacity of 2Gbit and 256Mbyte. The capacity is equally divided into 16 equal parts, each with 16 mbytes, and one buffer space block is used for buffering data frames in one direction. Each buffer space block is then subdivided into small spaces of 2 kbytes capacity, one for each buffer of 1 frame data. This may enable the buffering of 8192 data frames per direction.
Because the length range of the Ethernet frame is 64-1518 bytes, in order to improve the space utilization rate and the bandwidth utilization rate of the DDR3 memory module, a plurality of packets with smaller length are spliced into a packet with larger length for centralized storage and forwarding. The length of the spliced data packet cannot exceed the capacity of 1 storage small space, so the length of the splice is limited.
When the length of the complete data frame received by the current FPGA module is smaller than 512 bytes (the maximum is 530 bytes), splicing the next data frame to the tail end of the previous frame to form a new data frame with a new length, adopting a frame interval identifier between the two frames, and decomposing the two frames into a plurality of original data frames according to the frame interval during transmission. If the length of the spliced plurality of data frames is still smaller than 512 bytes, a next new data frame is spliced continuously until the length is larger than 512 bytes. When the spliced data frames are stored and forwarded in the FPGA, the spliced data frames are regarded as a whole, the frame length is the whole length, and the DDR3 memory module takes the length as a reference when writing and reading operations are performed. In addition, if the data buffered in the buffer space is less than 512 bytes, but no new ethernet frame is received in the next 1 microsecond time, the data frame splicing operation is interrupted, the received data content is treated as 1 complete data frame, and a great time delay is avoided from the last received data frame.
The Ethernet processing module in the FPGA module continuously receives the Ethernet data frames and simultaneously continuously transmits the data frames, and according to the address of the write operation DDR3 memory module and the address of the read operation DDR3 memory module, the number of the data frames which are cached in the DDR3 can be calculated. The speed of transmission is dynamically controlled according to the number of buffered data frames. Currently, control is performed in such a way that when the number of data frames in the DDR3 memory module is less than 32 frames, the read logic performs data transmission at a time interval of reading 1 frame every 1 millisecond, and when 1 exponential level is added, 1 data frame is added every 1 millisecond, and each packet is uniformly transmitted according to time when being transmitted. As shown in table 1 below:
TABLE 1
| Sequence number | Buffer frame number | 1Ms transmission frame number/frame | Transmission data bandwidth/Mbit |
| 1 | 0-31 | 1 | ≤12 |
| 2 | 32-63 | 2 | ≤24 |
| 3 | 64-127 | 3 | ≤36 |
| 4 | 128-255 | 4 | ≤48 |
| 5 | 256-511 | 5 | ≤60 |
| 6 | 512-1023 | 6 | ≤72 |
| 7 | 1024-2047 | 7 | ≤84 |
| 8 | 2048-4090 | 8 | ≤96 |
| 9 | ≥4091 | 9 | 1000 |
And the system side gigabit Ethernet GEPHY access module 14 is used for reading the data in the DDR3 memory module through the FPGA module and outputting the read data.
The system side gigabit Ethernet GEPHY access module is the same 4-way system side gigabit Ethernet interface, provides an independent 4-way gigabit Ethernet output function, corresponds to the 4-way gigabit Ethernet interface of the user side one to one, and realizes the transparent transmission function of data; the present embodiment is specifically described by taking one of them as an example.
When the Ethernet data processing module detects that data is cached in the DDR3 storage module, a data sending mechanism is started, the data is read from the DDR3 storage module according to a certain bandwidth control mechanism, and then is transmitted to the RGMII module connected with the system side gigabit Ethernet GEPHY access module to be recombined into an Ethernet frame, and the Ethernet frame is sent out through the system side gigabit Ethernet GEPHY access module.
And the management control CPU module 15 is used for carrying out configuration management on the FPGA module.
After the data received by the gigabit Ethernet GEPHY access module at the user side is subjected to FPGA cache processing and flow shaping, the data is output to the port of the gigabit Ethernet GEPHY access module at the system side at a designated moment according to the requirement of output bandwidth.
Correspondingly, the data input by the receiving system end in the embodiment is specifically output from the user end as follows:
The system side gigabit Ethernet GEPHY access module 14 is used for receiving data input by a system port and converting the received data into RGMII format data identified by the FPGA module;
The FPGA module 11 is used for acquiring data in an RGMII format, carrying out flow shaping processing on the acquired data, and caching the processed data into the DDR3 memory module;
the DDR3 memory module 12 is used for receiving and storing the data processed by the FPGA module;
and the user side gigabit Ethernet GEPHY access module 13 is used for reading the data in the DDR3 memory module through the FPGA module and outputting the read data.
The process flow of forwarding the data received from the system access port to the service side is the same as the process flow of forwarding the data received from the service access port to the system side, and this embodiment will not be described in detail.
After the data received by the gigabit Ethernet GEPHY access module port at the system side is subjected to the FPGA cache processing, the data is output to the gigabit Ethernet GEPHY access module port at the user side at the designated moment according to the requirement of output bandwidth.
The processing manners of the other three ports in this embodiment are the same, and will not be described in detail.
In this embodiment, data storage forwarding is performed between 4 service ports and 4 system ports, so that data storage is required in 8 directions. After the stored data is received by the receiving port, the data is written into the DDR3 chip, and then the data is read out and output to the sending port, so that the effective data read-write bandwidth of the DDR3 is larger than 16Gbit in order to realize timely data writing into the cache and data reading out from the cache. The operating clock frequency of DDR3 is chosen to be 1333Mhz in design, and the bandwidth utilization rate of DDR3 is not less than 75 percent.
Example two
The embodiment provides a method for realizing gigabit Ethernet data traffic shaping through an FPGA, which comprises the following steps:
S1, after a gigabit Ethernet GEPHY access module at a user side receives Ethernet data input by a user port, converting the received Ethernet data into RGMII format data identified by an FPGA module;
s2, the FPGA module acquires data in an RGMII format, performs flow shaping processing on the acquired data, and caches the processed data into the DDR3 memory module;
S3, the DDR3 storage module receives and stores the data processed by the FPGA module;
S4, the system side gigabit Ethernet GEPHY access module reads data in the DDR3 memory module through the FPGA module and outputs the read data.
Further, the method further comprises the following steps:
After receiving data input by a system port, the system side gigabit Ethernet GEPHY access module converts the received data into RGMII format data identified by the FPGA module;
And the user side gigabit Ethernet GEPHY access module reads the data in the DDR3 memory module through the FPGA module and outputs the read data.
It should be noted that, a method for implementing gigabit ethernet data traffic shaping by FPGA in this embodiment is similar to the embodiment, and will not be described in detail herein.
Compared with the prior art, the method and the device can realize flow shaping control of the multi-channel gigabit Ethernet input interface, equalize data burst in short time, reduce instantaneous bandwidth pressure, enable Ethernet data, and particularly can relieve the bandwidth pressure of the Ethernet data interface for video transmission and solve the instantaneous data pressure.
The specific embodiments described herein are offered by way of example only to illustrate the spirit of the invention. Those skilled in the art may make various modifications or additions to the described embodiments or substitutions thereof without departing from the spirit of the invention or exceeding the scope of the invention as defined in the accompanying claims.