CN114500385A - Method and system for realizing gigabit Ethernet data traffic shaping through FPGA - Google Patents

Abstract

The invention discloses a system and a method for realizing gigabit Ethernet data traffic shaping through an FPGA (field programmable gate array), wherein the related system comprises an FPGA module, a DDR3 storage module, a user side gigabit Ethernet GEPHY (gigabit Ethernet GEPHY) access module and a system side gigabit Ethernet GEPHY access module; the FPGA module is respectively connected with the DDR3 storage module, the user side gigabit Ethernet GEPHY access module and the system side gigabit Ethernet GEPHY access module; the user side gigabit Ethernet GEPHY access module is used for receiving the Ethernet data input by the user port and converting the received Ethernet data into RGMII format data identified by the FPGA module; the FPGA module is used for acquiring data in an RGMII format, performing flow shaping processing on the acquired data, and caching the processed data into the DDR3 storage module; the DDR3 storage module is used for receiving and storing the data processed by the FPGA module; and the system side gigabit Ethernet GEPHY access module is used for reading the data in the DDR3 storage module through the FPGA module and outputting the read data.

Description

Method and system for realizing gigabit Ethernet data traffic shaping through FPGA

Technical Field

The invention relates to the technical field of Ethernet access and control service management, in particular to a method and a system for realizing gigabit Ethernet data traffic shaping through an FPGA (field programmable gate array).

Background

Network traffic control is a method for controlling network traffic by using computer software or special equipment. In the process of data transmission and reception, it is likely that the receiver or the transmission network is not as good as receiving all the data of the sender, and at this time, both the sender and the receiver need to be controlled to avoid data loss.

The existing scheme I is as follows: the transmission bandwidth of the port or the service is limited through the network equipment, so that the service is transmitted on a transmission network by adopting the bandwidth which does not exceed the upper limit;

the first existing scheme has the following disadvantages: when network bandwidth is congested, bandwidth limitation on service is a common scheme. After the limitation, the service can only communicate with a bandwidth smaller than the set bandwidth, and even if the total transmission bandwidth is idle, the service cannot be allocated with more bandwidth for service use, and especially when the traffic is bursty, packet loss is likely to be caused greatly.

The existing scheme is as follows: time Sensitive Networks (TSNs) provide distributed time synchronization and deterministic communication using standard ethernet. TSN eliminates the non-determinism of standard ethernet due to traffic "congestion" and enables traffic.

The second existing scheme has the following defects: time Sensitive Networks (TSNs) are the new technology standard which is popular at present, and the important problem is that fewer chip solutions can be provided and the cost of implementation is high. When accessing a network, a sending end and a receiving end need to support the protocol of the TSN, and when the existing service device accesses, the function of the TSN network cannot be realized due to the fact that the original device does not support the TSN protocol, and further the advantage brought by the TSN cannot be experienced.

For this reason, it is necessary to design it newly to overcome the above-mentioned disadvantages.

Disclosure of Invention

The invention aims to provide a method and a system for realizing gigabit Ethernet data flow shaping through an FPGA (field programmable gate array), and provides a method for controlling the flow of data sent to an output end when a gigabit Ethernet receiving end receives the data and forwards the data, and shaping the real-time bandwidth flow of the data during output according to the requirement of the output side.

In order to achieve the purpose, the invention adopts the following technical scheme:

a system for realizing gigabit Ethernet data traffic shaping through an FPGA comprises an FPGA module, a DDR3 storage module, a user side gigabit Ethernet GEPHY access module and a system side gigabit Ethernet GEPHY access module; the FPGA module is respectively connected with the DDR3 storage module, the user side gigabit Ethernet GEPHY access module and the system side gigabit Ethernet GEPHY access module;

the user side gigabit Ethernet GEPHY access module is used for receiving the Ethernet data input by the user port and converting the received Ethernet data into RGMII format data identified by the FPGA module;

the FPGA module is used for acquiring data in an RGMII format, performing flow shaping processing on the acquired data, and caching the processed data into the DDR3 storage module;

the DDR3 storage module is used for receiving and storing the data processed by the FPGA module;

and the system side gigabit Ethernet GEPHY access module is used for reading the data in the DDR3 storage module through the FPGA module and outputting the read data.

Further, the system-side gigabit ethernet GEPHY access module is further configured to receive data input by a system port, and convert the received data into data in an RGMII format recognized by the FPGA module;

the user-side gigabit Ethernet GEPHY access module is also used for reading data in the DDR3 storage module through the FPGA module and outputting the read data.

Furthermore, the FPGA module comprises an RGMII module, an Ethernet data processing module and a memory gating module; the Ethernet data processing module is respectively connected with the RGMII module and the memory gating module;

the RGMII module is used for analyzing the Ethernet data according to the protocol of the standard Ethernet to obtain the data message of the Ethernet and judging whether the obtained Ethernet data message is the correct message or not;

the Ethernet data processing module adopts an FIFO memory to synchronize data to a local processing clock if the message is a correct message, and reads the Ethernet data in the FIFO memory after receiving a complete Ethernet data message;

and the memory gating module is used for storing the read Ethernet data.

Further, the ethernet data processing module is further configured to record the length of the data frame, and record the address cached by the DDR3 storage module.

Furthermore, the FPGA module also comprises a DDR control interface module, and the DDR control interface module is respectively connected with the memory gating module and the DDR3 storage module;

and the DDR control interface module is used for reading or writing data.

And the management control CPU module is connected with the FPGA module and is used for carrying out configuration management on the FPGA module.

Furthermore, a user-side gigabit Ethernet GEPHY access module and a system-side gigabit Ethernet GEPHY access module in the system are 4 paths.

Furthermore, the FPGA module adopts a chip with the model of GW 2A-18; the DDR3 memory module adopts a chip with the model number H5TQ2G 63.

Correspondingly, a method for realizing gigabit Ethernet data traffic shaping through an FPGA is also provided, and the method comprises the following steps:

s1, after receiving Ethernet data input by a user port, a gigabit Ethernet GEPHY access module at a user side converts the received Ethernet data into RGMII format data identified by an FPGA module;

s2, the FPGA module acquires data in an RGMII format, performs flow shaping processing on the acquired data, and caches the processed data to a DDR3 storage module;

s3, receiving and storing the data processed by the FPGA module by the DDR3 storage module;

and S4, the gigabit Ethernet GEPHY access module at the system side reads the data in the DDR3 storage module through the FPGA module and outputs the read data.

Further, the method also comprises the following steps:

after the gigabit Ethernet GEPHY access module on the system side receives data input by a system port, the received data is converted into data in an RGMII format identified by the FPGA module;

the gigabit Ethernet GEPHY access module at the user side reads data in the DDR3 storage module through the FPGA module and outputs the read data.

Compared with the prior art, the method can realize the flow shaping control of the multipath gigabit Ethernet input interface, balance the short-time burst data, reduce the instantaneous bandwidth pressure, relieve the bandwidth pressure of the Ethernet data, particularly the Ethernet data interface for video transmission, and solve the instantaneous data pressure.

Drawings

Fig. 1 is a system structure diagram for implementing gigabit ethernet data traffic shaping by an FPGA according to an embodiment;

fig. 2 is a block diagram of an FPGA module according to an embodiment.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.

The invention aims to provide a method and a system for realizing gigabit Ethernet data flow shaping through an FPGA (field programmable gate array), which aim to realize the bandwidth use condition of input port network access data, and simultaneously combine the configuration management of a CPU (central processing unit) to dynamically adjust the network bandwidth occupation of an output port, thereby ensuring that the output data is relatively balanced under the condition of not discarding the data.

Example one

The embodiment provides a system for realizing gigabit ethernet data traffic shaping through an FPGA, as shown in fig. 1, including anFPGA module 11, aDDR3 storage module 12, a plurality of user-side gigabit ethernetGEPHY access modules 13, a plurality of system-side gigabit ethernetGEPHY access modules 14, and a managementcontrol CPU module 15; theFPGA module 11 is connected to theDDR3 storage module 12, the plurality of user-side gigabit ethernetGEPHY access modules 13, the plurality of system-side gigabit ethernetGEPHY access modules 14, and the managementcontrol CPU module 15, respectively.

In the system for realizing gigabit ethernet data traffic shaping through the FPGA of this embodiment, data input by a user terminal is received and output from a system terminal; or receiving the data input by the system end and outputting the data from the user end.

The present embodiment will be described in detail by taking an example of receiving data input from a user side and outputting the data from a system side.

And the user side gigabit ethernetGEPHY access module 13 is configured to receive ethernet data input by the user port, and convert the received ethernet data into data in an RGMII format identified by the FPGA module.

The user-side gigabit ethernetGEPHY access module 13 in this embodiment is a same 4-way user-side gigabit ethernet interface, and the transmission mode and the processing mode of each way are the same, providing an independent 4-way gigabit ethernet access function; this embodiment is specifically described by taking one path as an example.

For example, the useraccess port #1 in fig. 1 receives ethernet data, and after receiving the ethernet data, the ethernet data is converted into interface data in RGMII format that can be recognized by theFPGA module 11 through the gigabit ethernetGEPHY access module 13 on the user side.

TheFPGA module 11 is configured to acquire data in an RGMII format, perform traffic shaping processing on the acquired data, and cache the processed data in the DDR3 storage module.

As shown in fig. 2, theFPGA module 11 includes a plurality of RGMII modules, a plurality of ethernet data processing modules, and a memory gating module; the Ethernet data processing module is respectively connected with the RGMII module and the memory gating module.

In this embodiment, the number of RGMII modules is twice that of ethernet data processing modules, and the number of ethernet data processing modules is the same as the number of gigabit ethernet GEPHY access modules on the user side and the number of gigabit ethernet GEPHY access modules on the system side; each user-side gigabit ethernet GEPHY access module is connected to one RGMII module, and each system-side gigabit ethernet GEPHY access module is also connected to one RGMII module.

The RGMII module is used for analyzing the Ethernet data according to the protocol of the standard Ethernet to obtain the data message of the Ethernet and judging whether the obtained Ethernet data message is the correct message or not;

after receiving the data, processing the data through an RGMII module connected with a gigabit Ethernet GEPHY access module at a user side, specifically, analyzing an Ethernet data message corresponding to the received data according to a protocol of a standard Ethernet; judging whether the analyzed Ethernet message is a correct message or not, if not, namely, the message is discarded if an error occurs in the transmission process; if so, the message is transmitted to the Ethernet data processing module to realize further processing.

The Ethernet data processing module adopts an FIFO memory to synchronize data to a local processing clock if the message is a correct message, and reads the Ethernet data in the FIFO memory after receiving a complete Ethernet data message;

after receiving the message input by the RGMII module, the ethernet data processing module first uses the on-chip FIFO memory) to synchronize the data to the local processing clock, and when receiving a complete data message, reads the data from the FIFO memory and outputs the data to the memory gating module, thereby realizing the cache of the on-board DDR3 memory module. Meanwhile, the Ethernet data processing module records the length of a data frame for reference of the data when the data is read out from the DDR3 storage module. And records the address cached by the DDR3 memory module for preparation of data output bandwidth control traffic shaping when sending.

And the memory gating module is used for storing the read Ethernet data.

In this embodiment, the FPGA module further includes a DDR control interface module, and the DDR control interface module is connected to the memory gating module and the DDR3 storage module respectively;

and the DDR control interface module is used for reading or writing data.

In order to reduce the time sequence pressure of FPGA design during design of the DDR control interface module, 128 bits are adopted for the internal data bit width, and therefore 1 clock is used for reading and writing 16 bytes of data. The memory gating module completes the selection and switching function when the 4-path Ethernet processing module accesses the DDR3 memory module in a reading and writing mode. And the operation authority of the DDR control interface module is endowed to a certain path determined in the 4 paths of Ethernet processing modules at a certain moment by a gating mode.

For write operation, a write command, a write address and write data of the data are simultaneously transmitted to the DDR3 control interface module in the same direction, and after receiving the operation command, the DDR3 control interface module writes the data into the DDR3 storage module.

For a read operation, a read command, a read address, and then data are given from the DDR3 memory module.

The maximum clock delay from the time a read command is given to the time data is received has been tested to be 90 clocks. In a read operation, if 512 bytes of data are read, the effective clock of the data operation is 32, but the total clock of the operation is as much as 112 at least, in this case, the bandwidth utilization rate of the DDR3 memory module is less than 28%, and if the bandwidth of the data operation in the DDR3 memory module is not up to the aforementioned 75% minimum bandwidth utilization rate. Therefore, the channel switching operation after the data is read and written cannot be considered during the design, but the switching operation of the read instruction issuing channel is separated from the switching operation of the data reading output.

The specific implementation mode is as follows: the memory gating module adopts a state machine to circularly follow the read-write instruction of the 4 paths of Ethernet processing modules, when the state machine detects that a certain path has a read-write request, the state machine locks, and assigns the operation authority of the DDR3 control interface module to the path. After the read-write command is sent, the Ethernet processing module immediately releases the read-write operation authority, and the state machine enters the next path of operation. If it is a write operation then the operation ends and if it is a read operation, the actual read data is not returned from the DDR3 control interface module to the module. The processing mechanism for reading the return data is enabled at this time. When no read operation instruction exists in 128 clocks and the DDR3 control interface module does not return valid read valid data, the data return state machine enters an idle state, all counters are cleared, and even if abnormality occurs in operation, the method can return to normal. If the memory gating module receives a read instruction, recording which module the read instruction is sent out, and simultaneously recording data needing to read a plurality of clocks; continuously, the memory gating module will continue to receive the read command, continue to record which module the read command is issued by, need to read data of multiple clocks, and so on. At this same time, the memory strobe module stores the read command requests and the requested data amount of the multiple channels, and at this time, the DDR3 control interface module finally reads the data from the DDR3 memory module and then transmits the data to the DDR3 control interface module. The DDR3 control interface module will return read data to the designated channel in turn according to the recorded channel number and the requested data amount. This effectively increases the actual data bandwidth used by theDDR 3.

By the mode, the flow shaping control of the 4-path gigabit Ethernet interface can be realized through the FPGA.

The FPGA module of this embodiment uses a chip with a model number of GW2A-18, and the FPGA chip is a core component of this solution, and completes access to a 4-way gigabit ethernet on a user side, access to a 4-way ethernet on a system side, control management of a DDR3 interface, and processing of all services.

And theDDR3 storage module 12 is used for receiving and storing the data processed by the FPGA module.

The DDR3 storage module adopts a chip with the model of H5TQ2G63 to realize on-chip cache of the received Ethernet service data.

The capacity of the DDR3 memory module is 2Gbit, and 256Mbyte is provided. The capacity is equally divided into 16 equal parts, each space is 16Mbyte, and one buffer space block is used for buffering data frames in one direction. Each buffer space block is then subdivided into small spaces with a capacity of 2Kbyte, each space being used for buffering 1 frame data. This allows 8192 data frames per direction to be buffered.

Because the length range of the Ethernet frame is 64-1518 bytes, in order to improve the space utilization rate and the bandwidth utilization rate of the DDR3 storage module, a plurality of packets with smaller lengths are spliced into a packet with larger length to be stored and forwarded in a centralized manner. The length of the spliced data packet cannot exceed the capacity of 1 small storage space, so the length of the splice is limited.

The specific implementation method is that when the length of a complete data frame received by the current FPGA module is less than 512 bytes (maximum 530 bytes), the next data frame is spliced to the end of the previous frame to form a data frame with a new length, a frame interval mark is adopted between the two frames, and the two frames are decomposed into a plurality of original data frames according to the frame interval when being sent. If the length of the spliced data frames is still less than 512 bytes, the next new data frame is spliced until the length is greater than 512 bytes. When the spliced data frames are stored and forwarded in the FPGA, the data frames are regarded as a whole, the length of the frame is the length of the whole, and the DDR3 storage module takes the length as reference when writing and reading operations are carried out. In addition, if the data cached in the cache space is less than 512 bytes, but no new ethernet frame is received in the next 1 microsecond, the data frame splicing operation is interrupted, the received data content is treated as 1 complete data frame, and the great time delay generated by the last received data frame is avoided.

The Ethernet processing module in the FPGA module continuously receives the Ethernet data frames and simultaneously continuously sends the data frames, and according to the address of the write operation DDR3 storage module and the address of the read operation DDR3 storage module, the number of the data frames which are cached in the DDR3 can be calculated. And dynamically controlling the sending speed according to the number of the buffered data frames. At present, the control is performed in the following manner, when the number of data frames in the DDR3 storage module is less than 32 frames, the read logic performs data transmission according to a time interval of reading 1 frame every 1 millisecond, when every 1 exponential level is added, the number of data frames transmitted every 1 millisecond is increased by 1, and each packet is uniformly transmitted according to time when being transmitted. As shown in table 1 below:

TABLE 1

Serial number	Number of buffer frames	1ms Transmission frame number/frame	Transmission data Bandwidth/Mbit
				1	0-31	1	≤12
2	32-63	2	≤24
				3	64-127	3	≤36
4	128-255	4	≤48
				5	256-511	5	≤60
6	512-1023	6	≤72
				7	1024-2047	7	≤84
8	2048-4090	8	≤96
				9	≥4091	9	1000

And the system-side gigabit EthernetGEPHY access module 14 is used for reading the data in the DDR3 storage module through the FPGA module and outputting the read data.

The system side gigabit Ethernet GEPHY access module is a same 4-channel system side gigabit Ethernet interface, provides an independent 4-channel gigabit Ethernet output function, corresponds to the 4-channel gigabit Ethernet interface on the user side in a one-to-one manner, and realizes a transparent data transmission function; this embodiment is specifically described by taking one path as an example.

When the Ethernet data processing module detects that data are cached in the DDR3 storage module, a data sending mechanism is started, the data are read from the DDR3 storage module according to a certain bandwidth control mechanism, and then the data are transmitted to the RGMII module connected with the system side gigabit Ethernet GEPHY access module to be recombined into an Ethernet frame which is sent out through the system side gigabit Ethernet GEPHY access module.

And the managementcontrol CPU module 15 is used for carrying out configuration management on the FPGA module.

Data received by the user-side gigabit ethernet GEPHY access module in this embodiment is buffered by the FPGA to perform traffic shaping, and then output to the port of the system-side gigabit ethernet GEPHY access module at a specified time according to the requirement of output bandwidth.

Correspondingly, the receiving of the data input from the system end in this embodiment specifically includes:

the system side gigabit EthernetGEPHY access module 14 is used for receiving data input by a system port and converting the received data into data in an RGMII format identified by the FPGA module;

theFPGA module 11 is configured to acquire data in an RGMII format, perform traffic shaping processing on the acquired data, and cache the processed data in the DDR3 storage module;

theDDR3 storage module 12 is used for receiving and storing the data processed by the FPGA module;

and the user side gigabit EthernetGEPHY access module 13 is used for reading the data in the DDR3 storage module through the FPGA module and outputting the read data.

The processing flow of forwarding the data received from the system access port to the service side is the same as the processing flow of forwarding the data received by the service access port to the system side, which is not described in this embodiment.

Data received by the system-side gigabit ethernet GEPHY access module port is cached by the FPGA and then output to the user-side gigabit ethernet GEPHY access module port at a specified time according to the requirement of output bandwidth.

The processing modes of the other three ports are also the same in this embodiment, and are not further described.

In the embodiment, 4 service ports and 4 system ports are used for data storage and forwarding, so that 8 directions are used for data storage. The stored data is written into a DDR3 chip after being received by a receiving port, and then read out and output to a sending port, and in order to realize timely writing and reading of the data into and from a cache, the effective data read-write bandwidth of the DDR3 is larger than 16 Gbit. The working clock frequency of the DDR3 is selected to be 1333Mhz during design, and the bandwidth utilization rate of the DDR3 is not less than 75%.

Example two

The embodiment provides a method for realizing gigabit ethernet data traffic shaping through an FPGA, which includes:

s1, after receiving Ethernet data input by a user port, a gigabit Ethernet GEPHY access module at a user side converts the received Ethernet data into RGMII format data identified by an FPGA module;

s2, the FPGA module acquires data in an RGMII format, performs flow shaping processing on the acquired data, and caches the processed data to a DDR3 storage module;

s3, receiving and storing the data processed by the FPGA module by the DDR3 storage module;

and S4, the gigabit Ethernet GEPHY access module at the system side reads the data in the DDR3 storage module through the FPGA module and outputs the read data.

Further, the method also comprises the following steps:

after the gigabit Ethernet GEPHY access module at the system side receives data input by a system port, the received data is converted into data in an RGMII format identified by the FPGA module;

the gigabit Ethernet GEPHY access module at the user side reads data in the DDR3 storage module through the FPGA module and outputs the read data.

It should be noted that, a method for implementing gigabit ethernet data traffic shaping by using an FPGA in this embodiment is similar to the embodiment, and details are not repeated here.

Compared with the prior art, the embodiment can realize the flow shaping control of the multipath gigabit Ethernet input interface, balance the short-time burst data, reduce the instantaneous bandwidth pressure, relieve the bandwidth pressure of the Ethernet data, particularly the Ethernet data interface for video transmission, and solve the instantaneous data pressure.

The specific embodiments described herein are merely illustrative of the spirit of the invention. Various modifications or additions may be made to the described embodiments or alternatives may be employed by those skilled in the art without departing from the spirit or ambit of the invention as defined in the appended claims.

Claims (10)

1. A system for realizing gigabit Ethernet data traffic shaping through an FPGA is characterized by comprising an FPGA module, a DDR3 storage module, a user side gigabit Ethernet GEPHY access module and a system side gigabit Ethernet GEPHY access module; the FPGA module is respectively connected with the DDR3 storage module, the user-side gigabit Ethernet GEPHY access module and the system-side gigabit Ethernet GEPHY access module;

the user side gigabit Ethernet GEPHY access module is used for receiving the Ethernet data input by the user port and converting the received Ethernet data into RGMII format data identified by the FPGA module;

the FPGA module is used for acquiring data in an RGMII format, performing flow shaping processing on the acquired data, and caching the processed data into the DDR3 storage module;

the DDR3 storage module is used for receiving and storing the data processed by the FPGA module;

and the system side gigabit Ethernet GEPHY access module is used for reading the data in the DDR3 storage module through the FPGA module and outputting the read data.

2. The system according to claim 1, wherein the system-side gigabit ethernet GEPHY access module is further configured to receive data input from a system port, and convert the received data into RGMII-format data recognized by the FPGA module;

the user-side gigabit Ethernet GEPHY access module is also used for reading data in the DDR3 storage module through the FPGA module and outputting the read data.

3. The system for gigabit ethernet data traffic shaping by means of an FPGA according to claim 1, wherein the FPGA module comprises an RGMII module, an ethernet data processing module, a memory gating module; the Ethernet data processing module is respectively connected with the RGMII module and the memory gating module;

the RGMII module is used for analyzing the Ethernet data according to the protocol of the standard Ethernet to obtain the data message of the Ethernet and judging whether the obtained Ethernet data message is the correct message or not;

the Ethernet data processing module adopts an FIFO memory to synchronize data to a local processing clock if the message is a correct message, and reads the Ethernet data in the FIFO memory after receiving a complete Ethernet data message;

and the memory gating module is used for storing the read Ethernet data.

4. The system according to claim 3, wherein the ethernet data processing module is further configured to record the length of the data frame and record the address of the buffer of the DDR3 storage module.

5. The system according to claim 3, wherein the FPGA module further comprises a DDR control interface module, and the DDR control interface module is respectively connected to the memory gating module and the DDR3 storage module;

and the DDR control interface module is used for reading or writing data.

6. The system according to claim 1, further comprising a management control CPU module connected to the FPGA module, wherein the management control CPU module is configured to perform configuration management on the FPGA module.

7. The system according to claim 2, wherein the gigabit ethernet GEPHY access module on the user side and the gigabit ethernet GEPHY access module on the system side are 4 channels.

8. The system for gigabit ethernet data traffic shaping by means of an FPGA according to claim 1, wherein the FPGA module is implemented by a chip of type GW 2A-18; the DDR3 memory module adopts a chip with the model number H5TQ2G 63.

9. A method for realizing gigabit Ethernet data traffic shaping through an FPGA is characterized by comprising the following steps:

s1, after receiving Ethernet data input by a user port, a gigabit Ethernet GEPHY access module at a user side converts the received Ethernet data into RGMII format data identified by an FPGA module;

s2, the FPGA module acquires data in an RGMII format, performs flow shaping processing on the acquired data, and caches the processed data to a DDR3 storage module;

s3, receiving and storing the data processed by the FPGA module by the DDR3 storage module;

and S4, the gigabit Ethernet GEPHY access module at the system side reads the data in the DDR3 storage module through the FPGA module and outputs the read data.

10. The method of claim 9, further comprising:

after the gigabit Ethernet GEPHY access module at the system side receives data input by a system port, the received data is converted into data in an RGMII format identified by the FPGA module;

the gigabit Ethernet GEPHY access module at the user side reads data in the DDR3 storage module through the FPGA module and outputs the read data.

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