Disclosure of Invention
In order to overcome the problem that the radio frequency signal is reflected and the quality of the transmission signal is damaged due to serious impedance mismatch in the related art at least to a certain extent, the application provides an ultra-wideband wafer level packaging matching structure.
The scheme of the application is as follows:
an ultra-wideband wafer level package matching structure, comprising:
A chip wafer level package portion and a PCB portion;
The chip wafer level package portion includes a package substrate, a chip, a first passivation layer, a redistribution layer (Redistribution Layer, RDL), a second passivation layer, an under bump metallization layer (Under Bump Metallurgy, UBM), and solder balls;
The chip comprises a functional surface, a bottom surface and a chip bonding pad, wherein the bottom surface of the chip is embedded in the packaging substrate, and the functional surface of the chip is exposed;
the first passivation layer comprises a first passivation layer metal through hole, wherein the first passivation layer is arranged outside the functional surface of the chip, and the center of the first passivation layer metal through hole is aligned with the center of the chip bonding pad;
the RDL comprises an RDL signal line and an RDL metal ground, wherein the RDL is arranged outside the first passivation layer;
the UBM comprises a signal UBM and a ground UBM, wherein the UBM is arranged in the second passivation layer;
the second passivation layer is arranged outside the RDL;
the chip is vertically interconnected with the PCB part through the solder balls;
The RDL signal line is provided with a matching node for adjusting impedance mismatch between the first passivation layer metallization through hole and the signal UBM.
Preferably, in one implementation of the present application, the PCB portion includes a PCB pad, a high resistance line, a Klopfenstein gradual change line, a microstrip line, and a dielectric substrate;
The PCB bonding pad, the high-resistance wire, the Klopfenstein gradual change wire and the microstrip line are arranged on the dielectric substrate;
the chip is vertically interconnected with the PCB bonding pad through the solder ball;
The PCB bonding pad is connected with the high-resistance wire;
And the Klopfenstein gradual change line is respectively connected with the high-resistance line and the microstrip line.
Preferably, in one implementation of the present application, the RDL metal ground is symmetrically disposed on both sides of the RDL signal line.
Preferably, in one implementation manner of the application, the RDL metal ground is provided with an opening avoidance above the microstrip line, and the size of the opening avoidance is adjustable.
Preferably, in one possible implementation of the present application, a comparison between a radius of the opening relief and a radius of the UBM is 1.5:1.
Preferably, in one implementation of the present application, a radius of the solder ball and a radius of the UBM are compared to each other by 0.8:1;
the radius of the PCB bonding pad and the radius of the welding ball are compared with each other to be 1.2:1.
Preferably, in one implementation of the present application, the ground UBM is coaxially distributed around the signal UBM.
Preferably, in one realizable mode of the application, the solder balls comprise signal solder balls and ground solder balls;
the grounding solder balls are coaxially distributed around the signal solder balls.
Preferably, in one implementation mode of the application, the dielectric substrate comprises a substrate surface layer and a bottom metal grounding layer, wherein the substrate surface layer is arranged at two sides of the PCB bonding pad, the high-resistance line, the Klopfenstein gradual change line and the microstrip line, and a gap avoidance exists.
Preferably, in an implementation manner of the present application, the size of the matching section has a preset correspondence with the parameter of the Klopfenstein gradient line.
The ultra-wideband wafer level packaging matching structure provided by the application has the beneficial effects that the ultra-wideband wafer level packaging matching structure comprises a chip wafer level packaging part and a PCB part, wherein the chip wafer level packaging part comprises a packaging substrate, a chip, a first passivation layer, an RDL, a second passivation layer, a UBM and a solder ball. The chip comprises a functional surface, a bottom surface and a chip bonding pad, wherein the bottom surface of the chip is embedded in a packaging substrate, the functional surface of the chip is exposed, the first passivation layer comprises a first passivation layer metal through hole, the first passivation layer is arranged outside the functional surface of the chip, the center of the first passivation layer metal through hole is aligned with the center of the chip bonding pad, the RDL comprises an RDL signal wire and RDL metal grounding, the RDL is arranged outside the first passivation layer, the UBM comprises a signal UBM and a grounding UBM, the UBM is arranged in a second passivation layer, the second passivation layer is arranged outside the RDL, the chip is vertically interconnected with the PCB through a solder ball, and the RDL signal wire is provided with a matching node for adjusting impedance mismatch between the first passivation layer metal through hole and the signal UBM. In the application, as the RDL signal line is provided with the matching section, impedance mismatch between the first passivation layer metallization through hole and the signal UBM can be regulated, thereby preliminarily realizing impedance matching between the core bonding pad and the UBM and improving signal transmission performance.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application as claimed.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims.
An ultra-wideband wafer level package matching structure, referring to fig. 1-2, comprising:
a chip 120 wafer level package portion 100 and a PCB portion 200;
the wafer level package portion 100 of the chip 120 includes a package substrate 110, the chip 120, a first passivation layer 131, an RDL140, a second passivation layer 132, UBM160, and solder balls 170;
the chip 120 comprises a functional surface, a bottom surface and a chip bonding pad 152, wherein the bottom surface of the chip 120 is embedded in the packaging substrate 110, and the functional surface 150 of the chip is exposed;
The first passivation layer 131 includes a first passivation layer metal via, the first passivation layer 131 being disposed outside the functional surface 150 of the chip with the center of the first passivation layer metal via aligned with the center of the chip pad 152;
RDL140 includes RDL signal lines and RDL metal ground, RDL140 is disposed outside first passivation layer 131;
UBM160 includes a signal UBM and a ground UBM, UBM160 being disposed in second passivation layer 132;
The second passivation layer 132 is disposed outside the RDL 140;
the chip 120 is vertically interconnected with the PCB portion 200 by solder balls 170;
wherein the RDL signal line is provided with a matching junction for adjusting an impedance mismatch between the first passivation layer 131 metallized via and the signal UBM.
The second passivation layer 132 in this embodiment is mainly used to protect the RDL140 layer.
The ultra-wideband wafer level package matching structure in this embodiment includes a chip 120 wafer level package portion 100 and a PCB portion 200, the chip 120 wafer level package portion 100 including a package substrate 110, a chip 120, a first passivation layer 131, an RDL140, a second passivation layer 132, UBM160 and solder balls 170. The chip 120 includes a functional surface, a bottom surface and a chip pad 152, the bottom surface of the chip 120 is embedded in the package substrate 110, the functional surface 150 of the chip is exposed, the first passivation layer 131 includes a first passivation layer metal through hole, the first passivation layer 131 is arranged outside the functional surface 150 of the chip, the center of the first passivation layer metal through hole is aligned with the center of the chip pad 152, the RDL140 includes an RDL signal line and RDL metal ground, the RDL140 is arranged outside the first passivation layer 131, the UBM160 includes a signal UBM and a ground UBM, the UBM160 is arranged in the second passivation layer 132, the second passivation layer 132 is arranged outside the RDL140, the chip 120 is vertically interconnected with the PCB portion 200 through the solder ball 170, and the RDL signal line is provided with a matching section for adjusting impedance mismatch between the first passivation layer 131 metallization through hole and the signal UBM. In this embodiment, since the RDL signal line is provided with a matching node, impedance mismatch between the metallized through hole of the first passivation layer 131 and the UBM signal can be adjusted, so that impedance matching between the core pad and the UBM160 is primarily achieved, and signal transmission performance is improved.
Referring to fig. 3, a PCB portion 200 includes a PCB pad 210, a high resistance line 220, a Klopfenstein taper line 230, a microstrip line 240, and a dielectric substrate;
The PCB bonding pad 210, the high resistance wire 220, the Klopfenstein gradual change wire 230 and the microstrip line 240 are arranged on the dielectric substrate;
The chip 120 is vertically interconnected with the PCB pads 210 by solder balls 170;
the PCB pad 210 is connected to the high resistance wire 220;
The Klopfenstein taper line 230 connects the high resistance line 220 and the microstrip line 240, respectively.
Preferably, the PCB pad 210 may be, but is not limited to, a circular PCB pad 210.
Preferably, microstrip line 240 may be, but is not limited to, a 50 ohm microstrip line.
The high resistance wire 220 in this embodiment is used to match the capacitive effect of the PCB pad 210.
The Klopfenstein gradient line 230 is used to connect the high-resistance line 220 and the 50 ohm microstrip line 240, realizing broadband impedance transformation.
Preferably, in this embodiment, the dielectric substrate is a rojies 3003 substrate with a thickness of 0.127mm, and the corresponding microstrip line 240 has a width of about 0.3mm.
In some embodiments of the ultra-wideband wafer level package matching structure, RDL metal ground is symmetrically distributed on both sides of the RDL signal line.
In this embodiment, RDL metal ground is symmetrically distributed on both sides of the RDL signal line, forming a coplanar waveguide transmission line.
In the ultra-wideband wafer level packaging matching structure in some embodiments, an opening avoidance is arranged above the microstrip line 240 by RDL metal grounding, and the size of the opening avoidance is adjustable.
In this embodiment, the RDL metal ground is provided with an opening above the microstrip line 240 to avoid the space radiation of the microstrip line 240 of the PCB portion 200 from being reflected, which significantly improves the signal transmission performance.
Further, the contrast relationship between the radius of the opening relief and the radius of the UBM160 is 1.5:1;
The radius of solder ball 170 versus the radius of UBM160 is 0.8:1;
the radius of PCB pad 210 versus the radius of solder ball 170 is 1.2:1.
Preferably, the UBM160 has a radius of 100 μm, the opening relief has a radius of 150 μm, the solder ball 170 has a radius of 125 μm, and the PCB pad 210 has a radius of 50 μm.
In some embodiments, the ultra-wideband wafer level package matching structure has the grounded UBM distributed coaxially around the signal UBM.
Further, the solder balls 170 include signal solder balls and ground solder balls;
The grounding solder balls are coaxially distributed around the signal solder balls.
In this embodiment, UBM160 layer is approximately distributed with solder balls 170 for RDL signal lines, RDL metal ground, and solder ball 170 interconnection.
The grounding solder balls are coaxially distributed around the signal solder balls, so that signals can be greatly restrained to prevent leakage, and the signal transmission characteristics can be greatly improved in the millimeter wave frequency band.
The coaxial-like structure in this embodiment may be modified in practice for PCB manufacturability without uniform distribution.
In this embodiment, the chip 120 is soldered to the PCB pads 210 by signal solder balls.
The ultra-wideband wafer level packaging matching structure in some embodiments comprises a substrate surface layer and a bottom metal grounding layer, wherein the substrate surface layer is arranged on two sides of a PCB bonding pad 210, a high-resistance line 220, a Klopfenstein gradual change line 230 and a microstrip line 240, and gap avoidance exists.
Preferably, referring to fig. 3, the substrate surface relief radius of the pcb pad 210 is 300 μm, the relief distance of the substrate surface to the axis 2 is 400 μm, and the length of the high resistance wire 220 is 200 μm and the width is 150 μm.
In some embodiments, the size of the matching section and the parameters of the Klopfenstein taper line 230 have a predetermined correspondence.
Specifically, the calculation formula of the size of the Klopfenstein gradient line 230 is as follows:
Where ZL and Z0 are the load impedance and the source impedance of the graded line, respectively, I1 (x) is a modified bessel function, Γm is the maximum reflection coefficient within the passband. In practical design, the N-section impedance matching section converter is infinitely close to a Klopfenstein taper line, and when ZL、Z0, N and Γm are given, the required size of the Klopfenstein taper line 230 can be accurately obtained through MATLAB programming.
Preferably, in this embodiment, N is set to 20, Γm is 30dB, and based on the above formula, the detailed impedance distribution is obtained by MATLAB programming, and the length of the final Klopfenstein gradient line 230 is about 700 μm.
In this embodiment, the Klopfenstein taper line 230 may give the shortest matching section when the Klopfenstein taper line 230 defines the maximum reflectance specification within the passband.
In summary, in the ultra-wideband wafer level package matching structure in this embodiment, by arranging the matching section on the RDL140 layer, adjusting the opening avoiding radius of the RDL metal ground, arranging the solder balls 170 distributed like the coaxial line, arranging the high-resistance wire 220Klopfenstein taper gradient wire on the PCB, the parasitic effect caused by the interconnection structure of the solder balls 170 is greatly improved, and broadband matching is realized through the impedance gradient wire, compared with the traditional quarter-wavelength impedance transformation section matching structure.
It is to be understood that the same or similar parts in the above embodiments may be referred to each other, and that in some embodiments, the same or similar parts in other embodiments may be referred to.
It should be noted that in the description of the present application, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Furthermore, in the description of the present application, unless otherwise indicated, the meaning of "plurality" means at least two.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and further implementations are included within the scope of the preferred embodiment of the present application in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present application.
It is to be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, may be implemented using any one or combination of techniques known in the art, discrete logic circuits with logic gates for implementing logic functions on data signals, application specific integrated circuits with appropriate combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.
Those of ordinary skill in the art will appreciate that all or a portion of the steps carried out in the method of the above-described embodiments may be implemented by a program to instruct related hardware, where the program may be stored in a computer readable storage medium, and where the program, when executed, includes one or a combination of the steps of the method embodiments.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing module, or each unit may exist alone physically, or two or more units may be integrated in one module. The integrated modules may be implemented in hardware or in software functional modules. The integrated modules may also be stored in a computer readable storage medium if implemented in the form of software functional modules and sold or used as a stand-alone product.
The above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, or the like.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present application have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the application, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the application.