CN114464536A - An optimized process for TRENCH MOSFET with integrated ESD diode - Google Patents

Abstract

Translated fromChinese

本发明的一种集成ESD二极管的TRENCH MOSFET优化工艺，主要是应用于常规N管和P管的TRENCH MOSFET产品使用，使其产品本身抗静电能力得到提高的同时降低ISGS漏电级别，改进了目前集成ESD二极管的TRENCH MOSFET产品由于工艺流程不合理导致的ISGS漏电偏大现象，提出ESD本征多晶硅生长后先不进行P型杂质注入，而是先与BODY区高温一起热处理，经过高温处理后的本征多晶硅颗粒之间更加紧密，之后再进行P型杂质注入，ESD光刻，刻蚀，然后一起加工后续的步骤，利用最后一步的回流热处理进行ESD区域N+与P区形成，由于N+杂质推结阻力小，可以保证N+把整个多晶硅扩散透，保证ESD结构上N+区能合理把整个多晶硅层扩散透，形成只有横向结构的NPNPN管结构。

The optimization process of TRENCH MOSFET integrating ESD diode of the present invention is mainly applied to TRENCH MOSFET products of conventional N-tube and P-tube, so that the antistatic capability of the product itself is improved, and the leakage level of ISGS is reduced, and the current integration is improved. Due to the large leakage of ISGS caused by unreasonable process flow of TRENCH MOSFET products of ESD diodes, it is proposed that P-type impurities should not be implanted after ESD intrinsic polysilicon growth. The polysilicon particles are more closely spaced, and then P-type impurity implantation, ESD lithography, etching are performed, and subsequent steps are processed together. The final step of reflow heat treatment is used to form the N+ and P regions of the ESD region. The resistance is small, which can ensure that N+ diffuses through the entire polysilicon, and ensures that the N+ region on the ESD structure can reasonably diffuse the entire polysilicon layer, forming an NPNPN tube structure with only a lateral structure.

Description

Translated fromChinese

一种集成ESD二极管的TRENCH MOSFET优化工艺An optimized process for TRENCH MOSFET with integrated ESD diode

技术领域technical field

本发明涉及TRENCH MOSFET产品制造技术领域，特别是涉及一种集成ESD二极管的TRENCH MOSFET优化工艺。The invention relates to the technical field of manufacture of TRENCH MOSFET products, in particular to an optimization process of a TRENCH MOSFET integrated with an ESD diode.

背景技术Background technique

沟槽型(TRENCH)金属-氧化层半导体场效晶体管(Metal-Oxide-SemiconductorField-Effect Transistor，MOSFET)由于其器件的集成度较高，导通电阻较低，具有较低的栅-漏电荷密度、较大的电流容量，因而其具有较低的开关损耗和较快的开关速度，被广泛地应用在低压功率领域。目前集成ESD二极管的TRENCH MOSFET产品的两种常规工艺流程如下，所述常规工艺包括六层光罩(含钝化层)，以下两种常规工艺流程均是以N管MOSFET为主进行说明的：Trench type (TRENCH) metal-oxide semiconductor field effect transistor (Metal-Oxide-SemiconductorField-Effect Transistor, MOSFET) due to its high device integration, low on-resistance and low gate-drain charge density , larger current capacity, so it has lower switching loss and faster switching speed, is widely used in the field of low-voltage power. At present, two conventional process flows of TRENCH MOSFET products integrating ESD diodes are as follows. The conventional process includes six layers of photomasks (including passivation layers). The following two conventional process flows are mainly described with N-tube MOSFETs:

常规工艺流程一：硬掩膜层——打开沟槽——牺牲氧化——栅氧化——栅多晶淀积——回刻——淀积一定厚度TEOS氧化层——淀积ESD本征多晶硅——ESD多晶硅普注——ESD多晶硅薄氧氧化——ESD多晶硅光刻，反刻——BODY注入——BODY高温退火——源区及ESD多晶硅光刻——源区注入——NDR退火(PMOS无需此步)——BPSG淀积、回流热处理——引线孔光刻、刻蚀——引线孔硅刻蚀——CT注入——RTA退火——TI/TIN淀积及RTP退火——W淀积/AL,Cu淀积——金属刻蚀——钝化——减薄背金；Conventional process flow 1: hard mask layer - open trench - sacrificial oxidation - gate oxidation - gate polysilicon deposition - etch back - deposit a certain thickness of TEOS oxide layer - deposit ESD intrinsic polysilicon - ESD polysilicon general injection - ESD polysilicon thin oxygen oxidation - ESD polysilicon lithography, reverse etching - BODY implantation - BODY high temperature annealing - source area and ESD polysilicon lithography - source area implantation - NDR annealing ( PMOS does not need this step) - BPSG deposition, reflow heat treatment - lead hole lithography, etching - lead hole silicon etching - CT implantation - RTA annealing - TI/TIN deposition and RTP annealing - W Deposition/AL, Cu deposition - metal etching - passivation - thinning back gold;

常规工艺流程二：硬掩膜层——打开沟槽——牺牲氧化——栅氧化——栅多晶淀积——回刻——BODY注入——淀积一定厚度的氮化硅和TEOS氧化膜——淀积ESD本征多晶硅——ESD多晶硅普注——ESD多晶硅薄氧氧化——ESD多晶硅光刻，反刻——BODY高温退火——源区及ESD多晶硅光刻——源区注入——NDR退火(PMOS无需此步)——BPSG淀积、回流热处理——引线孔光刻、刻蚀——引线孔硅刻蚀——CT注入——RTA退火——TI/TIN淀积及RTP退火——W淀积/AL,Cu淀积——金属刻蚀——钝化——减薄背金。Conventional process flow 2: hard mask layer - open trench - sacrificial oxidation - gate oxidation - gate polycrystalline deposition - etch back - BODY implantation - deposit a certain thickness of silicon nitride and TEOS oxidation Film - Deposition ESD Intrinsic Polysilicon - ESD Polysilicon General Injection - ESD Polysilicon Thin Oxygen Oxidation - ESD Polysilicon Lithography, Reverse Engraving - BODY High Temperature Annealing - Source and ESD Polysilicon Lithography - Source Implantation - NDR annealing (PMOS does not need this step) - BPSG deposition, reflow heat treatment - lead hole lithography, etching - lead hole silicon etching - CT implantation - RTA annealing - TI/TIN deposition and RTP annealing - W deposition/AL, Cu deposition - metal etching - passivation - thinning back gold.

流程一与流程二工艺流程大同小异，主要区别是在ESD多晶硅淀积是在BODY注入前还是注入后淀积加工，从结构安全性出发，流程二相对来说比较合理一些，IGSS正反向漏电差异不大，而流程一由于ESD多晶硅下面没有BODY区，可能会导致正反向IGSS差异大，但不管是流程一还是流程二，它们都存在共同的缺陷：IGSS漏电绝对值太大，将导致器件开关损耗增大，且容易发热，降低了器件的可靠性。ESD二极管的IGSS漏电都比较大，目前业内最好的水平漏电控制都是在2uA到8uA之间，甚至有些达到10uA左右，微安级以上的漏电严重影响了带ESD二极管的TRENCH MOSFET产品推广应用，造成ISGS漏电大的原因主要是上述两种流程导致其形成的结构上先天不足导致的，具体可以参照图1，以常规工艺流程二作为标准集成ESD结构的TRENCH N-MOSFET进行说明，由于TRENCH MOSFET工艺特点，引线孔把全部氧化层打开后还需要继续刻硅做沟槽，而且沟槽的深度必须要比源区N+的结深要深一些才行，大部分源区N+的结深在0.3um，所以孔槽的加工深度要求在0.35～0.40um之间，而且孔槽底部还要进行浓P+注入加工，保证纵向能较好短接源区N+与PBODY区，由于ESD对应的多晶硅N+区是与元胞源区N+一起加工的，这样一来，为保证孔槽刻硅时不把ESD的多晶硅刻透，务必保证ESD的多晶硅厚度必须在6000～8000A之间，从工艺流程上可以发现，不管是流程一还是流程二，都是采用ESD本征多晶硅生长后先进行P型杂质注入，然后与PBODY一起进行高温推结处理，这样一来，后续的ESD区N+是在已经完全重度P型化后的多晶上进行反型推结，导致N+推结阻力大，结深无法穿透纵向P型多晶层，最终形成的ESD结构是由悬空浅N+与横向纵向P型区形成的NPNPN串并联畸型结构，这是由于工艺条件天生不合理搭配造成的，导致IGSS漏电大，无法把IGSS漏电降到微安级以下；现有技术中，对于离子注入，如专利文献1，其考虑导到了有时候需要在基片特定点上实现精确的定点注入而不是传统的整片离子注入，因此其设置了可以横向和纵向移动的遮盖板结构，通过设置遮盖板结构使得离子注入可以实现精确的定点注入，但是，该离子注入设备并不适合本申请的源区注入，且其注入效率低下，并不能对多片基片进行注入；又如专利文献2，其公开了一种芯片的离子注入机构，该离子注入机构通过设置能够驱动离子注入机移动的支架和能够移动芯片移动的支架结构，解决目前的芯片离子注入设备在使用时，作业面积小只能对待注入基板进行单点注入，生产效率低下的问题，但是，该种离子注入方式在解决效率低下问题时不能够精确的控制离子注入位置、且也不能够很好的对多片芯片进行定点、定位注入。Process 1 andProcess 2 are similar in process flow. The main difference is whether ESD polysilicon is deposited before or after BODY implantation. From the perspective of structural safety,Process 2 is relatively reasonable, and the difference between IGSS forward and reverse leakage It is not big, andprocess 1 may cause a large difference between forward and reverse IGSS because there is no BODY area under the ESD polysilicon, but whether it isprocess 1 orprocess 2, they all have a common defect: the absolute value of IGSS leakage is too large, which will cause the device The switching loss increases, and it is easy to generate heat, which reduces the reliability of the device. The IGSS leakage current of ESD diodes is relatively large. At present, the best horizontal leakage current control in the industry is between 2uA and 8uA, and some even reach about 10uA. The leakage current above microamp level seriously affects the promotion and application of TRENCH MOSFET products with ESD diodes. , the reason for the large leakage of ISGS is mainly due to the inherent deficiencies in the structure formed by the above two processes. For details, please refer to Figure 1. Theconventional process flow 2 is used as a TRENCH N-MOSFET with a standard integrated ESD structure for illustration. Because the TRENCH MOSFET Process characteristics, after the lead hole has opened all the oxide layers, it is necessary to continue to carve silicon to make a trench, and the depth of the trench must be deeper than the junction depth of N+ in the source region. Most of the junction depth of N+ in the source region is 0.3 um, so the processing depth of the hole and groove is required to be between 0.35 and 0.40um, and the bottom of the hole and groove should be processed with concentrated P+ implantation to ensure that the source area N+ and PBODY area can be well shorted in the longitudinal direction. Because the polysilicon N+ area corresponding to ESD It is processed together with the cell source region N+. In this way, in order to ensure that the ESD polysilicon is not carved through when the hole and groove are carved into silicon, it is necessary to ensure that the thickness of the ESD polysilicon must be between 6000 and 8000A. It can be found from the process flow. , whether it isprocess 1 orprocess 2, the ESD intrinsic polysilicon is used for P-type impurity implantation after growth, and then high-temperature junction processing is performed together with PBODY. In this way, the subsequent ESD area N+ is completely heavy P-type. The reverse type push junction is performed on the polycrystalline after the type, resulting in a large N+ push junction resistance, and the junction depth cannot penetrate the vertical P-type polycrystalline layer. The final ESD structure is formed by the floating shallow N+ and the horizontal vertical P-type region. NPNPN series-parallel distorted structure, which is caused by the unreasonable combination of process conditions, resulting in large IGSS leakage, which cannot reduce IGSS leakage below the microamp level; in the prior art, for ion implantation, such asPatent Document 1, it considers This leads to the fact that sometimes it is necessary to achieve precise fixed-point implantation on a specific point of the substrate instead of the traditional whole-chip ion implantation. Therefore, it is equipped with a cover plate structure that can move laterally and vertically. By setting the cover plate structure, the ion implantation can achieve precise However, this ion implantation device is not suitable for the source region implantation of the present application, and its implantation efficiency is low, and it cannot implant multiple substrates; another example isPatent Document 2, which discloses a chip ion implantation Implantation mechanism, the ion implantation mechanism is provided with a bracket that can drive the ion implanter to move and a bracket structure that can move the chip, so as to solve the problem that when the current chip ion implantation equipment is in use, the working area is small and only single-point implantation can be performed on the substrate to be implanted. The problem of low production efficiency, however, when solving the problem of low efficiency, this ion implantation method cannot accurately control the ion implantation position, and cannot perform fixed-point and positioning implantation on multiple chips well.

[专利文献1]CN109256314B；[Patent Document 1] CN109256314B;

[专利文献2]CN107346723B。[Patent Document 2] CN107346723B.

综上所述，本发明在充分分析目前工艺流程存在的问题根源基础上，针对目前集成ESD二极管的TRENCH MOSFET产品由于工艺流程不合理导致的ISGS漏电偏大现象，在全面分析目前常规工艺流程的基础上进行创新改进，务必保证ESD结构上N+区能合理把整个多晶硅层扩散透，形成只有横向结构的NPNPN管结构，提出ESD本征多晶硅生长后先不进行P型杂质注入，而是先与BODY区高温一起热处理，经过高温处理后的本征多晶硅颗粒之间更加紧密，之后再进行P型杂质注入，ESD光刻，刻蚀，然后一起加工后续的步骤，利用最后一步的回流热处理进行ESD区域N+与P区形成，由于N+杂质推结阻力小，可以保证N+把整个多晶硅扩散透，最终形成的结构示意图如图2所示，只有横向结构的NPNPN管结构，使得产品本身抗静电能力得到提高的同时降低ISGS漏电级别。更进一步地，针对优化工艺中的源区注入工艺，本发明还提供了一种专门适用的离子注入设备，其能够很好的在N⁺区杂质注入时，提高注入精度以及提高注入效率，且还能够针对多片芯片进行逐步注入。To sum up, on the basis of fully analyzing the root causes of the problems existing in the current process flow, the present invention comprehensively analyzes the current conventional process flow for the phenomenon of large ISGS leakage caused by the unreasonable process flow of the TRENCH MOSFET products with integrated ESD diodes. On the basis of innovation and improvement, it is necessary to ensure that the N+ region on the ESD structure can reasonably diffuse the entire polysilicon layer to form an NPNPN tube structure with only a lateral structure. The BODY area is heat-treated at high temperature together, and the intrinsic polysilicon particles after high-temperature treatment are closer together, and then P-type impurity implantation, ESD lithography, and etching are performed, and then the subsequent steps are processed together, using the last step of reflow heat treatment for ESD The N+ and P regions are formed. Due to the small resistance of N+ impurity pushing junction, it can ensure that N+ diffuses through the entire polysilicon. The final structure diagram is shown in Figure 2. Only the NPNPN tube structure of the lateral structure makes the antistatic ability of the product itself. Improve while reducing ISGS leakage level. Further, for the source region implantation process in the optimization process, the present invention also provides a specially suitable ion implantation equipment, which can well improve the implantation precision and improve the implantation efficiency during the impurity implantation in the N⁺ region, and Step-by-step implantation is also possible for multiple chips.

发明内容SUMMARY OF THE INVENTION

为了克服现有TRENCH MOSFET工艺的不足，本发明提供了一种技术方案，一种集成ESD二极管的TRENCH MOSFET优化工艺，其步骤包括：In order to overcome the deficiencies of the existing TRENCH MOSFET process, the present invention provides a technical solution, a TRENCH MOSFET optimization process integrating an ESD diode, the steps of which include:

1)形成硬掩膜层：提供衬底，在衬底上形成硬掩膜层；1) forming a hard mask layer: providing a substrate, and forming a hard mask layer on the substrate;

2)打开沟槽：通过蚀刻或者激光束加工的方式，形成沟槽；2) Open the groove: form the groove by etching or laser beam processing;

3)牺牲氧化：通过热氧化形成牺牲氧化层；3) Sacrificial oxidation: a sacrificial oxide layer is formed by thermal oxidation;

4)栅氧化——栅多晶淀积——回刻——BODY注入；4) Gate oxidation - gate polycrystalline deposition - etchback - BODY implantation;

5)淀积一定厚度的TEOS层——淀积ESD本征多晶硅——多晶硅薄氧氧化——BODY高温退火；5) Deposit a certain thickness of TEOS layer - deposit ESD intrinsic polysilicon - polysilicon thin oxygen oxidation - BODY high temperature annealing;

6)ESD多晶硅普注：使用离子注入机进行P型杂质注入；6) ESD polysilicon general injection: use an ion implanter for P-type impurity implantation;

7)ESD多晶硅光刻，反刻——源区及ESD多晶硅光刻；7) ESD polysilicon lithography, reverse etching - source area and ESD polysilicon lithography;

8)源区注入：在源区进行N⁺杂质注入；8) Source region implantation: N⁺ impurity implantation is performed in the source region;

9)NDR退火；9) NDR annealing;

10)BPSG淀积、回流热处理——引线孔光刻、刻蚀——引线孔硅刻蚀——CT注入——RTA退火——TI和/或TIN淀积及RTP退火——W淀积和/或Al、Cu淀积；10) BPSG deposition, reflow heat treatment - lead hole lithography, etching - lead hole silicon etching - CT implantation - RTA annealing - TI and/or TIN deposition and RTP annealing - W deposition and / or Al, Cu deposition;

11)金属刻蚀——钝化——减薄背金。11) Metal etching - passivation - thinning back gold.

优选地，所述步骤5)中BODY高温退火全程使用N₂退火。Preferably, in the step 5), N₂ annealing is used throughout the BODY high temperature annealing process.

优选地，PMOS无需步骤9)NDR退火。Preferably, step 9) NDR annealing is not required for PMOS.

优选地，所述步骤8)采用离子注入设备完成，所述离子注入设备包括注入腔室、离子注入机、遮盖板、驱动筒、支撑筒和芯片支架，芯片支架包括主体支撑段以及设置于主体支撑段两端的螺纹段一和螺纹段二，所述主体支撑段为圆柱体结构，且在主体支撑段上沿其轴线周向均布有若干支撑架，支撑架上设置有芯片支撑板，芯片可拆卸的固定设置于芯片支撑板上，所述驱动筒包括支撑架一和筒壁一，所述筒壁一上设置有驱动螺纹一，所述驱动螺纹一与螺纹段一啮合，支撑架一上固定设置有驱动缸，驱动缸的右端抵接芯片支架的左端，离子注入机固定设置于注入腔室的上端，遮盖板固定设置于离子注入机的下端，遮盖板上设置有离子注入口，以及能够打开或关闭离子注入口的滑动盖板，滑动盖板在盖板驱动机构的带动下进行滑动，离子注入机通过离子注入口完成芯片的离子注入，注入腔室内还设置有抽、放真空装置，能够对注入腔室进行抽真空和放真空操作。Preferably, the step 8) is completed by using an ion implantation device, the ion implantation device includes an implantation chamber, an ion implanter, a cover plate, a driving cylinder, a support cylinder and a chip support, the chip support includes a main body support section and a The first and second threaded sections at both ends of the support section, the main body support section has a cylindrical structure, and a number of support frames are evenly distributed along the circumference of its axis on the main body support section. The support frame is provided with a chip support plate, and the chip is detachable It is fixed on the chip support plate, the driving cylinder includes a supportingframe 1 and acylinder wall 1, thecylinder wall 1 is provided with adriving thread 1, thedriving thread 1 is engaged with the threaded section, and the supportingframe 1 is fixed on the first A drive cylinder is provided, the right end of the drive cylinder abuts the left end of the chip support, the ion implanter is fixedly arranged at the upper end of the implantation chamber, the cover plate is fixedly arranged at the lower end of the ion implanter, and the cover plate is provided with an ion implantation port, and can The sliding cover plate of the ion implantation port is opened or closed, and the sliding cover plate slides under the drive of the cover plate drive mechanism. The ion implanter completes the ion implantation of the chip through the ion implantation port. The implantation chamber is also provided with a vacuum pumping and releasing device. The injection chamber can be evacuated and evacuated.

优选地，螺纹段一和驱动螺纹一的螺距设置为，在驱动缸伸出带动芯片沿芯片支架的轴线旋转过一周后，芯片沿芯片支架的轴线移动的距离为步骤8)中需要注入的两N⁺区域的间隔L。Preferably, the pitch of the first thread segment and the first driving thread is set so that after the driving cylinder extends and drives the chip to rotate for one week along the axis of the chip holder, the distance that the chip moves along the axis of the chip holder is the two steps that need to be injected in step 8). The interval L of the N⁺ region.

优选地，在进行所述步骤8)之前，将若干芯片装入芯片支撑板上，将需要离子注入的区域对准离子注入口，然后先使得滑动盖板封闭离子注入口，抽真空装置动作，使得注入腔室内为真空状态，启动离子注入机进入步骤8)，待离子注入机喷出的离子稳定后，打开离子注入口，对第一个芯片进行离子注入，待注入完成后，关闭离子注入口，同时使得驱动缸伸出，推动芯片支架向右滑动，同时驱动螺纹一使得支撑架旋转，当转动到第二个芯片对准离子注入口后，停止驱动缸的驱动，同时使得离子注入口打开，离子注入机对第二个芯片进行离子注入，如此继续动作，待第一个芯片又旋转到离子注入口后，又能够进行相邻N⁺区域的离子注入，如此反复，最终完成所有芯片的源区注入，关闭离子注入机，取出所有芯片进行下一步骤的操作。Preferably, before performing the step 8), a number of chips are mounted on the chip support plate, and the area that needs ion implantation is aligned with the ion implantation port, and then the sliding cover plate is first closed to the ion implantation port, and the vacuum device is activated, Make the implantation chamber in a vacuum state, start the ion implanter and enter step 8). After the ions ejected by the ion implanter are stable, open the ion implantation port and perform ion implantation on the first chip. After the implantation is completed, turn off the ion implanter. At the same time, the driving cylinder is extended to push the chip holder to slide to the right, and at the same time, the thread is driven to make the holder rotate. When the second chip is rotated to align with the ion injection port, the driving of the driving cylinder is stopped, and the ion injection port is Turn on, the ion implanter implants ions into the second chip, and so on. After the first chip rotates to the ion implantation port again, the ion implantation of the adjacent N⁺ region can be performed again. Repeat this, and finally all chips are completed. The source region is implanted, the ion implanter is turned off, and all chips are taken out for the next step.

优选地，支撑筒包括筒壁二和支撑架二，在支撑架二上固定设置有恢复缸，在筒壁二上设置有螺纹段二，螺纹段二与驱动螺纹段二啮合，恢复缸伸出后能够使得芯片支架向左滑动，从而能够恢复芯片支架的初始位置。Preferably, the support cylinder comprises a second cylinder wall and a second support frame, a recovery cylinder is fixedly arranged on the second support frame, and a second thread segment is provided on the second cylinder wall, the second thread segment engages with the second driving thread segment, and the recovery cylinder extends out Afterwards, the chip holder can be slid to the left, so that the original position of the chip holder can be restored.

优选地，所述若干支撑架为4、6、8或12个。Preferably, there are 4, 6, 8 or 12 of the several support frames.

优选地，所述离子注入口为条形孔结构；Preferably, the ion implantation port is a strip-shaped hole structure;

优选地，所述离子注入口为圆形孔结构，此时，芯片支撑板可转动的设置于支撑架上，能够沿支撑架的轴线进行转动，从而能够调整芯片的旋转角度，在离子注入口为圆形孔结构时，在对第一块芯片进行离子注入时，同时使得驱动缸进行缓慢伸长，从而通过支撑架的转动，使得离子注入机通过离子注入口能够在芯片上进行离子的线性注入，在进行此时的离子注入时，首先调整芯片的角度，使得离子注入在芯片上形成的线条满足芯片的加工要求。Preferably, the ion implantation port has a circular hole structure. At this time, the chip support plate is rotatably arranged on the support frame and can be rotated along the axis of the support frame, so that the rotation angle of the chip can be adjusted. In the case of a circular hole structure, when ion implantation is performed on the first chip, the driving cylinder is slowly extended at the same time, so that the ion implanter can perform ion linearization on the chip through the rotation of the support frame through the ion implantation port. For implantation, during the ion implantation at this time, the angle of the chip is first adjusted so that the lines formed on the chip by the ion implantation meet the processing requirements of the chip.

优选地，步骤6)中的ESD多晶硅普注也通过所述离子注入设备完成，其只要调节离子注入口的开度大小即可实现，与步骤8)共用一个离子注入设备，在进行步骤6)时使得离子注入口在全开和全闭之间切换，对芯片进行离子注入操作，而在进行步骤8)时，使得离子注入口处于全闭和开一定间隙之间切换，对芯片进行离子注入操作。Preferably, the general injection of ESD polysilicon in step 6) is also completed by the ion implantation equipment, which can be realized as long as the opening of the ion implantation port is adjusted, and the same ion implantation equipment is shared with step 8), and step 6) is performed. When the ion implantation port is switched between fully open and fully closed, the ion implantation operation is performed on the chip, and when step 8) is performed, the ion implantation port is switched between fully closed and open with a certain gap, and ion implantation is performed on the chip. operate.

本发明的有益效果为：The beneficial effects of the present invention are:

1)、采用改进的优化工艺流程后，最终形成的ESD结构是由标准的横向NPNPN管组成的串联二极管形成，IGSS漏电正反向都在微安级以内，具体数据在500nA左右，漏电下降75％左右，减少了器件的开关损耗，有效提高器件的可靠性；1) After adopting the improved and optimized process flow, the final ESD structure is formed by a series diode composed of standard lateral NPNPN transistors. The forward and reverse IGSS leakage current is within the microamp level. The specific data is about 500nA, and the leakage current drops by 75%. %, which reduces the switching loss of the device and effectively improves the reliability of the device;

2)、进一步地，优化工艺将ESD多晶硅的第一次普注的杂质和第二次与源区同类型的杂质放在BODY高温退火之后注入，通过工艺改进，两种杂质都可以完全穿透ESD多晶硅，其原理是由于两种杂质同步在本征多晶硅上进行热退火，虽然多晶硅N⁺区前面已经有P型杂质注入，但由于没有提前激活，N⁺区的杂质很浓，可以轻松地把未激活的P型杂质中和掉，然后再轻松地把整个多晶层扩散透，由于多晶硅与单晶硅结构上存在差异，虽然N⁺杂质在元胞区最终的结深只有0.3um左右，但在多晶硅上结深能达0.8um左右，即使多晶硅做到8000A的厚度，N⁺区在新的流程下也可以完全把多晶硅扩透，从而达到减少漏电的目的；2) Further, optimize the process to inject the impurities of the first general injection of ESD polysilicon and the impurities of the same type as the source region for the second time after the BODY high temperature annealing. Through process improvement, both impurities can be completely penetrated The principle of ESD polysilicon is that two kinds of impurities are simultaneously thermally annealed on the intrinsic polysilicon. Although P-type impurities have been implanted in front of the polysilicon N⁺ region, the impurity in the N⁺ region is very thick because it is not activated in advance. Neutralize the unactivated P-type impurities, and then diffuse the entire polycrystalline layer easily. Due to the difference in the structure of polycrystalline silicon and monocrystalline silicon, although the final junction depth of N⁺ impurities in the cell region is only about 0.3um , but the junction depth on polysilicon can reach about 0.8um, even if the thickness of polysilicon is 8000A, the N⁺ region can completely expand the polysilicon under the new process, so as to achieve the purpose of reducing leakage;

3)、进一步地，为了适应源区注入步骤，提供了一种离子注入设备，所述离子注入设备能够同时对多片芯片进行离子注入操作，且在对多片芯片进行离子注入操作时并不需要频繁关闭或打开离子注入机，而且能够合理布局各N+区域的间隔大小，能够高效、准确的完成离子注入；3), further, in order to adapt to the source region implantation step, an ion implantation device is provided, the ion implantation device can perform ion implantation operations on multiple chips at the same time, and does not perform ion implantation operations on multiple chips. It is necessary to close or open the ion implanter frequently, and the interval size of each N+ region can be reasonably arranged, and the ion implantation can be completed efficiently and accurately;

4)、进一步地，本发明的离子注入设备，其设置了带螺纹段结构的芯片支架结构，芯片支架上周向布置有若干支撑架，各支撑架上均设置有待离子注入的芯片，其通过使用横向移动的驱动缸结构，使得芯片支架在向右滑动时，能够进行转动，调整对准离子注入口的芯片，从而连续的完整了若干芯片的离子注入工艺；4), further, the ion implantation equipment of the present invention, it is provided with the chip support structure with threaded segment structure, the chip support is arranged with a number of support frames in the circumferential direction, and each support frame is provided with the chip to be ion implanted, which passes through. The use of a laterally moving drive cylinder structure enables the chip holder to rotate when sliding to the right to adjust the chip aligned with the ion implantation port, thereby continuously completing the ion implantation process of several chips;

5)、进一步地，本发明的离子注入设备，能够适应流程中的ESD多晶硅普注和源区注入步骤，提高了设备的利用率，在进行普注时，仅需要使得离子注入口在全开和全闭之间切换即可；5) Further, the ion implantation device of the present invention can adapt to the ESD polysilicon general injection and source region implantation steps in the process, and improves the utilization rate of the device. When performing general injection, only the ion implantation port needs to be fully opened. You can switch between fully closed and fully closed;

6)、进一步地，本发明的离子注入设备是与本申请的优化工艺相适应的，通过使用该离子注入设备能够进一步地提高芯片成型的效率和质量，避免了现有的离子注入时需要不断调整芯片与离子注入机之间的位置从而获得理想效果的芯片的缺陷，使用本离子注入设备仅需要初始时调整芯片位置即可，后续离子注入均是自动化完成的，其提高效率的同时也保证了芯片的离子注入质量，从而保证了最终成品的质量。6), further, the ion implantation equipment of the present invention is compatible with the optimized process of the present application, and the efficiency and quality of chip molding can be further improved by using the ion implantation equipment, avoiding the need for continuous ion implantation during the existing ion implantation. To adjust the position between the chip and the ion implanter to obtain the desired effect of the defect of the chip, the use of this ion implantation equipment only needs to adjust the position of the chip at the beginning, and the subsequent ion implantation is completed automatically, which improves the efficiency and guarantees The ion implantation quality of the chip is improved, thereby ensuring the quality of the final product.

附图说明Description of drawings

图1为经过现有的TRENCH MOSFET工艺流程后得到的晶体管示意图；Fig. 1 is the transistor schematic diagram obtained after the existing TRENCH MOSFET process flow;

图2为经过优化的TRENCH MOSFET工艺流程后得到的晶体管示意图；Fig. 2 is the schematic diagram of the transistor obtained after the optimized TRENCH MOSFET process flow;

图3为本发明的离子注入设备的主视图；3 is a front view of the ion implantation device of the present invention;

图4为图3的A-A视图；Fig. 4 is the A-A view of Fig. 3;

图5为遮盖板的俯视图。FIG. 5 is a top view of the cover plate.

标号说明Label description

1、注入腔室；2、离子注入机；3、遮盖板；4、驱动筒；5、支撑筒；6、芯片支架；7、芯片；8、驱动缸；9、螺纹段一；10、主体支撑段；11、螺纹段二；12、支撑架；13、芯片支撑板；14、支撑架一；15、筒壁一；16、驱动螺纹一；17、支撑架二；18、筒壁二；19、驱动螺纹段二；20、恢复缸；21、左支撑缸；22、右支撑缸；23、滑动座；24、离子注入口；25、支撑架；26、滑动盖板。1. Injection chamber; 2. Ion implanter; 3. Cover plate; 4. Driving cylinder; 5. Supporting cylinder; 6. Chip holder; 7. Chip; 8. Driving cylinder; 9. Thread section one; 10. Main body Support section; 11, thread section two; 12, support frame; 13, chip support plate; 14, support frame one; 15, cylinder wall one; 16, driving thread one; 17, support frame two; 18, cylinder wall two; 19. Drivethread section 2; 20. Recovery cylinder; 21. Left support cylinder; 22. Right support cylinder; 23. Sliding seat; 24. Ion injection port;

具体实施方式Detailed ways

下面结合实施例对本发明作进一步的说明，但不以任何方式对本发明加以限制，基于本发明教导所作的任何变换或替换，均属于本发明的保护范围。The present invention is further described below in conjunction with the examples, but the present invention is not limited in any way, and any transformation or replacement made based on the teachings of the present invention belongs to the protection scope of the present invention.

一种集成ESD二极管的TRENCH MOSFET优化工艺，其步骤包括：A TRENCH MOSFET optimization process integrating an ESD diode, the steps of which include:

1)形成硬掩膜层：提供衬底，在衬底上形成硬掩膜层；1) forming a hard mask layer: providing a substrate, and forming a hard mask layer on the substrate;

2)打开沟槽：通过蚀刻或者激光束加工的方式，形成沟槽；2) Open the groove: form the groove by etching or laser beam processing;

3)牺牲氧化：通过热氧化形成牺牲氧化层；3) Sacrificial oxidation: a sacrificial oxide layer is formed by thermal oxidation;

4)栅氧化——栅多晶淀积——回刻——BODY注入；4) Gate oxidation - gate polycrystalline deposition - etchback - BODY implantation;

5)淀积一定厚度的TEOS层——淀积ESD本征多晶硅——多晶硅薄氧氧化——BODY高温退火；5) Deposit a certain thickness of TEOS layer - deposit ESD intrinsic polysilicon - polysilicon thin oxygen oxidation - BODY high temperature annealing;

6)ESD多晶硅普注：使用离子注入机进行P型杂质注入；6) ESD polysilicon general injection: use an ion implanter for P-type impurity implantation;

7)ESD多晶硅光刻，反刻——源区及ESD多晶硅光刻；7) ESD polysilicon lithography, reverse etching - source area and ESD polysilicon lithography;

8)源区注入：在源区进行N⁺杂质注入；8) Source region implantation: N⁺ impurity implantation is performed in the source region;

9)NDR退火；9) NDR annealing;

10)BPSG淀积、回流热处理——引线孔光刻、刻蚀——引线孔硅刻蚀——CT注入——RTA退火——TI/TIN淀积及RTP退火——W淀积/AL,Cu淀积；10) BPSG deposition, reflow heat treatment - lead hole lithography, etching - lead hole silicon etching - CT implantation - RTA annealing - TI/TIN deposition and RTP annealing - W deposition/AL, Cu deposition;

11)金属刻蚀——钝化——减薄背金；11) Metal etching - passivation - thinning back gold;

所述步骤5)中BODY高温退火全程使用N₂退火；In the step 5), the high temperature annealing of BODY uses N₂ annealing throughout the whole process;

PMOS无需步骤9)NDR退火；PMOS does not need step 9) NDR annealing;

所述步骤8)采用专门适用的离子注入设备完成，如图3-5所示，所述离子注入设备包括注入腔室1、离子注入机2、遮盖板3、驱动筒4、支撑筒5和芯片支架6，芯片支架6包括主体支撑段10以及设置于主体支撑段10两端的螺纹段一9和螺纹段二19，主体支撑段10为圆柱体结构，且在主体支撑段10上沿其轴线周向均布有若干支撑架12，支撑架12上设置有芯片支撑板13，芯片7即可拆卸的固定设置于芯片支撑板13上，驱动筒4包括支撑架一14和筒壁一15，筒壁一15上设置有驱动螺纹一16，所述驱动螺纹一16与螺纹段一9啮合，支撑架一14上固定设置有驱动缸8，驱动缸8的右端抵接芯片支架6的左端，离子注入机2固定设置于注入腔室1的上端，遮盖板3固定设置于离子注入机2的下端，遮盖板3上设置有离子注入口24，以及能够打开或关闭离子注入口24的滑动盖板26，滑动盖板26在盖板驱动机构的带动下进行滑动，离子注入机2通过离子注入口24完成芯片7的离子注入，螺纹段一9和驱动螺纹一16的螺距设置为，在驱动缸8伸出带动芯片7沿芯片支架6的轴线旋转过一周后，芯片7沿芯片支架6的轴线移动的距离为步骤8)中需要注入的两N⁺区域的间隔L(为两N⁺区域之间的P型杂质区域的宽度)，注入腔室1内还设置有抽、放真空装置(图未示出)，能够对注入腔室1进行抽真空和放真空操作，由于其并不是本发明的重点，故不再赘述。The step 8) is completed by using a specially adapted ion implantation device, as shown in Figs. 3-5, the ion implantation device includes animplantation chamber 1, anion implanter 2, acover plate 3, adrive cylinder 4, a support cylinder 5 and Thechip support 6 includes a mainbody support section 10 and a threadedsection 1 9 and a threadedsection 2 19 disposed at both ends of the mainbody support section 10. The mainbody support section 10 is a cylindrical structure, and is on the mainbody support section 10 along its axis A plurality of support frames 12 are evenly distributed in the circumferential direction. Achip support plate 13 is arranged on thesupport frame 12. Thechip 7 can be detachably fixed on thechip support plate 13. Thedrive cylinder 4 includes a support frame one 14 and a cylinder wall one 15. One 15 is provided with a drivingthread 1 16, the drivingthread 1 16 is engaged with the threadedsegment 1 9, and adriving cylinder 8 is fixed on thesupport frame 1 14, the right end of the drivingcylinder 8 abuts the left end of thechip holder 6, and ion implantation is performed. Themachine 2 is fixedly arranged at the upper end of theimplantation chamber 1, thecover plate 3 is fixedly arranged at the lower end of theion implanter 2, thecover plate 3 is provided with anion implantation port 24, and a slidingcover plate 26 capable of opening or closing theion implantation port 24 , the slidingcover plate 26 slides under the drive of the cover plate drive mechanism, theion implanter 2 completes the ion implantation of thechip 7 through theion implantation port 24, the pitch of the thread segment one 9 and the driving thread one 16 is set to be, in thedrive cylinder 8 After extending and driving thechip 7 to rotate for one week along the axis of thechip holder 6, the distance that thechip 7 moves along the axis of thechip holder 6 is the interval L of the two N⁺ areas that need to be injected in step 8) (is between the two N⁺ areas. The width of the P-type impurity region), theinjection chamber 1 is also provided with a vacuuming and vacuuming device (not shown in the figure), which can perform vacuuming and vacuuming operations on theinjection chamber 1, because it is not the invention. important, so I won't go into details.

在进行所述步骤8)之前，将若干芯片7装入芯片支撑板13上，将需要离子注入的区域对准离子注入口24，然后先使得滑动盖板26封闭离子注入口24，抽真空装置动作，使得注入腔室1内为真空状态，启动离子注入机2进入步骤8)，待离子注入机2喷出的离子稳定后，打开离子注入口24，对第一个芯片进行离子注入，待注入完成后，关闭离子注入口24，同时使得驱动缸8伸出，推动芯片支架6向右滑动，同时驱动螺纹一16使得支撑架12旋转，当转动到第二个芯片对准离子注入口24后，停止驱动缸8的驱动，同时使得离子注入口24打开，离子注入机2对第二个芯片进行离子注入，如此继续动作，待第一个芯片又旋转到离子注入口24后，又能够进行相邻N⁺区域的离子注入，如此反复，最终完成所有芯片的源区注入，关闭离子注入机2，取出所有芯片进行下一步骤的操作。Before performing the step 8), a number ofchips 7 are loaded on thechip support plate 13, the area that needs ion implantation is aligned with theion implantation port 24, and then the slidingcover plate 26 is made to close theion implantation port 24, and the vacuum device is evacuated. action to make theimplantation chamber 1 in a vacuum state, start theion implanter 2 and enter step 8). After the ions ejected by theion implanter 2 are stable, open theion implantation port 24, and perform ion implantation on the first chip. After the implantation is completed, theion implantation port 24 is closed, and thedriving cylinder 8 is extended to push thechip holder 6 to slide to the right, while driving the thread one 16 to make thesupport frame 12 rotate. Then, the driving of the drivingcylinder 8 is stopped, and theion implantation port 24 is opened at the same time, and theion implanter 2 performs ion implantation on the second chip. The ion implantation of adjacent N⁺ regions is performed, and so on, until the source region implantation of all chips is finally completed, theion implanter 2 is turned off, and all chips are taken out for the next step.

优选地，芯片7装入芯片支撑板13的方式可以通过真空吸附、机械夹紧、电磁夹紧等方式实现，能保证在支撑架12翻转时芯片7不掉落即可，此处并不是本发明的重点故不再赘述。Preferably, the method of loading thechip 7 into thechip support plate 13 can be realized by vacuum adsorption, mechanical clamping, electromagnetic clamping, etc., which can ensure that thechip 7 does not fall off when thesupport frame 12 is turned over. The key points of the invention will not be repeated here.

优选地，为了能够调整离子注入机2与芯片之间的间距，使得驱动筒4下端固定设置有左支撑缸21，支撑筒5的额下端固定设置有右支撑缸22；优选地，为了能够方便芯片的拿取，使得注入腔室1的侧壁设置有能够开合的门，左支撑缸21和右支撑缸22均固定设置于滑动座23上，滑动座23能够滑动的设置于注入腔室1的底部，在需要进行芯片安装和卸载时，打开侧壁的门，然后拉出滑动座23，即可方便芯片支撑板13上的芯片的安装和卸载。Preferably, in order to be able to adjust the distance between theion implanter 2 and the chip, the lower end of thedrive cylinder 4 is fixedly provided with aleft support cylinder 21, and the lower end of the support cylinder 5 is fixedly provided with aright support cylinder 22; preferably, for convenience The chip is taken, so that the side wall of theinjection chamber 1 is provided with a door that can be opened and closed. 1, when the chip needs to be installed and unloaded, open the door of the side wall, and then pull out the slidingseat 23, which can facilitate the installation and unloading of the chip on thechip support plate 13.

优选地，为了保证主体支撑段10能够进行稳定滑动、转动及初始化，使得支撑筒5包括筒壁二18和支撑架二17，在支撑架二17上固定设置有恢复缸20，在筒壁二18上设置有螺纹段二19，螺纹段二19与驱动螺纹段二11啮合，恢复缸20伸出后能够使得芯片支架6向左滑动，从而能够恢复芯片支架6的初始位置。Preferably, in order to ensure that the mainbody support section 10 can be stably slid, rotated and initialized, the support cylinder 5 includes asecond cylinder wall 18 and a second support frame 17, and arecovery cylinder 20 is fixed on the second support frame 17. Thesecond thread segment 19 is provided on the 18, and thesecond thread segment 19 engages with the seconddriving thread segment 11. After therecovery cylinder 20 is extended, thechip holder 6 can slide to the left, thereby restoring the initial position of thechip holder 6.

优选地，所述若干支撑架12优选为4、6、8、12个。Preferably, there are 4, 6, 8 or 12 of the plurality of support frames 12 .

优选地，为了能够精确的控制芯片支架6的滑动距离，使得各螺纹段均为丝杠结构；优选地，使得驱动缸8的右端和恢复缸20的左端均分别可转动地固定连接于主体支撑段的左端和右端。Preferably, in order to accurately control the sliding distance of thechip support 6, each thread segment is a lead screw structure; preferably, the right end of thedrive cylinder 8 and the left end of therecovery cylinder 20 are respectively rotatably and fixedly connected to the main body support The left and right ends of the segment.

优选地，所述滑动盖板26还可以选择遮盖离子注入口24的程度，从而能够根据不同的离子注入区域大小而进行调整；优选地，所述盖板驱动机构选择为驱动气缸、驱动油缸或丝杆驱动机构等结构，只要能够实现能够驱动滑动盖板26滑动即可。Preferably, the slidingcover plate 26 can also choose the degree of covering theion implantation port 24, so that it can be adjusted according to the size of different ion implantation areas; The structure of the screw drive mechanism and the like may be implemented as long as the slidingcover plate 26 can be driven to slide.

优选地，所述离子注入口24为条形孔结构；Preferably, theion implantation port 24 is a strip-shaped hole structure;

优选地，所述离子注入口24也可以为圆形孔结构，此时，芯片支撑板13可转动的设置于支撑架12上，能够沿支撑架12的轴线进行转动，从而能够调整芯片7的旋转角度，在离子注入口24为圆形孔结构时，在对第一块芯片进行离子注入时，同时使得驱动缸8进行缓慢伸长，从而通过支撑架12的转动，使得离子注入机2通过离子注入口24能够在芯片7上进行离子的线性注入，在进行此时的离子注入时，首先调整芯片7的角度，使得离子注入在芯片7上形成的线条满足芯片7的加工要求，不会出现斜线离子注入的情形；Preferably, theion implantation port 24 can also be a circular hole structure. At this time, thechip support plate 13 is rotatably arranged on thesupport frame 12 and can be rotated along the axis of thesupport frame 12, so that thechip 7 can be adjusted. Rotation angle, when theion implantation port 24 is a circular hole structure, when the ion implantation is performed on the first chip, the drivingcylinder 8 is slowly extended at the same time, so that theion implanter 2 passes through the rotation of thesupport frame 12. Theion implantation port 24 can perform linear implantation of ions on thechip 7. During the ion implantation at this time, the angle of thechip 7 is adjusted first, so that the lines formed by the ion implantation on thechip 7 meet the processing requirements of thechip 7 and will not The situation of oblique ion implantation occurs;

优选地，若是使得离子注入口24为圆形孔结构，可以使得支撑架12的数量为使得芯片7能够包围住主体支撑段10，此时，即可以不用再断断续续打开或关闭离子注入口24，可以在对芯片7进行离子注入时，使得驱动缸8以一定的速度进行均速推动芯片支架6向右移动，使得离子注入机2能够对安放于芯片支撑板13上的所有芯片进行无间断的离子注入操作，提高离子注入效率。Preferably, if theion implantation port 24 has a circular hole structure, the number of support frames 12 can be made such that thechip 7 can surround the mainbody support section 10. At this time, theion implantation port 24 need not be opened or closed intermittently. When ion implantation is performed on thechip 7, the drivingcylinder 8 can be made to push thechip holder 6 to move to the right at a certain speed at a uniform speed, so that theion implanter 2 can perform uninterrupted operation on all the chips placed on thechip support plate 13. Ion implantation operation to improve ion implantation efficiency.

优选地，所述遮盖板3通过支撑架25固定设置于支撑筒5的上端。Preferably, thecover plate 3 is fixedly arranged on the upper end of the support cylinder 5 through thesupport frame 25 .

优选地，所述滑动座23上可以设置驱动轮结构，使得其能够自动滑出或滑入注入腔室1。Preferably, a driving wheel structure can be provided on the slidingseat 23 so that it can slide out or slide into theinjection chamber 1 automatically.

优选地，所述各支撑架12的设置位置可以为，在驱动缸8推动芯片支架6向右滑动时，待离子注入的芯片7第一次转动到与离子注入口24对应的位置处时，每个芯片7的第一次进行离子注入的位置相同，从而能够保证所有芯片在经过离子注入机2的离子注入后生产出来的芯片都是一样的。Preferably, the setting positions of the supportingframes 12 can be such that when the drivingcylinder 8 pushes thechip holder 6 to slide to the right, when thechip 7 to be ion implanted is rotated to the position corresponding to theion implantation port 24 for the first time, The positions of the first ion implantation of eachchip 7 are the same, so that it can be ensured that the chips produced by all the chips after the ion implantation by theion implanter 2 are the same.

优选地，所述各缸体和驱动机构的动作顺序、时机可以为程序设定好的，或者可以为由远程操纵的方式动作的，此处不是重点，故不再赘述。Preferably, the sequence and timing of actions of the cylinders and the drive mechanism may be set by a program, or may be actuated by remote control, which is not the key point here, and will not be repeated here.

优选地，各芯片7是否到达与离子注入口24的对应位置，可以通过设置视频监控装置进行监控，或者可以通过预先设定好的位置进行确定。Preferably, whether eachchip 7 reaches a position corresponding to theion implantation port 24 can be monitored by setting a video monitoring device, or can be determined by a preset position.

优选地，在驱动筒4和/或支撑筒5上设置有抱闸机构，所述抱闸机构能够抱紧主体支撑段10，从而使得主体支撑段10能够停留在预定的转动位置处，提高离子注入机2在对晶片进行加工时的平稳度。优选地，所述抱闸机构可以为电磁抱闸机构，在需要抱紧时夹紧主体支撑段10，在需要转动主体支撑段10时放松，此处不是本发明的重点，故不再赘述。Preferably, a brake mechanism is provided on thedrive cylinder 4 and/or the support cylinder 5, and the brake mechanism can hold the mainbody support section 10 tightly, so that the mainbody support section 10 can stay at a predetermined rotational position, and improve the ionization rate. The smoothness of theimplanter 2 when processing the wafer. Preferably, the brake mechanism can be an electromagnetic brake mechanism, which clamps the mainbody support section 10 when it needs to be tightened, and relaxes when the mainbody support section 10 needs to be rotated.

优选地，步骤6)中的ESD多晶硅普注也可以通过所述离子注入设备完成，其只要调节离子注入口24的开度大小，即可实现，具体的离子注入流程与步骤8)类似，不过此处的离子注入口24则建议选择为条形孔结构，若是步骤6)和步骤8)选择同一离子注入设备完成，则在进行步骤6)时使得离子注入口24在全开和全闭之间切换，对芯片进行离子注入操作，而在进行步骤8)时，使得离子注入口24处于全闭和开一定间隙之间切换，对芯片进行离子注入操作。Preferably, the ESD polysilicon injection in step 6) can also be completed by the ion implantation equipment, which can be realized as long as the opening of theion implantation port 24 is adjusted. The specific ion implantation process is similar to that in step 8), but Theion implantation port 24 here is suggested to be a strip-shaped hole structure. If the same ion implantation equipment is selected for step 6) and step 8), theion implantation port 24 is fully opened and fully closed when step 6) is performed. When switching between, the ion implantation operation is performed on the chip, and when step 8) is performed, theion implantation port 24 is switched between fully closed and open with a certain gap, and the ion implantation operation is performed on the chip.

优选地，通过左支撑缸21、右支撑缸22、芯片支撑板13的动作，可以实时调节待离子注入的芯片7的位置，实现芯片7的特殊位置的离子注入，极大的提高了离子注入的多样性。Preferably, through the actions of theleft support cylinder 21 , theright support cylinder 22 and thechip support plate 13 , the position of thechip 7 to be ion implanted can be adjusted in real time, ion implantation at a special position of thechip 7 can be realized, and the ion implantation can be greatly improved. diversity.

虽然本发明已以较佳实施例揭露如上，然而并非用以限定本发明。任何熟悉本领域的技术人员，在不脱离本发明技术方案范围的情况下，都可利用上述揭示的技术内容对本发明技术方案做出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本发明技术方案的内容，依据本发明技术实质对以上实施例所做的任何简单修改、等同变化及修饰，均应落在本发明技术方案保护的范围内。Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art, without departing from the scope of the technical solution of the present invention, can make many possible changes and modifications to the technical solution of the present invention by using the technical content disclosed above, or modify it into an equivalent implementation of equivalent changes. example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solutions of the present invention should fall within the protection scope of the technical solutions of the present invention.

Claims (10)

1. A TRENCH MOSFET optimization process for integrating ESD diodes is characterized in that: the method comprises the following steps:

1) forming a hard mask layer: providing a substrate, and forming a hard mask layer on the substrate;

2) opening the groove: forming a groove by etching or laser beam processing;

3) sacrificial oxidation: forming a sacrificial oxide layer by thermal oxidation;

4) gate oxidation-gate polycrystalline deposition-back etching-BODY injection;

5) depositing a TEOS layer with a certain thickness, depositing ESD intrinsic polysilicon, oxidizing polysilicon thin oxygen and carrying out BODY high-temperature annealing;

6) ESD polysilicon common injection: performing P-type impurity implantation by using an ion implanter;

7) ESD polysilicon photoetching, reverse etching-source region and ESD polysilicon photoetching;

8) source region injection: performing N in a source region⁺Injecting impurities;

9) NDR annealing;

10) BPSG deposition, reflow heat treatment, lead hole photoetching, etching, lead hole silicon etching, CT injection, RTA annealing, TI and/or TIN deposition and RTP annealing, W deposition and/or Al and Cu deposition;

11) metal etching-passivation-thinning back gold.

2. A tree MOSFET optimization process integrating an ESD diode as claimed in claim 1, wherein: n is used in the whole BODY high-temperature annealing process in the step 5)₂And (6) annealing.

3. A tree MOSFET optimization process integrating an ESD diode as claimed in claim 1, wherein: the PMOS does not require the NDR anneal of step 9).

4. A tree MOSFET optimization process integrating an ESD diode as claimed in claim 1, wherein: the step 8) is completed by adopting ion implantation equipment, soThe ion implantation equipment comprises an implantation chamber (1), an ion implanter (2), a cover plate (3), a driving cylinder (4), a supporting cylinder (5) and a chip support (6), wherein the chip support (6) comprises a main body supporting section (10), and a first screw thread section (9) and a second screw thread section (19) which are arranged at two ends of the main body supporting section (10), the main body supporting section (10) is of a cylindrical structure, a plurality of supporting frames (12) are uniformly distributed on the main body supporting section (10) along the axial direction of the main body supporting section in the circumferential direction, a chip supporting plate (13) is arranged on each supporting frame (12), a chip (7) is detachably and fixedly arranged on each chip supporting plate (13), the driving cylinder (4) comprises a first supporting frame (14) and a first cylinder wall (15), a first driving screw thread (16) is arranged on the first cylinder wall (15), and the first driving screw thread (16) is meshed with the first screw thread section (9), a driving cylinder (8) is fixedly arranged on the first support frame (14), the right end of the driving cylinder (8) is abutted against the left end of the chip support (6), the ion implanter (2) is fixedly arranged at the upper end of the implantation chamber (1), the cover plate (3) is fixedly arranged at the lower end of the ion implanter (2), an ion injection opening (24) is arranged on the cover plate (3), and a sliding cover plate (26) capable of opening or closing the ion injection hole (24), wherein the sliding cover plate (26) slides under the driving of a cover plate driving mechanism, the ion implantation of the chip (7) is completed by the ion implanter (2) through the ion injection hole (24), the thread pitches of the first thread section (9) and the first driving thread (16) are set, after the driving cylinder (8) extends out to drive the chip (7) to rotate for a circle along the axis of the chip bracket (6), the distance that the chip (7) moves along the axis of the chip support (6) is two N that need to be implanted in step 8).⁺And at the interval L of the areas, a vacuumizing and vacuumizing device is also arranged in the injection chamber (1) and can vacuumize and vacuumize the injection chamber (1).

5. A TRENCH MOSFET optimization process integrating ESD diodes as claimed in claim 4, wherein: before the step 8), a plurality of chips (7) are arranged on a chip supporting plate (13), the area needing ion implantation is aligned to an ion injection hole (24), then a sliding cover plate (26) is made to seal the ion injection hole (24), a vacuumizing device is made to act to enable the interior of an implantation chamber (1) to be in a vacuum state, an ion implanter (2) is started to enter the step 8), and after ions sprayed out by the ion implanter (2) are stabilized, the ion injection hole is opened(24) Carry out ion implantation to first chip, wait to pour into the back into, close ion injection mouth (24), make actuating cylinder (8) stretch out simultaneously, promote chip support (6) and slide right, drive screw thread (16) simultaneously make support frame (12) rotatory, after rotating second chip and aim at ion injection mouth (24), stop the drive of actuating cylinder (8), make ion injection mouth (24) open simultaneously, ion implantation machine (2) carry out ion implantation to second chip, so continue to move, wait that first chip again rotates behind ion injection mouth (24), can carry out adjacent N again⁺And repeating the ion implantation of the regions, finally completing the source region implantation of all the chips, closing the ion implanter (2), and taking out all the chips to carry out the operation of the next step.

6. A TRENCH MOSFET optimization process integrating ESD diodes as claimed in claim 5, wherein: the supporting cylinder (5) comprises a cylinder wall II (18) and a supporting frame II (17), a recovery cylinder (20) is fixedly arranged on the supporting frame II (17), a thread section II (19) is arranged on the cylinder wall II (18), the thread section II (19) is meshed with the driving thread section II (11), and the recovery cylinder (20) can slide the chip support (6) leftwards after extending out, so that the initial position of the chip support (6) can be recovered.

7. A tree MOSFET optimization process integrating an ESD diode as claimed in claim 3, wherein: the number of the support frames (12) is 4, 6, 8 or 12.

8. A tree MOSFET optimization process integrating an ESD diode as claimed in claim 3, wherein: the ion injection opening (24) is of a strip-shaped hole structure.

9. A tree MOSFET optimization process integrating an ESD diode as claimed in claim 3, wherein: ion injection mouth (24) are the circular hole structure, at this moment, the rotatable setting in support frame (12) of chip backup pad (13), can rotate along the axis of support frame (12), thereby can adjust the rotation angle of chip (7), when ion injection mouth (24) are the circular hole structure, when carrying out ion implantation to first chip, make driving cylinder (8) carry out slow extension simultaneously, thereby the rotation through support frame (12), make ion implantation machine (2) can carry out the linear injection of ion on chip (7) through ion injection mouth (24), when carrying out the ion implantation this moment, at first the angle of adjustment chip (7), make the lines that ion implantation formed on chip (7) satisfy the processing requirement of chip (7).

10. A tree MOSFET optimization process integrating an ESD diode as claimed in claim 3, wherein: the ESD polysilicon common injection in the step 6) is also finished by the ion injection equipment, the ESD polysilicon common injection can be realized by only adjusting the opening size of the ion injection opening (24), the ESD polysilicon common injection and the step 8) share one ion injection equipment, the ion injection opening (24) is switched between full opening and full closing when the step 6) is carried out, the ion injection operation is carried out on the chip, and the ion injection opening (24) is switched between full closing and a certain gap opening when the step 8) is carried out, and the ion injection operation is carried out on the chip.

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