Disclosure of Invention
The application provides a method for forming a semiconductor structure, which can simplify the process for forming an inner side wall, reduce the damage to the surface of a silicon channel, and improve the quality of a source electrode and a drain electrode, thereby improving the reliability of a device.
The application provides a method for forming a semiconductor structure, which comprises the steps of providing a semiconductor substrate, forming a dummy gate layer on the top surfaces of the sacrificial layer and the channel layer, etching the sacrificial layer and the channel layer on two sides of the dummy gate layer until the surface of the semiconductor substrate is exposed, simultaneously enabling the side wall of the sacrificial layer below the dummy gate layer to form a recess, forming an oxide layer on the side wall of the sacrificial layer and the side wall of the channel layer, enabling the oxide layer on the side wall of the sacrificial layer to keep the shape of the recess, and forming an inner side wall in the recess of the oxide layer on the side wall of the sacrificial layer.
In some embodiments of the application, the material of the sacrificial layer comprises silicon germanium and the material of the channel layer comprises silicon.
In some embodiments of the application, the method of forming the plurality of sequentially stacked sacrificial layers and channel layers includes an epitaxial growth process.
In some embodiments of the application, the method of forming an oxide layer on the sacrificial layer and the channel layer sidewall includes a wet oxidation process.
In some embodiments of the application, the process parameters of the wet oxidation process include an oxidation temperature of 500 degrees celsius to 900 degrees celsius and an oxidation time of 15 minutes to 25 minutes.
In some embodiments of the application, the method for forming the inner side wall on the surface of the concave part of the oxide layer comprises the steps of forming an inner side wall material layer on the side wall of the oxide layer, and etching to remove the side wall material layer on the surface of the oxide layer on the side wall of the channel layer to expose the oxide layer on the side wall of the channel layer.
In some embodiments of the present application, the method for etching and removing the sidewall material layer on the surface of the oxide layer on the sidewall of the channel layer includes anisotropic dry etching.
In some embodiments of the application, the method for forming the semiconductor structure further comprises etching and removing the oxide layer of the channel layer side wall until the channel layer side wall is exposed, and forming a source electrode and a drain electrode on the surface of the semiconductor substrate and the channel layer side wall and the inner side wall.
In some embodiments of the application, the method of etching away the oxide layer of the channel layer sidewall exposes the channel layer sidewall includes wet etching.
In some embodiments of the application, the method of forming the source and drain on the surface of the semiconductor substrate and the channel layer sidewall and the inner sidewall includes an epitaxial growth process.
According to the method for forming the semiconductor structure, disclosed by the application, the recess is formed on the side wall of the sacrificial layer by utilizing the difference of the etching rates of the sacrificial layer and the channel layer, then the recess is further deepened by utilizing the difference of the oxidation rates of the sacrificial layer and the channel layer, and finally the inner side wall is formed in the recess, so that the process for forming the inner side wall can be simplified, the damage to the surface of a silicon channel is reduced, the quality of a source electrode and a drain electrode is improved, and the reliability of a device is improved.
Detailed Description
The following description provides specific applications and requirements of the application to enable any person skilled in the art to make and use the application. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.
The technical scheme of the invention is described in detail below with reference to the examples and the accompanying drawings.
The embodiment of the application provides a method for forming a semiconductor structure, which comprises the steps of providing a semiconductor substrate, forming a pseudo gate layer on the top surfaces of the sacrificial layer and the channel layer, etching the sacrificial layer and the channel layer on two sides of the pseudo gate layer until the surface of the semiconductor substrate is exposed, simultaneously enabling the side wall of the sacrificial layer below the pseudo gate layer to form a recess, forming an oxide layer on the side walls of the sacrificial layer and the channel layer, enabling the oxide layer on the side wall of the sacrificial layer to keep the shape of the recess, and forming an inner side wall in the recess of the oxide layer on the side wall of the sacrificial layer.
Fig. 1 to 11 are schematic structural views of steps in a method for forming a semiconductor structure according to an embodiment of the application. Fig. 1 is a perspective view, and fig. 2 to 11 are sectional views taken along the dashed line frame in fig. 1. The method for forming the semiconductor structure according to the embodiments of the present application is described in detail below with reference to the accompanying drawings.
Referring to fig. 1, a semiconductor substrate 100 is provided, and the surface of the semiconductor substrate 100 includes a plurality of sacrificial layers 110 and channel layers 120 stacked in sequence.
In some embodiments of the present application, the lowermost layer is the sacrificial layer 110 and the uppermost layer is also the sacrificial layer 110. In other embodiments of the present application, the lowermost layer is the sacrificial layer 110, and the uppermost layer may also be the channel layer 120. So long as the fully-enclosed Gate (GAA) structural feature can be achieved.
In addition, in the embodiment of the present application, only two channel layers 120 and three sacrificial layers 110 are exemplified in fig. 1, but this is not a limitation of the present application. The number of the channel layer 120 and the sacrificial layer 110 may be other numbers as long as the feature that the metal gate surrounds the silicon channel in the fully surrounding gate structure is realized. Specifically, the number of the channel layers 120 and the sacrificial layers 110 may be designed according to the difficulty of the process and the thickness of the overall structure, and in the case that the thickness of the overall structure cannot be too thick, more layers may be provided as the process allows, so as to increase the electromigration efficiency.
In some embodiments of the present application, the material of the semiconductor substrate 100 comprises (i) an elemental semiconductor, such as silicon or germanium, or the like, (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, or indium phosphide, or the like, (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, or indium gallium phosphide, or the like, or (iv) a combination thereof. In addition, the semiconductor substrate 100 may be doped (e.g., a P-type substrate or an N-type substrate). In some embodiments of the present application, the semiconductor substrate 100 may be doped with a P-type dopant (e.g., boron, indium, aluminum, or gallium) or an N-type dopant (e.g., phosphorus or arsenic).
In some embodiments of the present application, the material of the sacrificial layer 110 comprises silicon germanium and the material of the channel layer 120 comprises silicon.
In some embodiments of the present application, when the material of the sacrificial layer 110 is silicon germanium and the material of the channel layer 120 is silicon, the method for forming the plurality of sacrificial layers 110 and the channel layer 120 stacked in sequence includes an epitaxial growth process. In other embodiments of the present application, the plurality of sequentially stacked sacrificial layers 110 and channel layer 120 may also be formed by any other suitable method (e.g., a vapor deposition process).
As shown in fig. 2 to 3, a dummy gate layer 130 is formed on top of the sacrificial layer 110 and the channel layer 120. The dummy gate layer 130 is used to define the location of the metal gate, and the dummy gate layer 130 is replaced with the metal gate in a subsequent process.
In some embodiments of the present application, the method of forming the dummy gate layer 130 on the top surfaces of the sacrificial layer 110 and the channel layer 120 includes forming a dummy gate material layer 130a on the top surfaces of the sacrificial layer 110 and the channel layer 120 with reference to fig. 2, and etching the dummy gate material layer 130a to form the dummy gate layer 130 with reference to fig. 3.
In some embodiments of the present application, the method of forming the dummy gate material layer 130a on the top surfaces of the sacrificial layer 110 and the channel layer 120 includes a chemical vapor deposition process or a physical vapor deposition process, etc.
In some embodiments of the present application, the method of etching the dummy gate material layer 130a to form the dummy gate layer 130 includes wet etching, dry etching, or the like.
In some embodiments of the present application, the material of the dummy gate layer 130 is a sacrificial material that is not easily oxidized, such as silicon nitride.
Referring to fig. 4, the sacrificial layer 110 and the channel layer 120 at both sides of the dummy gate layer 130 are etched until the surface of the semiconductor substrate 100 is exposed, while recesses 111 are formed in the sidewalls of the sacrificial layer 110 under the dummy gate layer 130. Because the sacrificial layer 110 and the channel layer 120 are made of different materials, the different etching rates can be used to select the etching solution for etching the sacrificial layer 110 faster, so that due to the difference of the etching rates, the recess 111 is etched on the side wall of the sacrificial layer 110, and the etching amount of the side wall of the channel layer 120 is very small or even negligible.
In some methods of forming the semiconductor structure, the sacrificial layer 110 and the channel layer 120 on both sides of the dummy gate layer 130 are etched first until the surface of the semiconductor substrate 100 is exposed, and then an etching solution having a very high etching selectivity to the sacrificial layer 110 and the channel layer 120 is selected to etch the sacrificial layer 110 alone. This not only requires more process steps, but also requires high etching solutions and may damage the channel layer 120. In the method for forming a semiconductor structure according to the embodiment of the present application, the recess 111 may be formed by one etching using a conventional common etching solution, so that the process may be simplified and damage to the channel layer 120 may be reduced. The recess 111 is further enlarged in the subsequent process, thereby realizing the formation of the inner sidewall.
In some embodiments of the present application, the sacrificial layer 110 and the channel layer 120 on both sides of the dummy gate layer 130 are etched until the surface of the semiconductor substrate 100 is exposed, and the etching solution used to form the recess 111 on the sidewall of the sacrificial layer 110 under the dummy gate layer 130 may be a conventional dry anisotropic etching solution or an atomic layer etching solution or the like capable of etching silicon germanium.
Referring to fig. 5, an oxide layer 140 is formed on the sidewalls of the sacrificial layer 110 and the channel layer 120, and the oxide layer 140 is also formed on the surfaces of the dummy gate layer 130 and the semiconductor substrate 100, wherein the oxide layer 140 located on the sidewalls of the sacrificial layer 110 maintains the shape of the recess 111.
In some embodiments of the application, the process parameters of the wet oxidation process include an oxidation temperature of 500 degrees celsius to 900 degrees celsius, such as 550 degrees celsius, 600 degrees celsius, 650 degrees celsius, 700 degrees celsius, 750 degrees celsius, 800 degrees celsius, 850 degrees celsius, or the like, and an oxidation time of 15 minutes to 25 minutes, such as 18 minutes, 20 minutes, 23 minutes, or the like.
In some embodiments of the present application, the oxidizing gas of the wet oxidation process comprises oxygen, hydrogen, and nitrogen in a ratio of (1-3) to (12-20).
A thin oxide layer 140 is formed on the sacrificial layer 110 and the sidewall of the channel layer 120 by oxidation, and since the oxidation rate of the sacrificial layer 110 is lower than that of the channel layer 120, that is, the oxide layer on the sidewall of the sacrificial layer 110 is thinner than that on the sidewall of the channel layer 120, the recess 111 can be further deepened to form an inner sidewall.
In some embodiments of the present application, the method of forming the oxide layer on the sidewalls of the sacrificial layer 110 and the channel layer 120 includes a wet oxidation method. The wet oxidation process requires a relatively low process temperature (typically less than 900 degrees celsius) and does not result in germanium ion diffusion.
Referring to fig. 6 to 7, an inner sidewall wall 150 is formed in the recess 111 of the oxide layer 140 of the sidewall of the sacrificial layer 110. The inner sidewall 150 may reduce parasitic capacitance between the metal gate to the source and drain.
In some embodiments of the present application, the method for forming the inner sidewall 150 on the surface of the recess 111 of the oxide layer 140 includes forming an inner sidewall material layer 150a on the sidewall of the oxide layer 140, referring to fig. 6, etching to remove the sidewall material layer 150a on the surface of the oxide layer 140 on the sidewall of the channel layer 120, exposing the oxide layer 140 on the sidewall of the channel layer 120, and the remaining material in the recesses on both sides of the sacrificial layer 110 is the inner sidewall 150, referring to fig. 7. At the same time, the sidewall material layer 150a on the oxide layer 140 on the surface of the semiconductor substrate 100 and on the oxide layer 140 on the top surface of the dummy gate 130 is also removed.
In some embodiments of the present application, forming the inner sidewall material layer 150a on the sidewall of the oxide layer 140 includes a chemical vapor deposition process or a physical vapor deposition process.
In some embodiments of the present application, the method for etching to remove the sidewall material layer 150a on the surface of the oxide layer 140 on the sidewall of the channel layer 120 includes anisotropic dry etching. The anisotropic dry etching may remove only a portion of the sidewall material layer protruding from the sidewall of the channel layer 120, but not remove the sidewall material layer of the sidewall of the sacrificial layer 110.
Referring to fig. 8, in some embodiments of the present application, the method further includes etching to remove the oxide layer 140 on the sidewall of the channel layer 120 until the sidewall of the channel layer 120 is exposed. The oxide layer 140 on the sidewall of the channel layer 120 is completely exposed without the protection of the inner sidewall wall 150, and thus can be etched away. At the same time, the oxide layer 140 on the surface of the semiconductor substrate 100 and the oxide layer 140 on the top surface of the dummy gate 130 are also removed.
In some embodiments of the present application, the method of etching the oxide layer 140 from the sidewall of the channel layer 120 until the sidewall of the channel layer 120 is exposed includes wet etching.
Referring to fig. 9, a source 160 and a drain 170 are formed on the surface of the semiconductor substrate 100 and on the sidewalls of the channel layer 120 and the sidewalls of the inner sidewall 150. The positions of the source 160 and the drain 170 may be arbitrary, and the source 160 may be located on the left side, or the drain 170 may be located on the left side.
In some embodiments of the present application, the method of forming the source 160 and drain 170 on the surface of the semiconductor substrate 110 and on the sidewalls of the channel layer 120 and the sidewalls of the inner sidewall 150 includes an epitaxial growth process.
In some embodiments of the present application, the method for forming a semiconductor structure further includes removing the dummy gate layer 130 and the sacrificial layer 110 to form a cavity 180 as shown in fig. 10, and forming a metal gate 190 in the cavity 180 as shown in fig. 11.
In some embodiments of the present application, the method of removing the dummy gate layer 130 and the sacrificial layer 110 to form the void 180 includes wet etching.
In some embodiments of the present application, the method of forming the metal gate 190 in the cavity 180 includes a chemical vapor deposition process or a physical vapor deposition process or an atomic layer deposition process, etc.
In some embodiments of the present application, the material of the metal gate 190 includes aluminum or other work function metal.
With continued reference to fig. 11, in some embodiments of the present application, the oxide layer 140 on the sidewall of the metal gate 190 and the remaining sidewall material layer on the surface of the oxide layer 140 on the sidewall of the metal gate 190 may be used together as the outer sidewall of the metal gate 190. In other embodiments of the present application, the top surface and the oxide layer of the sidewall of the metal gate 190 and the remaining gate material layer on the oxide layer surface of the top surface of the sidewall of the metal gate 190 may be removed, so as to form the outer sidewall of the metal gate 190 separately.
The method for forming the semiconductor structure saves the complex process of INNER SPACER recess etching, is realized through a simple process of film deposition, and can be compatible with the conventional GAA process. The method comprises the steps of forming a SiGe recess serving as a starting end of INNER SPACER in a source electrode and drain electrode back etching process by utilizing a small difference of etching rates of SiGe and Si, further forming a distance difference between the outer side of SiGe and a protrusion on the surface of Si by utilizing the difference of oxidation rates of the SiGe and the Si to form INNER SPACER, depositing a side wall material layer on all surfaces, etching the side wall material layer on the surface of Si by utilizing a height difference of the protrusion of the side wall material layer on the surface of Si, fully etching the side wall material layer on the surface of Si by utilizing anisotropic dry etching to expose an oxidation layer, wrapping the SiGe and other surfaces by the side wall material layer, removing the oxidation layer on the surface of a channel layer by utilizing the difference of wet etching of the oxidation layer and the side wall material layer, exposing the channel layer required by epitaxy, and forming an inner side wall structure at the same time.
According to the method for forming the semiconductor structure, disclosed by the application, the recess is formed on the side wall of the sacrificial layer by utilizing the difference of the etching rates of the sacrificial layer and the channel layer, then the recess is further deepened by utilizing the difference of the oxidation rates of the sacrificial layer and the channel layer, and finally the inner side wall is formed in the recess, so that the process for forming the inner side wall can be simplified, the damage to the surface of a silicon channel is reduced, the quality of a source electrode and a drain electrode is improved, and the reliability of a device is improved.
In view of the foregoing, it will be evident to those skilled in the art after reading this disclosure that the foregoing application may be presented by way of example only and may not be limiting. Although not explicitly described herein, those skilled in the art will appreciate that the present application is intended to embrace a variety of reasonable alterations, improvements and modifications to the embodiments. Such alterations, improvements, and modifications are intended to be within the spirit and scope of the exemplary embodiments of the application.
It should be understood that the terms "and/or" as used in this embodiment include any and all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present.
Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means without intermediate elements. It will be further understood that the terms "comprises," "comprising," "includes," or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be further understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element in some embodiments could be termed a second element in other embodiments without departing from the teachings of the present application. Like reference numerals or like reference numerals designate like elements throughout the specification.
Furthermore, the present description describes example embodiments with reference to idealized example cross-sectional and/or plan and/or perspective views. Thus, differences from the illustrated shapes, due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.