Disclosure of Invention
The present invention aims to provide an output stage circuit and an audio device, which can solve the above problems.
An aspect of an embodiment of the present invention provides an output stage circuit, including:
The first output power tube is connected between the power end and the target output end;
The second output power tube is connected between the ground end and the target output end;
the first delay driving circuit is connected with the control end of the first output power tube;
The second delay driving circuit is connected with the control end of the second output power tube;
wherein:
Under the condition of inputting a first voltage signal, the second delay driving circuit controls the second output power tube to enter a cut-off state, and the first delay driving circuit gradually reduces the voltage of the control end of the first input power tube so as to gradually increase the voltage of the target output end;
under the condition of inputting a second voltage signal, the first delay driving circuit controls the first output power tube to enter a cut-off state, and the second delay driving circuit gradually pulls up the voltage of the control end of the second input power tube so as to gradually pull down the voltage of the target output end.
Optionally, the first output power tube includes a first PMOS tube;
the second output power tube comprises a first NMOS tube;
The first delay driving circuit includes: the first input end of the OR gate is connected with the target input end through an inverter, and the second input end of the OR gate is connected with the grid electrode of the first NMOS tube; the first RC delay circuit comprises a first resistor and a first capacitor, and is connected between the power supply end and the output end of the OR gate through a first switch or between the target output end and the output end of the OR gate through a second switch; the grid electrode of the second PMOS tube is connected with the target input end, the source electrode of the second PMOS tube is connected with the power supply end, and the drain electrode of the second PMOS tube is connected between the first resistor and the first capacitor; and a common joint among the first resistor, the first capacitor and the second PMOS tube is used as an output end of the first delay driving circuit and is used for connecting a grid electrode of the first PMOS tube and controlling the on and off of the first PMOS tube.
Optionally, the second delay driving circuit includes: the first input end of the AND gate is connected with the target input end through an inverter, and the second input end of the AND gate is connected with the grid electrode of the first PMOS tube; the second RC delay circuit comprises a second resistor and a second capacitor, and is connected between the ground terminal and the output terminal of the AND gate through a third switch or between the target output terminal and the output terminal of the AND gate through a fourth switch; the grid electrode of the second NMOS tube is connected with the target input end, the source electrode of the second NMOS tube is connected with the ground end, and the drain electrode of the second NMOS tube is connected between the second resistor and the second capacitor; and a common joint among the second resistor, the second capacitor and the second NMOS tube is used as an output end of the second delay driving circuit and is used for connecting a grid electrode of the first NMOS tube and controlling the on and off of the first NMOS tube.
Optionally, in a first delay mode, the first switch is connected, the second switch is disconnected, the third switch is connected, and the fourth switch is disconnected; in a second delay mode, the first switch is turned off, the second switch is turned on, the third switch is turned off, and the fourth switch is turned on.
Optionally, the target input terminal is configured to receive a PWM signal;
and the PWM signal is obtained by carrying out differential and coding according to the output signal of the class-D power amplifier.
An aspect of an embodiment of the present invention further provides an output stage circuit, including:
An inverter whose input terminal is a target input terminal of the output stage circuit;
the first delay driving circuit is connected with the output end of the inverter;
The second delay driving circuit is connected with the output end of the inverter;
The grid electrode of the first PMOS tube is connected with the first delay driving circuit, and the source electrode of the first PMOS tube is connected with the power supply end;
The grid electrode of the first NMOS tube is connected with the second delay driving circuit, and the source electrode of the first NMOS tube is connected with the ground terminal;
The drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube, and a common joint between the drain electrode of the first PMOS tube and the drain electrode of the first NMOS tube is used as a target output end of the output stage circuit;
Wherein the first delay driving circuit includes: the first input end of the OR gate is connected with the output end of the inverter, and the second input end of the OR gate is connected with the grid electrode of the first NMOS tube; the first RC delay circuit comprises a first resistor and a first capacitor, and is connected between the power supply end and the output end of the OR gate through a first switch or between the target output end and the output end of the OR gate through a second switch; the grid electrode of the second PMOS tube is connected with the target input end, the source electrode of the second PMOS tube is connected with the power supply end, and the drain electrode of the second PMOS tube is connected between the first resistor and the first capacitor; the common junction among the first resistor, the first capacitor and the second PMOS tube is used as an output end of the first delay driving circuit and is used for connecting a grid electrode of the first PMOS tube and controlling the on and off of the first PMOS tube;
Wherein the second delay driving circuit includes: the first input end of the AND gate is connected with the output end of the inverter, and the second input end of the AND gate is connected with the grid electrode of the first PMOS tube; the second RC delay circuit comprises a second resistor and a second capacitor, and is connected between the ground end and the output end of the AND gate through a third switch or between the target output end and the output end of the AND gate through a fourth switch; the grid electrode of the second NMOS tube is connected with the target input end, the source electrode of the second NMOS tube is connected with the ground end, and the drain electrode of the second NMOS tube is connected between the second resistor and the second capacitor; and a common joint among the second resistor, the second capacitor and the second NMOS tube is used as an output end of the second delay driving circuit and is used for connecting a grid electrode of the first NMOS tube and controlling the on and off of the first NMOS tube.
An aspect of an embodiment of the present invention further provides an audio apparatus, including:
a class D power amplifier for providing an output signal;
the PWM encoder is used for carrying out difference and encoding according to the output signals of the class-D power amplifier to obtain PWM signals;
the output stage circuit is used for receiving the PWM signal and adjusting the output voltage of the output stage circuit based on the PWM signal.
Optionally, the PWM encoder is configured to:
Encoding the first differential signal to obtain a first quantized value; wherein the first differential signal is a differential signal of the output signal of the class D power amplifier;
Encoding the second differential signal to obtain a second quantized value; wherein the second differential signal is another differential signal of the output signal of the class D power amplifier.
Optionally, the PWM signal is obtained by combining a first quantization value and a second quantization value that are phase-staggered with each other.
Optionally, the signal to be encoded is encoded with a unit of quantization bit number N, and the encoding process is as follows: according to the quantization bit number N, coding the signals to be coded corresponding to the N clock periods in a symmetrical coding mode with the middle of the N clock periods as a starting point and gradually expanding towards two sides;
When the signal to be encoded is the first differential signal, encoding to obtain the first quantized value;
And when the signal to be encoded is the second differential signal, encoding to obtain the second quantized value.
According to the output stage circuit and the audio device, the first delay driving circuit and the second delay driving circuit are used for realizing fast and slow switching of the first power output pipe and the second power output pipe, so that output overshoot can be reduced to a great extent, and the condition of direct output is avoided. That is, the driving waveform of the output stage can be prevented from overshooting to avoid audio distortion, the signal to noise ratio of the output signal is improved, and the influence of power supply backflow is avoided to ensure the reliability of the power supply.
In order to make the above objects, features and advantages of the present invention more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. This invention may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to be within the scope of the present invention.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
In the description of the present invention, it should also be noted that, unless explicitly stated and limited otherwise, the terms "disposed," "connected," and "electrically connected" are to be construed broadly, and may be, for example, directly connected or indirectly connected through an intermediary, or may be in communication with each other between two elements. It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.
Some embodiments of the present invention are described in detail below with reference to the accompanying drawings. The following embodiments and features of the embodiments may be combined with each other without conflict.
The invention relates to the term interpretation:
PWM: pulse width modulation, pulse stretching modulation.
Class_d audio power amplifier: class D audio power amplifier.
And (3) AND gate: a gate circuit, the output Y is the and logic of the input signals a and B, y=a & B.
Or gate: a gate circuit, the output Y is the or logic of the input signals a and B, y=a+b.
An inverter: a gate circuit outputs Y as the NOT logic of an input signal A, Y= -A.
The inventors found that: with the popularization of wireless headphones, users have higher and higher requirements on the endurance function of the headphones, and the endurance time is prolonged as much as possible while the tone quality is ensured. Therefore, more and more audio power amplifiers start to give up the structures of the CLASS_AB and the CLASS_G with lower output efficiency, and the CLASS_D power amplifier structure with higher efficiency and lower power consumption is adopted. The power amplifier of the class_d structure is comparable to other power amplifiers in performance, and has higher requirements for the PWM signal input thereto.
The inventors found that: the output of the class_d power amplifier is a high-frequency PWM square wave, and its frequency spectrum not only includes the audio signal of the low frequency band but also includes a very large number of high-frequency components, and a part of energy may still remain after the high-frequency components finally pass through the low-pass filter, which is reflected as noise, thereby affecting the sound quality. Therefore, how to optimize the PWM output signal becomes a key to design a high performance class_d power amplifier. The signal quality of PWM output is mainly affected in two ways, namely, the encoding mode of PWM modulation and the driving waveform of the output stage.
Specifically:
(1) Coding scheme of PWM modulation: because PWM codes are output through a chip clock, and clock signals inevitably have jitter, and the differential output paths of PWM often have certain mismatch, the phase difference exists between the differential output waveforms of PWM, and thus burrs are generated to cause the output tone quality to be poor. Meanwhile, if the PWM coding is not reasonable enough, the code density difference on two sides of the differential output is too large, more noise may be introduced and the service life of the speaker may be affected.
(2) Driving waveform of output stage: the large overshoot is easy to generate, the audio distortion is caused, the signal to noise ratio of the output signal is reduced, and even a certain degree of power supply backflow can occur to influence the reliability of the power supply.
In view of this, embodiments of the present invention provide an output stage circuit and an audio device, so that the power amplifier of the class_d structure is comparable to other power amplifiers in performance.
Specific:
(1) A new output stage circuit is provided.
The special design mode of 'fast-closing slow-opening' is adopted, so that output overshoot can be reduced to a great extent, and the condition of output straight-through is avoided. Meanwhile, the output circuit also has two delay modes so as to adapt to different working scenes, and the best output performance can be obtained under different scenes.
(2) A new PWM coding scheme is provided.
The new PWM coding mode can ensure that more uniform code density is output in a differential mode, and is less sensitive to phase errors caused by clock jitter and channel mismatch, thereby ensuring high quality of output audio signals and protecting the use of a loudspeaker.
The specific method adopts a symmetrical coding mode with a central starting point in the time domain, the change between each data is only 1 bit, and the signals of the two paths of differential output are completely symmetrical, so that the performance of the differential output is ensured to be as ideal as possible. In addition, the final output data can be represented by flexible differential values, so that the uniformity of the output code density is further enhanced, and the noise is reduced.
Example 1
Fig. 1 schematically shows a circuit diagram of an output stage circuit according to a first embodiment of the invention. As shown in fig. 1, the output stage circuit according to the present invention may include: the first output power tube, the second output power tube, the first delay driving circuit X1 and the second delay driving circuit X2.
The first output power tube is connected between the power supply end VDD and the target output end VOUT;
The second output power tube is connected between the ground end GND and the target output end VOUT;
the first delay driving circuit X1 is connected with the control end of the first output power tube;
the second delay driving circuit X2 is connected with the control end of the second output power tube;
Wherein: under the condition that a first voltage signal is input to a target input end VIN, the second delay driving circuit X2 controls the second output power tube to enter a cut-off state, the first delay driving circuit X1 gradually pulls down the voltage of the control end of the first input power tube, and the on-resistance of the first output power tube is controlled to gradually shrink, so that the voltage of the target output end VOUT is gradually pulled up; under the condition that the second voltage signal is input to the target input end VIN, the first delay driving circuit X1 controls the first output power tube to enter a cut-off state, the second delay driving circuit X2 gradually pulls up the voltage of the control end of the second input power tube, and the on-resistance of the second output power tube is controlled to gradually shrink, so that the voltage of the target output end VOUT is gradually pulled down.
In this embodiment, the first output power tube and the second output power tube may be an effector tube. In other embodiments, the circuit design may be modified with different types of field effect transistors or transistors in the output stage circuit, as desired for the circuit design.
In the embodiment of the invention, the fast-closing slow-opening of the first power output pipe and the second power output pipe is realized through the first delay driving circuit X1 and the second delay driving circuit X2, so that the output overshoot can be reduced to a great extent, and the condition of direct output is avoided. That is, the driving waveform of the output stage can be prevented from overshooting to avoid audio distortion, the signal to noise ratio of the output signal is improved, and the influence of power supply backflow is avoided to ensure the reliability of the power supply.
In an exemplary embodiment, as shown in FIG. 2:
the first output power tube comprises a first PMOS tube P1;
the second output power tube comprises a first NMOS tube N1;
in order to ensure that the output power is sufficiently large, the dimensions of the first PMOS transistor P1 and the first NMOS transistor N1 may be designed to be relatively large, so that the output impedance may be reduced.
The first delay driving circuit X1 includes: the OR gate, the first RC delay circuit and the second PMOS tube P2; wherein:
The first input end of the OR gate is connected with the target input end VIN through an inverter, and the second input end of the OR gate is connected with the grid electrode of the first NMOS tube N1;
The first RC delay circuit comprises a first resistor R1 and a first capacitor C1, and is connected between the power supply end VDD and the output end of the OR gate through a first switch K1 or between the target output end VOUT and the output end of the OR gate through a second switch K2;
the grid electrode of the second PMOS tube P2 is connected with the target input end VIN, the source electrode of the second PMOS tube P2 is connected with the power supply end VDD, and the drain electrode of the second PMOS tube P2 is connected between the first resistor R1 and the first capacitor C1;
The common junction between the first resistor R1, the first capacitor C1 and the second PMOS transistor P2 is used as an output end of the first delay driving circuit X1, and is used to connect to the gate of the first PMOS transistor P1, to control the on and off of the first PMOS transistor P1.
In an exemplary embodiment, the second delay driving circuit X2 includes:
the first input end of the AND gate is connected with the target input end VIN through an inverter, and the second input end of the AND gate is connected with the grid electrode of the first PMOS tube P1;
the second RC delay circuit comprises a second resistor R2 and a second capacitor C2, and is connected between the ground end GND and the output end of the AND gate through a third switch K3 or between the target output end VOUT and the output end of the AND gate through a fourth switch K4;
the grid electrode of the second NMOS tube N2 is connected with the target input end VIN, the source electrode of the second NMOS tube N2 is connected with the ground end, and the drain electrode of the second NMOS tube N2 is connected between the second resistor R2 and the second capacitor C2;
The common junction between the second resistor R2, the second capacitor C2, and the second NMOS transistor N2 is used as an output end of the second delay driving circuit X2, and is used to connect to the gate of the first NMOS transistor N1, to control on and off of the first NMOS transistor N1.
In an exemplary embodiment, the output stage circuit further has two delay modes to adapt to different working scenarios, so as to ensure that the best output performance can be obtained in different scenarios. In the first delay mode, the first switch K1 is connected, the second switch K2 is disconnected, the third switch K3 is connected, and the fourth switch K4 is disconnected; in the second delay mode, the first switch K1 is turned off, the second switch K2 is turned on, the third switch K3 is turned off, and the fourth switch K4 is turned on.
In an exemplary embodiment:
The target input terminal VIN is configured to receive a PWM signal;
and the PWM signal is obtained by carrying out differential and coding according to the output signal of the class-D power amplifier.
In order to make the present embodiment easier to understand, the working principle of the present output stage circuit is explained below with reference to fig. 2 and 3. Fig. 3 provides a timing diagram of the present output stage circuit.
As shown in fig. 2, a first delay driving circuit X1 composed of an or gate, a first resistor R1, a first capacitor C1, and a second PMOS transistor P2 is used to drive a gate vg_p of the first PMOS transistor P1; the second delay driving circuit X2 composed of the and gate, the second resistor R2, the second capacitor C2, and the second NMOS transistor N2 is used to drive the gate vg_n of the first NMOS transistor N1. The input signal of the target input end VIN is directly connected to the gates of the second PMOS tube P2 and the second NMOS tube N2 and is connected to one end of an AND gate and one end of an OR gate through an inverter; the second input end of the OR gate is connected with the grid VG_N of the first NMOS tube N1; the second input end of the AND gate is connected with the grid VG_P of the first PMOS tube P1. The other end of the first capacitor C1 may be selectively connected to the power supply terminal VDD or the target output terminal VOUT through the switches K1 and K2, the other end of the second capacitor C2 may be selectively connected to the ground terminal GND or the target output terminal VOUT through the switches K3 and K4, in the first delay mode, the other end of the first capacitor C1 is connected to the power supply terminal VDD and the other end of the second capacitor C2 is connected to the ground terminal GND, and in the second delay mode, the other end of the first capacitor C1 and the other end of the second capacitor C2 are both connected to the target output terminal VOUT. The output signal of the target output terminal VOUT and the input signal of the target input terminal VIN have the same phase.
Referring to fig. 3, when the input signal of the target input terminal VIN is switched from low to high, the second PMOS transistor P2 is turned off, the second NMOS transistor N2 is turned on, the gate vg_n of the first NMOS transistor N1 is rapidly pulled down by the second NMOS transistor N2, the first NMOS transistor N1 is rapidly turned off, at this time, the first PMOS transistor P1 is not yet turned on, and both input signals of the or gate are low, so the low level signal output by the or gate will slowly pull down the gate vg_p of the first PMOS transistor P1 through the first RC delay circuit formed by the first resistor R1 and the first capacitor C1, and then the voltage of the target output terminal VOUT becomes high. When the input signal of the target input end VIN is converted from high to low, the second PMOS transistor P2 is turned on, the second NMOS transistor N2 is turned off, the gate vg_p of the first PMOS transistor P1 is pulled up by the second PMOS transistor P2, the first PMOS transistor P1 is turned off rapidly, the first NMOS transistor N1 is not turned on at this time, both input signals of the and gate are high, so that the high level signal output by the and gate will pull up the gate vg_n of the first NMOS transistor N1 slowly through the second RC delay circuit composed of the second resistor R2 and the second capacitor C2, and then the voltage of the target output end VOUT becomes low. In contrast, the delay time of the first delay mode is shorter, and the delay time of the second delay mode is longer, so that the method is suitable for different application scenes. The working mode of 'fast-closing slow-opening' of the first PMOS tube P1 and the first NMOS tube N1 can greatly reduce output burrs on output signals of the output end VOUT, and a short period of closing all the first PMOS tube P1 and the first NMOS tube N1 exists, so that the direct risk from the power supply end VDD to the ground end GND is avoided.
Example two
The specific principle of this embodiment is the same as that of the first embodiment, and this is not repeated.
Fig. 2 schematically shows a circuit diagram of an output stage circuit according to a second embodiment of the invention.
An inverter whose input terminal is a target input terminal of the output stage circuit;
the first delay driving circuit is connected with the output end of the inverter;
The second delay driving circuit is connected with the output end of the inverter;
the grid electrode of the first PMOS tube P1 is connected with the first delay driving circuit, and the source electrode of the first PMOS tube P1 is connected with the power supply end VDD;
The grid electrode of the first NMOS tube N1 is connected with the second delay driving circuit, and the source electrode of the first NMOS tube N1 is connected with the ground end GND;
The drain electrode of the first PMOS transistor P1 is connected with the drain electrode of the first NMOS transistor N1, and a common junction therebetween is used as a target output end of the output stage circuit;
wherein the first delay driving circuit includes:
The first input end of the OR gate is connected with the output end of the inverter, and the second input end of the OR gate is connected with the grid electrode of the first NMOS tube N1;
The first RC delay circuit comprises a first resistor R1 and a first capacitor C1, and is connected between the power supply end VDD and the output end of the OR gate through a first switch K1 or between the target output end VOUT and the output end of the OR gate through a second switch K2;
the grid electrode of the second PMOS tube P2 is connected with the target input end VIN, the source electrode of the second PMOS tube P2 is connected with the power supply end VDD, and the drain electrode of the second PMOS tube P2 is connected between the first resistor R1 and the first capacitor C1;
The common junction between the first resistor R1, the first capacitor C1 and the second PMOS tube P2 is used as an output end of the first delay driving circuit and is used for connecting a grid electrode of the first PMOS tube P1 to control the on and off of the first PMOS tube P1;
wherein the second delay driving circuit includes:
The first input end of the AND gate is connected with the output end of the inverter, and the second input end of the AND gate is connected with the grid electrode of the first PMOS tube P1;
The second RC delay circuit comprises a second resistor R2 and a second capacitor C2, and is connected between the ground terminal and the output terminal of the AND gate through a third switch K3 or between the target output terminal VOUT and the output terminal of the AND gate through a fourth switch K4;
the grid electrode of the second NMOS tube is connected with the target input end VIN, the source electrode of the second NMOS tube is connected with the ground end GND, and the drain electrode of the second NMOS tube is connected between the second resistor R2 and the second capacitor C2;
The common junction between the second resistor R2, the second capacitor C2 and the second NMOS transistor N2 is used as an output end of the second delay driving circuit, and is used to connect to the gate of the first NMOS transistor N1, to control the on and off of the first NMOS transistor N1.
Example III
The present embodiment provides a PWM encoding scheme based on the first and second embodiments.
An audio device, comprising:
a class D power amplifier for providing an output signal;
the PWM encoder is used for carrying out difference and encoding according to the output signals of the class-D power amplifier to obtain PWM signals;
and the output stage circuit is used for receiving the PWM signal and adjusting the output voltage (namely, the voltage of a target output end) of the output stage circuit based on the PWM signal. It should be noted that the output and the circuit may adopt the technical solutions provided in the first and second embodiments.
In an exemplary said, the PWM encoder is configured to:
Encoding the first differential signal to obtain a first quantized value; wherein the first differential signal is a differential signal of the output signal of the class D power amplifier;
Encoding the second differential signal to obtain a second quantized value; wherein the second differential signal is another differential signal of the output signal of the class D power amplifier.
In the exemplary description:
The PWM signal is obtained by combining a first quantized value and a second quantized value which are staggered in phase.
In the exemplary description:
and coding the signal to be coded by taking the quantization bit number N as a unit, wherein the coding process is as follows: according to the quantization bit number N, coding the signals to be coded corresponding to the N clock periods in a symmetrical coding mode with the middle of the N clock periods as a starting point and gradually expanding towards two sides;
When the signal to be encoded is the first differential signal, encoding to obtain the first quantized value;
And when the signal to be encoded is the second differential signal, encoding to obtain the second quantized value.
In order to make the present embodiment easier to understand, the working principle of the present output stage circuit is explained below with reference to fig. 4 and 5. Fig. 5 provides a time domain waveform using the present PWM encoding scheme.
As shown in fig. 4, the two differential signals are denoted as a first differential signal pwm_p and a second differential signal pwm_n, and take 4bit quantization coding as an example (the quantization bit number can be flexibly adjusted in practical application), and each of positive and negative 8 quantization values corresponds to 8 clock cycles. The encoded values are finally converted into output duty ratios of PWM_P and PWM_N in the time domain, taking the output duty ratio of 0 as a reference, if the duty ratio of the output of the PWM_P terminal is 1/8 to represent +1, and if the duty ratio of the output of the PWM_N terminal is 3/8 to represent-3.
The starting point of the encoded output is at the middle of 8 clock cycles, and each data increment follows one clock cycle extending forward and backward in sequence. Compared with other starting point positions, the output mode can obtain better output uniformity, the sensitivity of the difference between the PWM_P and the PWM_N to the time Zhong Maoci and the channel delay difference can be greatly reduced, burrs possibly contained in the differential signal are eliminated, and the quality of the output signal is improved.
As shown in fig. 5, this may further illustrate the advantages of the PWM encoding method provided in this embodiment. Since the differential signal of the output PWM has a value from-8 to +8, most of the intermediate data can be obtained by subtraction, instead of the pure one side outputting 0 and the other side outputting absolute value. For example, when the difference value of the pwm_p-pwm_n to be output is +2, a combination of pwm_p=3 and pwm_n=1 (or other numerical combinations) may be selected, and as shown in the left half waveform of fig. 5, the signal edges of pwm_p and pwm_n are completely staggered in phase, so that the signal edges are not affected by clock jitter or channel delay, and burrs are avoided. When the differential output is-1, as shown in the waveform of the right half of fig. 5, if the combination of pwm_p=1 and pwm_n=2 is selected, the output signals will be aligned at the falling edge, and there is a possibility of generating glitches, and at this time, pwm_p=0 and pwm_n=1 may be selected, thereby eliminating the glitches.
It can be understood that the differential output signals pwm_p and pwm_n of PWM can be applied to the speaker through the output stage circuits of the first and second embodiments to achieve the advantages of uniform output code density, no burr, low overshoot, high reliability and high signal to noise ratio.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.