CN114430519A

Movatterモバイル変換

Info

Publication number: CN114430519A
Application number: CN202210121702.XA
Authority: CN
Inventors: 詹昶; 谭波
Original assignee: Shenzhen Wood Core Technology Co ltd
Current assignee: Shenzhen Wood Core Technology Co ltd
Priority date: 2022-02-09
Filing date: 2022-02-09
Publication date: 2022-05-03
Anticipated expiration: 2042-02-09
Also published as: CN114430519B

Abstract

An embodiment of the present invention provides an output stage circuit, including: the first output power tube is connected between a power supply end and a target output end; the second output power tube is connected between the ground end and the target output end; the first delay driving circuit is connected with the control end of the first output power tube; and the second delay driving circuit is connected with the control end of the second output power tube. The embodiment of the invention also provides the audio equipment. The technical scheme provided by the invention realizes the 'fast switching and slow switching' of the first power output tube and the second power output tube, thereby greatly reducing the output overshoot and avoiding the situation of direct connection of output. Therefore, the drive waveform of the output stage can not be overshot to avoid audio distortion, the signal to noise ratio of the output signal is improved, and the influence of power supply backward flow is avoided to ensure the reliability of the power supply.

Description

Output stage circuit and audio equipment

Technical Field

The invention relates to the technical field of audio power amplification, in particular to an output stage circuit and audio equipment.

Background

Along with the popularization of wireless earphones, users have higher and higher requirements on the endurance function of the earphones, and the endurance time needs to be prolonged as far as possible while the tone quality is ensured. Therefore, more and more audio power amplifiers begin to give up structures such as CLASS _ AB and CLASS _ G with lower output efficiency, and adopt a CLASS _ D power amplifier structure with higher efficiency and lower power consumption.

A class D power amplifier (also called digital audio power amplifier) is a common power amplifier in the market at present, and drives a speaker to operate by controlling a high-side switching tube and a low-side switching tube in an output stage circuit of the class D power amplifier to be alternately turned on. The driving waveform output by the output stage circuit of the class-D power amplifier is prone to generate large overshoot to cause audio distortion, reduce the signal-to-noise ratio of the output signal, and even cause a certain degree of power supply backflow to affect the reliability of the power supply.

Disclosure of Invention

The present invention is directed to an output stage circuit and an audio device, which can solve the above problems.

An aspect of an embodiment of the present invention provides an output stage circuit, including:

the first output power tube is connected between a power supply end and a target output end;

the second output power tube is connected between the ground end and the target output end;

the first delay driving circuit is connected with the control end of the first output power tube;

the second delay driving circuit is connected with the control end of the second output power tube;

wherein:

under the condition of inputting a first voltage signal, the second delay driving circuit controls the second output power tube to enter a cut-off state, and the first delay driving circuit gradually pulls down the voltage of the control end of the first input power tube so as to gradually pull up the voltage of the target output end;

under the condition of inputting a second voltage signal, the first delay driving circuit controls the first output power tube to enter a cut-off state, and the second delay driving circuit gradually pulls up the voltage of the control end of the second input power tube so as to gradually pull down the voltage of the target output end.

Optionally, the first output power transistor includes a first PMOS transistor;

the second output power tube comprises a first NMOS tube;

the first delay driving circuit includes: the first input end of the OR gate is connected with the target input end through the phase inverter, and the second input end of the OR gate is connected with the grid electrode of the first NMOS tube; the first RC time delay circuit comprises a first resistor and a first capacitor and is connected between the power supply end and the output end of the OR gate through a first switch or connected between the target output end and the output end of the OR gate through a second switch; a grid electrode of the second PMOS tube is connected with the target input end, a source electrode of the second PMOS tube is connected with the power supply end, and a drain electrode of the second PMOS tube is connected between the first resistor and the first capacitor; and a common joint among the first resistor, the first capacitor and the second PMOS tube is used as an output end of the first delay driving circuit and is used for connecting a grid electrode of the first PMOS tube and controlling the conduction and the cut-off of the first PMOS tube.

Optionally, the second delay driving circuit includes: the first input end of the AND gate is connected with the target input end through a phase inverter, and the second input end of the AND gate is connected with the grid electrode of the first PMOS tube; the second RC time delay circuit comprises a second resistor and a second capacitor and is connected between the ground end and the output end of the AND gate through a third switch or between the target output end and the output end of the AND gate through a fourth switch; a grid electrode of the second NMOS tube is connected with the target input end, a source electrode of the second NMOS tube is connected with the ground end, and a drain electrode of the second NMOS tube is connected between the second resistor and the second capacitor; and a common joint among the second resistor, the second capacitor and the second NMOS tube is used as an output end of the second time delay driving circuit and is used for connecting a grid electrode of the first NMOS tube and controlling the on and off of the first NMOS tube.

Optionally, in a first delay mode, the first switch is turned on, the second switch is turned off, the third switch is turned on, and the fourth switch is turned off; in a second delay mode, the first switch is turned off, the second switch is turned on, the third switch is turned off, and the fourth switch is turned on.

Optionally, the target input end is configured to receive a PWM signal;

and the PWM signal is obtained by carrying out difference and coding according to the output signal of the D-type power amplifier.

An aspect of an embodiment of the present invention further provides an output stage circuit, including:

an inverter, the input end of which is used as the target input end of the output stage circuit;

the first delay driving circuit is connected with the output end of the phase inverter;

the second delay driving circuit is connected with the output end of the phase inverter;

the grid electrode of the first PMOS tube is connected with the first delay driving circuit, and the source electrode of the first PMOS tube is connected with a power supply end;

the grid electrode of the first NMOS tube is connected with the second time delay driving circuit, and the source electrode of the first NMOS tube is connected with the ground end;

the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube, and a common joint point between the drain electrode of the first PMOS tube and the drain electrode of the first NMOS tube is used as a target output end of the output stage circuit;

wherein the first delay driving circuit includes: the first input end of the OR gate is connected with the output end of the phase inverter, and the second input end of the OR gate is connected with the grid electrode of the first NMOS tube; the first RC time delay circuit comprises a first resistor and a first capacitor and is connected between the power supply end and the output end of the OR gate through a first switch or connected between the target output end and the output end of the OR gate through a second switch; a grid electrode of the second PMOS tube is connected with the target input end, a source electrode of the second PMOS tube is connected with the power supply end, and a drain electrode of the second PMOS tube is connected between the first resistor and the first capacitor; a common junction point among the first resistor, the first capacitor and the second PMOS tube is used as an output end of the first delay driving circuit and is used for connecting a grid electrode of the first PMOS tube and controlling the conduction and the cut-off of the first PMOS tube;

wherein the second delay driving circuit includes: the first input end of the AND gate is connected with the output end of the phase inverter, and the second input end of the AND gate is connected with the grid electrode of the first PMOS tube; the second RC time delay circuit comprises a second resistor and a second capacitor and is connected between the ground end and the output end of the AND gate through a third switch or between the target output end and the output end of the AND gate through a fourth switch; a grid electrode of the second NMOS tube is connected with the target input end, a source electrode of the second NMOS tube is connected with the ground end, and a drain electrode of the second NMOS tube is connected between the second resistor and the second capacitor; and a common joint among the second resistor, the second capacitor and the second NMOS tube is used as an output end of the second delay drive circuit and is used for connecting a grid electrode of the first NMOS tube and controlling the conduction and the cut-off of the first NMOS tube.

An aspect of an embodiment of the present invention further provides an audio device, including:

a class D power amplifier for providing an output signal;

the PWM encoder is used for carrying out difference and encoding according to the output signal of the D-type power amplifier to obtain a PWM signal;

the output stage circuit is used for receiving the PWM signal and adjusting the output voltage of the output stage circuit based on the PWM signal.

Optionally, the PWM encoder is configured to:

coding the first differential signal to obtain a first quantized value; wherein the first differential signal is a differential signal of an output signal of the class-D power amplifier;

coding the second differential signal to obtain a second quantized value; wherein the second differential signal is another differential signal of the output signal of the class-D power amplifier.

Optionally, the PWM signal is obtained by combining a first quantization value and a second quantization value, which are mutually staggered in phase.

Optionally, the signal to be encoded is encoded by using the quantization bit number N as a unit, and the encoding process is as follows: according to the quantization bit number N, coding signals to be coded corresponding to the N clock cycles in a symmetrical coding mode that the middle part of the N clock cycles is taken as a starting point and gradually expands towards two sides;

when the signal to be coded is the first differential signal, coding to obtain the first quantized numerical value;

and when the signal to be coded is the second differential signal, coding to obtain the second quantized numerical value.

According to the output stage circuit and the audio equipment, the first delay driving circuit and the second delay driving circuit are used for realizing fast switching and slow switching of the first power output tube and the second power output tube, so that output overshoot can be reduced to a great extent, and the condition of direct connection of output is avoided. Therefore, overshoot is avoided in the driving waveform of the output stage, audio distortion is avoided, the signal-to-noise ratio of the output signal is improved, and the influence of power supply backward flowing is avoided to ensure the reliability of the power supply.

In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.

Fig. 1 schematically shows a circuit diagram of an output stage circuit according to a first embodiment of the present invention.

Fig. 2 schematically shows another circuit diagram of the output stage circuit according to the first embodiment of the present invention.

Fig. 3 schematically shows a time domain waveform diagram using the output stage circuit of fig. 2.

Fig. 4 schematically shows a PWM encoding method according to a third embodiment of the present invention.

Fig. 5 is a schematic diagram of a time domain waveform using the PWM coding scheme of fig. 4.

Description of the main element symbols:

a power supply terminal VDD;

a ground terminal GND;

a target input VIN;

a target output terminal VOUT;

a first PMOS transistor P1;

a second PMOS transistor P2;

a first NMOS transistor N1;

a second NMOS transistor N2;

a first resistor R1;

a second resistor R2;

a first capacitance C1;

a second capacitance C2;

a first delay driver circuit X1;

the second delay driver circuit X2.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. The present invention may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

In the description of the present invention, it should also be noted that, unless otherwise explicitly specified or limited, the terms "disposed," "connected," and "electrically connected" are to be construed broadly and may be, for example, directly connected, indirectly connected through an intermediary agent, or communicated between two elements. It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.

Some embodiments of the invention are described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.

Interpretation of terms to which the invention relates:

PWM: pulse width modulation, Pulse width modulation.

CLASS _ D audio power amplifier: class D audio power amplifiers.

And gate: a gate circuit, the output Y is the AND logic of input signals A and B, Y is A & B.

Or gate: a gate circuit, the output Y is the OR logic of the input signals A and B, Y is A + B.

An inverter: a gate circuit, the output Y is the 'NOT' logic of the input signal A, and Y is equal to A.

The inventor finds that: along with the popularization of wireless earphones, users have higher and higher requirements on the endurance function of the earphones, and the endurance time needs to be prolonged as far as possible while the tone quality is ensured. Therefore, more and more audio power amplifiers begin to give up structures such as CLASS _ AB and CLASS _ G with lower output efficiency, and adopt a more efficient and lower power consumption CLASS _ D power amplifier structure. The power amplifier with the CLASS _ D structure is compared favorably with other power amplifiers in performance, and higher requirements are generated on the input PWM signals.

The inventor finds that: the output of the CLASS _ D power amplifier is a high-frequency PWM square wave, the frequency spectrum of which not only contains the audio signal of the low frequency band but also includes a lot of high-frequency components, and a part of energy may still remain after the high-frequency components finally pass through the low-pass filter, which is reflected as noise, thereby affecting the sound quality. Therefore, how to optimize the output signal of PWM becomes the key to design high performance CLASS _ D power amplifier. The quality of the signal output by the PWM is mainly affected by two aspects, namely, the encoding mode of the PWM modulation and the driving waveform of the output stage.

Specifically, the method comprises the following steps:

(1) encoding mode of PWM modulation: because the PWM code is output by the chip clock, the clock signal inevitably has jitter, and the differential output paths of the PWM often have a certain mismatch, which causes a phase difference between the differential output waveforms of the PWM, thereby generating glitches to deteriorate the output sound quality. Meanwhile, if the PWM coding is not reasonable enough, the difference of the code density on both sides of the differential output is too large, which may introduce more noise and affect the service life of the speaker.

(2) Drive waveform of the output stage: the audio distortion is easily caused by large overshoot, the signal-to-noise ratio of the output signal is reduced, and even a certain degree of power supply backward flow is generated to influence the reliability of the power supply.

In view of this, the embodiments of the present invention provide an output stage circuit and an audio device, so that the power amplifier with the CLASS _ D structure can be compared with other power amplifiers in terms of performance.

Specifically, the method comprises the following steps:

(1) a new output stage circuit is provided.

A special design mode of 'fast switch and slow switch' is adopted, so that output overshoot can be reduced to a great extent, and the condition of direct connection of output is avoided. Meanwhile, the output circuit is also provided with two delay modes to adapt to different working scenes so as to ensure that the optimal output performance can be obtained in different scenes.

(2) And a new PWM coding mode is provided.

The new PWM coding mode can ensure that more uniform code density is output in a differential mode, and is less sensitive to phase errors caused by clock jitter and channel mismatching, so that high quality of output audio signals is ensured, and the use of a loudspeaker is protected.

Specifically, a symmetrical coding mode of a central starting point is adopted in a time domain, the change of each data is only 1 bit, and signals of two paths of differential outputs are completely symmetrical, so that the performance of the differential outputs is ensured to be ideal as far as possible. In addition, the final output data can be expressed by adopting flexible difference numerical values, so that the uniformity of the output code density is further enhanced, and the noise is reduced.

Example one

Fig. 1 schematically shows a circuit diagram of an output stage circuit according to a first embodiment of the present invention. As shown in fig. 1, the output stage circuit according to the present invention may include: the circuit comprises a first output power tube, a second output power tube, a first delay driving circuit X1 and a second delay driving circuit X2.

A first output power transistor connected between a power supply terminal VDD and a target output terminal VOUT;

the second output power tube is connected between a ground end GND and the target output end VOUT;

the first time delay driving circuit X1 is connected with the control end of the first output power tube;

the second time delay driving circuit X2 is connected with the control end of the second output power tube;

wherein: under the condition that a first voltage signal is input to a target input end VIN, the second delay driving circuit X2 controls the second output power tube to enter an off state, the first delay driving circuit X1 gradually pulls down the voltage of the control end of the first input power tube, and controls the on-resistance of the first output power tube to gradually decrease, so as to gradually pull up the voltage of the target output end VOUT; under the condition that a second voltage signal is input to the target input end VIN, the first delay driving circuit X1 controls the first output power tube to enter an off state, and the second delay driving circuit X2 gradually pulls up the voltage of the control end of the second input power tube, controls the on-resistance of the second output power tube to gradually decrease, and thus gradually pulls down the voltage of the target output end VOUT.

In this embodiment, the first output power tube and the second output power tube may be effect tubes, etc. In other embodiments, the circuit design may be modified by different types of fets or transistors in the output stage circuit according to the requirements of the circuit design.

In the embodiment of the invention, the first delay driving circuit X1 and the second delay driving circuit X2 are used for realizing the fast switching and slow switching of the first power output tube and the second power output tube, so that the output overshoot can be reduced to a great extent, and the condition of direct connection of output is avoided. Therefore, the drive waveform of the output stage can not be overshot to avoid audio distortion, the signal to noise ratio of the output signal is improved, and the influence of power supply backward flow is avoided to ensure the reliability of the power supply.

In an exemplary embodiment, as shown in FIG. 2:

the first output power tube comprises a first PMOS tube P1;

the second output power tube comprises a first NMOS tube N1;

it should be noted that, in order to ensure a sufficient output power, the sizes of the first PMOS transistor P1 and the first NMOS transistor N1 may be designed to be relatively large, so as to reduce the output impedance.

The first delay driver circuit X1 includes: the OR gate, the first RC time delay circuit and the second PMOS pipe P2; wherein:

the first input end of the or gate is connected with the target input end VIN through an inverter, and the second input end of the or gate is connected with the grid electrode of the first NMOS transistor N1;

a first RC delay circuit including a first resistor R1 and a first capacitor C1, connected between the power source terminal VDD and the output terminal of the or gate through a first switch K1, or connected between the target output terminal VOUT and the output terminal of the or gate through a second switch K2;

a second PMOS transistor P2, having a gate connected to the target input terminal VIN, a source connected to the power terminal VDD, and a drain connected between the first resistor R1 and the first capacitor C1;

the common junction among the first resistor R1, the first capacitor C1 and the second PMOS transistor P2 is used as the output end of the first delay driving circuit X1, and is used for connecting the gate of the first PMOS transistor P1 and controlling the on and off of the first PMOS transistor P1.

In an exemplary embodiment, the second delay driver X2 includes:

a first input end of the AND gate is connected with the target input end VIN through a phase inverter, and a second input end of the AND gate is connected with the grid electrode of the first PMOS tube P1;

the second RC delay circuit comprises a second resistor R2 and a second capacitor C2, and is connected between the ground end GND and the output end of the AND gate through a third switch K3, or is connected between the target output end VOUT and the output end of the AND gate through a fourth switch K4;

a second NMOS transistor N2, having a gate connected to the target input VIN, a source connected to the ground, and a drain connected between the second resistor R2 and the second capacitor C2;

a common junction point among the second resistor R2, the second capacitor C2, and the second NMOS transistor N2 serves as an output end of the second delay driver circuit X2, and is used for connecting a gate of the first NMOS transistor N1 and controlling on and off of the first NMOS transistor N1.

In an exemplary embodiment, the output stage circuit further has two delay modes to adapt to different working scenarios, so as to ensure that the optimal output performance can be obtained under different scenarios. In the first delay mode, the first switch K1 is connected, the second switch K2 is disconnected, the third switch K3 is connected, and the fourth switch K4 is disconnected; in the second delay mode, the first switch K1 is turned off, the second switch K2 is turned on, the third switch K3 is turned off, and the fourth switch K4 is turned on.

In an exemplary embodiment:

the target input end VIN is used for receiving a PWM signal;

and the PWM signal is obtained by carrying out difference and coding according to the output signal of the class D power amplifier.

In order to make the present embodiment easier to understand, the operation principle of the present output stage circuit is explained below with reference to fig. 2 and 3. Fig. 3 provides a timing diagram of the present output stage circuit.

As shown in fig. 2, the first delay driver circuit X1, which is composed of the or gate, the first resistor R1, the first capacitor C1, and the second PMOS transistor P2, is used to drive the gate VG _ P of the first PMOS transistor P1; the second delay driving circuit X2, which is composed of the and gate, the second resistor R2, the second capacitor C2, and the second NMOS transistor N2, is used to drive the gate VG _ N of the first NMOS transistor N1. An input signal of a target input end VIN is directly connected to the grid electrodes of a second PMOS tube P2 and a second NMOS tube N2 and is connected to one end of an AND gate and an OR gate through an inverter; the second input end of the OR gate is connected with a gate VG _ N of the first NMOS tube N1; the second input end of the AND gate is connected with the gate VG _ P of the first PMOS tube P1. The other terminal of the first capacitor C1 can be selectively connected to the power supply terminal VDD or the target output terminal VOUT through the switches K1 and K2, the other terminal of the second capacitor C2 can be selectively connected to the ground terminal GND or the target output terminal VOUT through the switches K3 and K4, the other terminal of the first capacitor C1 is connected to the power supply terminal VDD and the other terminal of the second capacitor C2 is connected to the ground terminal GND in the first delay mode, and the other terminal of the first capacitor C1 and the other terminal of the second capacitor C2 are both connected to the target output terminal VOUT in the second delay mode. The phase of the output signal of the target output terminal VOUT is the same as the phase of the input signal of the target input terminal VIN.

Referring to fig. 3, when the input signal of the target input terminal VIN is converted from low to high, the second PMOS transistor P2 is turned off, the second NMOS transistor N2 is turned on, the gate VG _ N of the first NMOS transistor N1 is pulled down by the second NMOS transistor N2 quickly, the first NMOS transistor N1 is turned off quickly, at this time, the first PMOS transistor P1 is not yet turned on, and both input signals of the or gate are low, so that the low level signal output by the or gate will slowly pull down the gate VG _ P of the first PMOS transistor P1 through the first RC delay circuit formed by the first resistor R1 and the first capacitor C1, and then the voltage of the target output terminal VOUT becomes high. When the input signal of the target input end VIN is converted from high to low, the second PMOS transistor P2 is turned on, the second NMOS transistor N2 is turned off, the gate VG _ P of the first PMOS transistor P1 is pulled up by the second PMOS transistor P2 quickly, the first PMOS transistor P1 is turned off quickly, at this time, the first NMOS transistor N1 is not yet turned on, and both input signals of the and gate are high, so that the high level signal output by the and gate will slowly pull up the gate VG _ N of the first NMOS transistor N1 through the second RC delay circuit composed of the second resistor R2 and the second capacitor C2, and then the voltage of the target output end VOUT becomes low. In contrast, the delay time of the first delay mode is shorter, and the delay time of the second delay mode is longer, so as to adapt to different application scenarios. The working mode of 'fast switching and slow switching' of the first PMOS tube P1 and the first NMOS tube N1 can greatly reduce output burrs on an output signal of the target output end VOUT, a short time period for turning off both exists in the first PMOS tube P1 and the first NMOS tube N1, and the risk of direct connection from a power supply end VDD to a ground end GND is eliminated.

Example two

The specific principle of the embodiment is the same as that of the embodiment one, and the detailed description thereof is omitted.

Fig. 2 schematically shows a circuit diagram of an output stage circuit according to a second embodiment of the present invention.

An inverter having an input terminal as a target input terminal of the output stage circuit;

the grid electrode of the first PMOS pipe P1 is connected with the first delay driving circuit, and the source electrode of the first PMOS pipe P1 is connected with a power supply end VDD;

the grid electrode of the first NMOS tube N1 is connected with the second time delay driving circuit, and the source electrode of the first NMOS tube N1 is connected with the ground end GND;

the drain electrode of the first PMOS pipe P1 and the drain electrode of the first NMOS pipe N1 are connected, and the common joint point between the two is used as the target output end of the output stage circuit;

wherein the first delay driving circuit includes:

the first input end of the OR gate is connected with the output end of the inverter, and the second input end of the OR gate is connected with the grid electrode of the first NMOS transistor N1;

a common junction point among the first resistor R1, the first capacitor C1 and the second PMOS transistor P2 is used as an output end of the first delay driving circuit, and is used for connecting a gate of the first PMOS transistor P1 and controlling on and off of the first PMOS transistor P1;

wherein the second delay driving circuit includes:

the first input end of the AND gate is connected with the output end of the phase inverter, and the second input end of the AND gate is connected with the grid electrode of the first PMOS tube P1;

the second RC time delay circuit comprises a second resistor R2 and a second capacitor C2, and is connected between the ground end and the output end of the AND gate through a third switch K3, or is connected between the target output end VOUT and the output end of the AND gate through a fourth switch K4;

a second NMOS transistor having a gate connected to the target input terminal VIN, a source connected to the ground terminal GND, and a drain connected between the second resistor R2 and the second capacitor C2;

a common junction point among the second resistor R2, the second capacitor C2, and the second NMOS transistor N2 serves as an output end of the second delay driver circuit, and is used for connecting a gate of the first NMOS transistor N1 and controlling on and off of the first NMOS transistor N1.

EXAMPLE III

In this embodiment, on the basis of the first embodiment and the second embodiment, a coding scheme of PWM is provided.

An audio device, comprising:

a class D power amplifier for providing an output signal;

and the output stage circuit is used for receiving the PWM signal and adjusting the output voltage (namely the voltage of the target output end) of the output stage circuit based on the PWM signal. It should be noted that the output and the circuit may adopt the technical solutions provided in the first and second embodiments.

In an exemplary said, the PWM encoder is for:

In the exemplary description:

the PWM signal is obtained by combining a first quantized value and a second quantized value which are mutually staggered in phase.

In the exemplary description:

coding a signal to be coded by taking the quantization bit number N as a unit, wherein the coding process is as follows: according to the quantization bit number N, coding signals to be coded corresponding to the N clock cycles in a symmetrical coding mode that the middle part of the N clock cycles is taken as a starting point and gradually expands towards two sides;

In order to make the present embodiment easier to understand, the working principle of the present output stage circuit is explained below with reference to fig. 4 and 5. Fig. 5 provides a time domain waveform using the present PWM coding scheme.

As shown in fig. 4, the two differential signals are denoted as a first differential signal PWM _ P and a second differential signal PWM _ N, and take 4-bit quantization coding as an example (in practical application, the quantization bit number can be flexibly adjusted), and each of the positive and negative 8 quantization values corresponds to 8 clock cycles. The encoded values are finally converted into output duty ratios of PWM _ P and PWM _ N in time domain, takingoutput duty ratio 0 as reference, if the duty ratio of the output of PWM _ P terminal is 1/8 to represent +1, and if the duty ratio of the output of PWM _ N terminal is 3/8 to represent-3.

The starting position of the encoded output starts in the middle of 8 clock cycles and each data increment follows a sequential one clock cycle expansion to the front and back. Compared with the output mode of other starting point positions, the output uniformity can be better obtained, the sensitivity of the difference value of PWM _ P and PWM _ N to clock glitch and channel delay difference can be greatly reduced, glitches possibly contained in the differential signal are eliminated, and the quality of the output signal is improved.

As shown in fig. 5, it can further illustrate the advantages of the PWM encoding method provided by the present embodiment. Since the value of the differential signal of the output PWM is from-8 to +8, most of the intermediate data can be obtained by subtraction, rather than simply outputting 0 on one side and absolute value on the other side. For example, when the difference between PWM _ P-PWM _ N to be output is +2, a combination of PWM _ P being 3 and PWM _ N being 1 (or other combinations of values) may be selected, and the signal edges of PWM _ P and PWM _ N are completely staggered in phase as shown in the left half of fig. 5, so that the influence of clock jitter or channel delay is avoided, and glitch generation is avoided. When the differential output is-1, as shown in the right half of the waveform of fig. 5, if the combination of PWM _ P-1 and PWM _ N-2 is selected, the output signals are aligned at the falling edge, and there is a possibility of generating glitches, and at this time, PWM _ P-0 and PWM _ N-1 can be selected, so as to eliminate the glitches.

It can be understood that the differential output signals PWM _ P and PWM _ N of PWM are applied to the speaker through the output stage circuits of the first and second embodiments, so as to combine the advantages of the two, and achieve the characteristics of uniform output code density, no glitch, low overshoot, high reliability, and high signal-to-noise ratio.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An output stage circuit, comprising:

wherein:

2. The output stage circuit of claim 1, wherein:

the first output power tube comprises a first PMOS tube;

the second output power tube comprises a first NMOS tube;

the first delay driving circuit includes:

the first input end of the OR gate is connected with the target input end through the phase inverter, and the second input end of the OR gate is connected with the grid electrode of the first NMOS tube;

the first RC time delay circuit comprises a first resistor and a first capacitor and is connected between the power supply end and the output end of the OR gate through a first switch or connected between the target output end and the output end of the OR gate through a second switch;

a grid electrode of the second PMOS tube is connected with the target input end, a source electrode of the second PMOS tube is connected with the power supply end, and a drain electrode of the second PMOS tube is connected between the first resistor and the first capacitor;

and a common joint among the first resistor, the first capacitor and the second PMOS tube is used as an output end of the first delay driving circuit and is used for connecting a grid electrode of the first PMOS tube and controlling the conduction and the cut-off of the first PMOS tube.

3. The output stage circuit of claim 2, wherein:

the second delay driver circuit includes:

the first input end of the AND gate is connected with the target input end through a phase inverter, and the second input end of the AND gate is connected with the grid electrode of the first PMOS tube;

the second RC time delay circuit comprises a second resistor and a second capacitor and is connected between the ground end and the output end of the AND gate through a third switch or between the target output end and the output end of the AND gate through a fourth switch;

a grid electrode of the second NMOS tube is connected with the target input end, a source electrode of the second NMOS tube is connected with the ground end, and a drain electrode of the second NMOS tube is connected between the second resistor and the second capacitor;

and a common joint among the second resistor, the second capacitor and the second NMOS tube is used as an output end of the second time delay driving circuit and is used for connecting a grid electrode of the first NMOS tube and controlling the on and off of the first NMOS tube.

4. The output stage circuit of claim 3, wherein:

in a first delay mode, the first switch is connected, the second switch is disconnected, the third switch is connected, and the fourth switch is disconnected;

in a second delay mode, the first switch is turned off, the second switch is turned on, the third switch is turned off, and the fourth switch is turned on.

5. The output stage circuit of claims 2-4, wherein:

the target input end is used for receiving a PWM signal;

6. An output stage circuit, comprising:

the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube, and a common joint between the drain electrode of the first PMOS tube and the drain electrode of the first NMOS tube is used as a target output end of the output stage circuit;

wherein the first delay driving circuit includes:

the first input end of the OR gate is connected with the output end of the phase inverter, and the second input end of the OR gate is connected with the grid electrode of the first NMOS tube;

a common junction point among the first resistor, the first capacitor and the second PMOS tube is used as an output end of the first delay driving circuit and is used for connecting a grid electrode of the first PMOS tube and controlling the conduction and the cut-off of the first PMOS tube;

wherein the second delay driving circuit includes:

the first input end of the AND gate is connected with the output end of the phase inverter, and the second input end of the AND gate is connected with the grid electrode of the first PMOS tube;

and a common joint among the second resistor, the second capacitor and the second NMOS tube is used as an output end of the second delay drive circuit and is used for connecting a grid electrode of the first NMOS tube and controlling the conduction and the cut-off of the first NMOS tube.

7. An audio device, comprising:

a class D power amplifier for providing an output signal;

the output stage circuit of any one of claims 1 to 6, configured to receive the PWM signal and to adjust an output voltage of the output stage circuit based on the PWM signal.

8. The audio device of claim 7, wherein the PWM encoder is configured to:

9. The audio device of claim 8, wherein:

10. Audio device according to claim 8 or 9, characterized in that: