

技术领域technical field
本发明涉及电子技术领域,具体是一种新型多相交错反激变换器自动功率均衡控制电路。The invention relates to the field of electronic technology, in particular to a novel automatic power balance control circuit of a multi-phase interleaved flyback converter.
背景技术Background technique
反激变换器由其结构简单、成本低被广泛应用,但是反激变换器具有较大的输出电流尖峰、输出功率有限等问题,而多相交错反激变换器的提出能够较好地解决反激变换器的上述缺点。多相交错反激变换器工作时,各相功率开关管交替开关,通过变压器对负载端提供能量,但是由于关键部件反激变压器生产工艺偏差及磁芯导磁率偏差会导致变压器电感量离散度可达±20%,导致变换器各相输出功率存在较大偏差的问题,进而可能导致某相因输出功率过大而损坏,因此功率均衡控制技术对改善变换器各相输出功率的均衡性及多相交错变换器的系统可靠性非常重要。The flyback converter is widely used due to its simple structure and low cost, but the flyback converter has problems such as large output current spikes and limited output power. The above-mentioned disadvantages of the exciter converter. When the multi-phase interleaved flyback converter is working, the power switches of each phase switch alternately, and the load is supplied with energy through the transformer. However, due to the deviation of the production process of the key components of the flyback transformer and the deviation of the magnetic permeability of the magnetic core, the inductance dispersion of the transformer can be increased. Up to ±20%, resulting in a large deviation of the output power of each phase of the converter, which may lead to damage to a certain phase due to excessive output power. Therefore, the power balance control technology can improve the balance and efficiency of the output power of each phase of the converter. The system reliability of the interleaved converter is very important.
目前,多相交错反激变换器多采用控制变压器等关键器件生产工艺的方式来缩小各相输出功率偏差,但是加严管控生产工艺会大大提高了生产成本,并降低生产效率,且功率偏差也只能控制在约±10%内。平均电流自动均流技术在多路变换器并联系统中是一种常用的功率均衡控制技术,即通过检测各变换器输出电流信号,并求取其平均值,作为公共信号,某路输出电流信号与平均值公共信号之差代表着该路功率均衡误差。通过误差信号调整该路变换器的基准电压,微调其输出电压,进而达到均衡输出功率的目的。平均电流自动均流技术在多路变换器并联系统中对功率均衡非常有效,但在多相交错反激变换器中采用该控制技术,由于各相共用输出端口,所以无法实现单独控制各相输出电压来调整该相输出功率的目的。但平均电流自动均流技术中,多路变换器选用电流平均值作为公共信号的思路值得借鉴。At present, the multi-phase interleaved flyback converter mostly adopts the method of controlling the production process of key components such as transformers to reduce the output power deviation of each phase, but tightening the control of the production process will greatly increase the production cost and reduce the production efficiency, and the power deviation It can only be controlled within about ±10%. The average current automatic current sharing technology is a commonly used power balance control technology in the multi-channel converter parallel system, that is, by detecting the output current signal of each converter, and obtaining the average value, as a common signal, a certain channel output current signal The difference from the average common signal represents the power equalization error of this channel. The reference voltage of the converter is adjusted by the error signal, and its output voltage is fine-tuned, so as to achieve the purpose of balancing the output power. The average current automatic current sharing technology is very effective for power balance in the parallel system of multi-channel converters, but this control technology is used in multi-phase interleaved flyback converters. Since each phase shares the output port, it is impossible to control the output of each phase independently. voltage to adjust the output power of that phase. However, in the automatic current sharing technology of average current, the idea of selecting the current average value as the common signal for the multiplexer is worth learning.
发明内容SUMMARY OF THE INVENTION
本发明的目的在于提供一种新型多相交错反激变换器自动功率均衡控制电路,以解决上述背景技术中提出的问题。The purpose of the present invention is to provide a novel automatic power equalization control circuit of a multi-phase interleaved flyback converter to solve the above-mentioned problems in the background art.
为实现上述目的,本发明提供如下技术方案:To achieve the above object, the present invention provides the following technical solutions:
一种新型多相交错反激变换器自动功率均衡控制电路,包含VIN采样电路、原边电流采样电路ISEN、积分电路U1、乘法电路U2、比较器U3、误差放大器U4、相位控制器、栅极驱动电路、功率MOS管Q1、变压器T、二极管D1、输出电容Co和负载模块,所述VIN采样电路与各相积分电路U1连接;相位控制器与各相栅极驱动电路连接;误差放大器U4输出端与各相比较器U3同相输入端连接;误差放大器U4电路反相输入端与输出电容Co正极相连;误差放大器U4同相输入端与基准电压Vref相连;输出电容Co并联负载模块,输出电容Co正极与各相二极管D1阴极相连,输出电容Co负极接输出地;原边电流采样电路ISEN与乘法电路U2输入端相连;积分电路U1与乘法电路U2另一输入端相连;乘法电路U2输出端与比较器U3反相输入端相连,比较器U3输出端与栅极驱动电路相连;栅极驱动电路输出端与功率MOS管栅极相连;功率MOS管源极通过原边电流采样电路ISEN与地相连;变压器T原边绕组同名端与输入电压VIN相连,另一端与功率MOS管漏极相连;变压器T副边绕组同名端接输出地,另一端与二极管D1阳极相连。A new type of multi-phase interleaved flyback converter automatic power balance control circuit, including VIN sampling circuit, primary current sampling circuit ISEN, integrating circuit U1, multiplying circuit U2, comparator U3, error amplifier U4, phase controller, gate Drive circuit, power MOS transistor Q1, transformer T, diode D1, output capacitor Co and load module, the VIN sampling circuit is connected to each phase integrating circuit U1; the phase controller is connected to each phase gate drive circuit; the error amplifier U4 outputs The terminal is connected to the non-inverting input terminal of each phase comparator U3; the inverting input terminal of the error amplifier U4 circuit is connected to the positive pole of the output capacitor Co; the non-inverting input terminal of the error amplifier U4 is connected to the reference voltage Vref; the output capacitor Co is connected in parallel with the load module, and the positive pole of the output capacitor Co is connected It is connected to the cathode of each phase diode D1, and the negative electrode of the output capacitor Co is connected to the output ground; the primary current sampling circuit ISEN is connected to the input end of the multiplication circuit U2; the integration circuit U1 is connected to the other input end of the multiplication circuit U2; the output end of the multiplication circuit U2 is connected to the comparison The inverting input end of the comparator U3 is connected, the output end of the comparator U3 is connected to the gate drive circuit; the output end of the gate drive circuit is connected to the gate of the power MOS tube; the source of the power MOS tube is connected to the ground through the primary current sampling circuit ISEN; The same-named end of the primary winding of the transformer T is connected to the input voltage VIN, and the other end is connected to the drain of the power MOS transistor; the same-named end of the secondary winding of the transformer T is connected to the output ground, and the other end is connected to the anode of the diode D1.
作为本发明的进一步方案:所述积分电路U1与乘法电路U2构成LII电路。As a further solution of the present invention: the integrating circuit U1 and the multiplying circuit U2 form an LII circuit.
作为本发明的进一步方案:所述相位控制器还产生各相所需时钟信号,并与各相栅极驱动电路相连。As a further solution of the present invention: the phase controller also generates clock signals required for each phase and is connected to the gate driving circuits of each phase.
作为本发明的进一步方案:所述积分电路U1对VIN采样电路信号进行[t,t+Ton]时间内的积分运算,其中,t为变换器某相功率MOS管Q1开通时刻,Ton为功率MOS管Q1开通时长,积分电路U1输出信号与原边电流采样信号ISEN经过乘法电路U2运算后产生上升信号K1K2LmIp2,即LII电路最终产生抛物线状上升信号K1K2LmIp2,然后与误差放大器U4输出信号进行比较,产生驱动关断信号,相位控制器产生各相时钟信号,保证变换器各相之间具有相同的工作频率及固定合理的相位偏移间隔,变换器各相相应时钟信号与上述驱动关断信号共同作用于栅极驱动电路产生PWM驱动脉冲,控制功率MOS管Q1的通断,进行电能转换。As a further solution of the present invention: the integration circuit U1 performs an integration operation on the VIN sampling circuit signal within the time [t, t+Ton], where t is the time when the power MOS transistor Q1 of a certain phase of the converter is turned on, and Ton is the power MOS transistor When the tube Q1 is turned on, the output signal of the integrating circuit U1 and the primary current sampling signal ISEN are operated by the multiplication circuit U2 to generate a rising signal K1 K2 LmIp2 , that is, the LII circuit finally generates a parabolic rising signal K1 K2 LmIp2 , and then Compare with the output signal of the error amplifier U4 to generate the drive-off signal, and the phase controller generates the clock signal of each phase to ensure that each phase of the converter has the same operating frequency and a fixed and reasonable phase offset interval, and each phase of the converter corresponds to The clock signal and the above-mentioned drive turn-off signal act together on the gate drive circuit to generate PWM drive pulses, control the on-off of the power MOS transistor Q1, and perform power conversion.
作为本发明的进一步方案:所述VIN采样电路采样的信号包括输入电压采样线性系数K1和变换器输入直流电压VIN。As a further solution of the present invention: the signal sampled by the VIN sampling circuit includes the input voltage sampling linear coefficient K1 and the converter input DC voltage VIN.
作为本发明的进一步方案:所述原边电流采样电路ISEN采样的信号包括原边电流采样线性系数K2和原边电流Ip。As a further solution of the present invention: the signal sampled by the primary current sampling circuit ISEN includes the primary current sampling linear coefficient K2 and the primary current Ip.
与现有技术相比,本发明的有益效果是:Compared with the prior art, the beneficial effects of the present invention are:
1.实现多相交错变换器各相输出功率自动均衡控制,防止某相输出功率过大而损坏,提高变换器工作可靠性;1. Realize the automatic equalization control of the output power of each phase of the multi-phase interleaved converter, prevent the output power of a certain phase from being too large and damaged, and improve the working reliability of the converter;
2.变换器各相输出功率逐周期控制,可快速响应负载的动态变化,实现各相输出功率快速准确均衡控制。2. The output power of each phase of the converter is controlled cycle by cycle, which can quickly respond to the dynamic change of the load and achieve fast and accurate balanced control of the output power of each phase.
附图说明Description of drawings
图1为本发明的电路原理图;Fig. 1 is the circuit schematic diagram of the present invention;
图2为本发明以双相交错反激变换器为例的关键信号波形图。FIG. 2 is a key signal waveform diagram of the present invention taking a bi-phase interleaved flyback converter as an example.
具体实施方式Detailed ways
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.
请参阅图1-2,一种新型多相交错反激变换器自动功率均衡控制电路,包含VIN采样电路、原边电流采样电路ISEN、积分电路U1、乘法电路U2、比较器U3、误差放大器U4、相位控制器、栅极驱动电路、功率MOS管Q1、变压器T、二极管D1、输出电容Co和负载模块,所述VIN采样电路与各相积分电路U1连接;相位控制器与各相栅极驱动电路连接;误差放大器U4输出端与各相比较器U3同相输入端连接;误差放大器U4电路反相输入端与输出电容Co正极相连;误差放大器U4同相输入端与基准电压Vref相连;输出电容Co并联负载模块,输出电容Co正极与各相二极管D1阴极相连,输出电容Co负极接输出地;原边电流采样电路ISEN与乘法电路U2输入端相连;积分电路U1与乘法电路U2另一输入端相连;乘法电路U2输出端与比较器U3反相输入端相连,比较器U3输出端与栅极驱动电路相连;栅极驱动电路输出端与功率MOS管栅极相连;功率MOS管源极通过原边电流采样电路ISEN与地相连;变压器T原边绕组同名端与输入电压VIN相连,另一端与功率MOS管漏极相连;变压器T副边绕组同名端接输出地,另一端与二极管D1阳极相连。Please refer to Figure 1-2, a new type of multi-phase interleaved flyback converter automatic power balance control circuit, including VIN sampling circuit, primary current sampling circuit ISEN, integrating circuit U1, multiplying circuit U2, comparator U3, error amplifier U4 , phase controller, gate drive circuit, power MOS transistor Q1, transformer T, diode D1, output capacitor Co and load module, the VIN sampling circuit is connected to each phase integrating circuit U1; the phase controller is connected to each phase gate driver Circuit connection; the output end of the error amplifier U4 is connected to the non-inverting input end of each phase comparator U3; the inverting input end of the error amplifier U4 circuit is connected to the positive pole of the output capacitor Co; the non-inverting input end of the error amplifier U4 is connected to the reference voltage Vref; the output capacitor Co is connected in parallel In the load module, the positive electrode of the output capacitor Co is connected to the cathode of each phase diode D1, and the negative electrode of the output capacitor Co is connected to the output ground; the primary current sampling circuit ISEN is connected to the input end of the multiplication circuit U2; the integrating circuit U1 is connected to the other input end of the multiplication circuit U2; The output end of the multiplication circuit U2 is connected to the inverting input end of the comparator U3, the output end of the comparator U3 is connected to the gate drive circuit; the output end of the gate drive circuit is connected to the gate of the power MOS tube; the source of the power MOS tube passes the primary current The sampling circuit ISEN is connected to the ground; the primary winding of the transformer T is connected to the input voltage VIN, and the other end is connected to the drain of the power MOS transistor; the secondary winding of the transformer T is connected to the output ground, and the other end is connected to the anode of the diode D1.
图1中,Vref为基准电压;Vo为多相交错变换器输出电压;K1为输入电压采样线性系数;K2为原边电流采样线性系数;Ip为原边电流;VIN为变换器输入直流电压;Lm为变压器T初级励磁电感;In Figure 1, Vref is the reference voltage; Vo is the output voltage of the multi-phase interleaved converter; K1 is the input voltage sampling linear coefficient; K2 is the primary current sampling linear coefficient; Ip is the primary current; VIN is the converter input DC voltage; Lm is the primary excitation inductance of transformer T;
LII电路由积分电路U1和乘法电路U2共同构成,积分电路U1对VIN采样电路信号K1VIN进行[t,t+Ton]时间内的积分运算(t为变换器某相功率MOS管Q1开通时刻,Ton为功率MOS管Q1开通时长),积分电路U1输出信号与原边电流采样信号ISEN经过乘法电路U2运算后产生图1中抛物线状上升信号K1K2LmIp2,即LII电路最终产生抛物线状上升信号K1K2LmIp2,然后与误差放大器输出信号COM进行比较,产生驱动关断信号。相位控制器产生各相时钟信号,保证变换器各相之间具有相同的工作频率及固定合理的相位偏移间隔。变换器各相相应时钟信号与上述驱动关断信号共同作用于栅极驱动电路产生PWM驱动脉冲,控制功率MOS管Q1的通断,进行电能转换。The LII circuit is composed of the integration circuit U1 and the multiplication circuit U2. The integration circuit U1 performs the integration operation in the [t, t+Ton] time for the VIN sampling circuit signal K1 VIN (t is the turn-on moment of the power MOS transistor Q1 of a certain phase of the converter) , Ton is the turn-on time of the power MOS transistor Q1), the output signal of the integrating circuit U1 and the primary current sampling signal ISEN are operated by the multiplication circuit U2 to generate the parabolic rising signal K1 K2 LmIp2 in FIG. 1 , that is, the LII circuit finally generates a parabola The rising signal K1 K2 LmIp2 is then compared with the error amplifier output signal COM to generate a drive-off signal. The phase controller generates clock signals for each phase to ensure that each phase of the converter has the same operating frequency and a fixed and reasonable phase offset interval. The corresponding clock signal of each phase of the converter and the above-mentioned drive turn-off signal work together on the gate drive circuit to generate PWM drive pulses, control the on-off of the power MOS transistor Q1, and perform power conversion.
以双相交错反激变换器为例,关键波形图如图(2)示,描述上述工作过程。Taking the two-phase interleaved flyback converter as an example, the key waveform diagram is shown in Figure (2) to describe the above working process.
具体原理推导如下:The specific principle is deduced as follows:
功率MOS管Q1导通期间,由法拉第电磁感应定理,变压器T原边绕组电压:During the conduction period of the power MOS transistor Q1, according to Faraday's theorem of electromagnetic induction, the voltage of the primary winding of the transformer T is:
在[t,t+Ton]时间内,对VIN采样信号K1VIN进行积分。变换器各相在功率MOS管Q1关断之后对LII电路中的积分电路U1进行复位,输出清零,为下个开关周期中积分运算作准备。式(1)两端同时乘以K1并进行积分,得:The VIN sampled signal K1 VIN is integrated over time [t,t+Ton]. Each phase of the converter resets the integral circuit U1 in the LII circuit after the power MOS transistor Q1 is turned off, and the output is cleared to prepare for the integral operation in the next switching cycle. Multiplying both ends of equation (1) by K1 and integrating at the same time, we get:
K1VIN*Ton=K1Lm(Ipmax) (2)K1 VIN*Ton=K1 Lm(Ipmax ) (2)
式(2)积分电路U1输出信号与原边电流采样信号ISEN K2Ip通过乘法电路U2进行实时乘法运算,t+Ton时刻运算结果为:Formula (2) The output signal of the integrating circuit U1 and the primary current sampling signal ISEN K2 Ip carry out real-time multiplication operation through the multiplication circuit U2, and the operation result at the time of t+Ton is:
K1Lm(Ipmax)*K2(Ipmax)=K1K2Lm(Ipmax)2 (3)K1 Lm(Ipmax )*K2 (Ipmax )=K1 K2 Lm(Ipmax )2 (3)
式(3)为LII电路运算结果,表征着多相交错变换器某相单位开关周期传递的能量,即该相的输出功率。Equation (3) is the operation result of the LII circuit, which represents the energy transferred per unit switching cycle of a certain phase of the multiphase interleaved converter, that is, the output power of this phase.
多相交错反激变换器各相工作于断续模式(DCM,Discontinuous ConductionMode),每个开关周期,开启时刻原边电流Ip由零开始线性增大。根据能量守恒原理,单位开关周期内变换器某相向多相交错反激变换器系统提供的能量为1/2*Lm(Ipmax)2,由于变换器各相采用相同的时钟频率,只是各相的相位不同,所以只要保证各相在单位开关周期内向多相交错反激变换器系统提供相同的能量,即可准确保证变换器各相的输出功率相等,所以保证变换器各相LII电路输出结果相等是实现变换器各相输出功率均衡的关键。Each phase of the multi-phase interleaved flyback converter works in a discontinuous conduction mode (DCM, Discontinuous Conduction Mode), and in each switching cycle, the primary current Ip increases linearly from zero at the turn-on time. According to the principle of energy conservation, the energy provided by a phase-to-phase multi-phase interleaved flyback converter system of the converter in a unit switching period is 1/2*Lm(Ipmax )2 . Since each phase of the converter adopts the same clock frequency, only each phase Therefore, as long as each phase provides the same energy to the multi-phase interleaved flyback converter system within a unit switching period, the output power of each phase of the converter can be accurately guaranteed to be equal, so the output power of each phase of the converter is guaranteed to be equal. Equality is the key to realize the balance of output power of each phase of the converter.
如图1,变换器各相采用统一的电压误差放大器U4输出信号COM作为该相的比较器U3参考电压,以保证变换器各相驱动关断信号产生时的LII电路输出结果相同,驱动关断信号与相应相的时钟信号共同产生PWM驱动脉冲,控制该相正常工作。又由于变换器各相采用相同的VIN采样系数K1和原边电流采样系数K2,所以可以准确保证单位开关周期内,变换器各相输出相同的能量1/2*Lm(Ipmax)2,即可保证变换器各相输出功率相同,实现多相交错反激变换器各相功率准确均衡控制的目的。另外,由于采用硬件乘法电路U2,延时小,再配合快速比较器U3,可实现变换器各相输出功率的逐周期控制,快速响应负载的动态变化,实现变换器各相输出功率快速准确均衡控制。As shown in Figure 1, each phase of the converter adopts the unified output signal COM of the voltage error amplifier U4 as the reference voltage of the comparator U3 of this phase, so as to ensure that the LII circuit output results are the same when the drive-off signal of each phase of the converter is generated, and the drive is turned off. The signal and the clock signal of the corresponding phase together generate a PWM drive pulse to control the normal operation of the phase. Since each phase of the converter adopts the same VIN sampling coefficient K1 and primary current sampling coefficient K2 , it can be accurately guaranteed that each phase of the converter outputs the same energy 1/2*Lm(Ipmax )2 within the unit switching period. , it can ensure that the output power of each phase of the converter is the same, and achieve the purpose of accurate balanced control of the power of each phase of the multi-phase interleaved flyback converter. In addition, due to the hardware multiplication circuit U2, the delay is small, and with the fast comparator U3, the cycle-by-cycle control of the output power of each phase of the converter can be realized, the dynamic change of the load can be quickly responded to, and the output power of each phase of the converter can be quickly and accurately balanced. control.
对于本领域技术人员而言,显然本发明不限于上述示范性实施例的细节,而且在不背离本发明的精神或基本特征的情况下,能够以其他的具体形式实现本发明。因此,无论从哪一点来看,均应将实施例看作是示范性的,而且是非限制性的,本发明的范围由所附权利要求而不是上述说明限定,因此旨在将落在权利要求的等同要件的含义和范围内的所有变化囊括在本发明内。不应将权利要求中的任何附图标记视为限制所涉及的权利要求。It will be apparent to those skilled in the art that the present invention is not limited to the details of the above-described exemplary embodiments, but that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments are to be regarded in all respects as illustrative and not restrictive, and the scope of the invention is to be defined by the appended claims rather than the foregoing description, which are therefore intended to fall within the scope of the claims. All changes within the meaning and scope of the equivalents of , are included in the present invention. Any reference signs in the claims shall not be construed as limiting the involved claim.
此外,应当理解,虽然本说明书按照实施方式加以描述,但并非每个实施方式仅包含一个独立的技术方案,说明书的这种叙述方式仅仅是为清楚起见,本领域技术人员应当将说明书作为一个整体,各实施例中的技术方案也可以经适当组合,形成本领域技术人员可以理解的其他实施方式。In addition, it should be understood that although this specification is described in terms of embodiments, not each embodiment only includes an independent technical solution, and this description in the specification is only for the sake of clarity, and those skilled in the art should take the specification as a whole , the technical solutions in each embodiment can also be appropriately combined to form other implementations that can be understood by those skilled in the art.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111556915.7ACN114430233B (en) | 2021-12-18 | 2021-12-18 | Automatic power balance control circuit of multiphase interleaved flyback converter |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111556915.7ACN114430233B (en) | 2021-12-18 | 2021-12-18 | Automatic power balance control circuit of multiphase interleaved flyback converter |
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| CN114430233Atrue CN114430233A (en) | 2022-05-03 |
| CN114430233B CN114430233B (en) | 2025-07-25 |
| Application Number | Title | Priority Date | Filing Date |
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| CN202111556915.7AActiveCN114430233B (en) | 2021-12-18 | 2021-12-18 | Automatic power balance control circuit of multiphase interleaved flyback converter |
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