Disclosure of Invention
The application aims to provide a constant voltage and constant current shared control loop, which solves the technical problems that an independent control loop is needed for the existing voltage and current modes and the control is troublesome.
In order to achieve the purpose, the application is realized by the following technical scheme:
the constant voltage constant current shared control loop comprises a first single chip microcomputer, wherein the first single chip microcomputer is sequentially connected with a resistor R9 and a resistor R10, the resistor R10 is connected with a first logic AND gate module, the first logic AND gate module is connected with a first comparator, the first comparator is sequentially connected with a second single chip microcomputer and a resistor R2, the resistor R9 is connected with a second logic AND gate module, the second logic AND gate module is connected with a second comparator, and the second comparator is sequentially connected with a third single chip microcomputer and a resistor R13.
Optionally, a resistor R1 is connected between the first comparator and the second singlechip.
Optionally, a resistor R3 is connected to the first comparator.
Optionally, a resistor R12 is connected between the second comparator and the third singlechip.
Optionally, a resistor R175 is connected to the second comparator.
Optionally, the first singlechip is connected with resistance R4, resistance R5, resistance R6, resistance R7, resistance R11 in proper order, and resistance R11 is connected with resistance R8.
The embodiment of the application has the following beneficial effects:
according to the embodiment of the application, the circuit power supply works in the current mode by sharing the same loop through the voltage and current modes, and under the condition of changing the output impedance, the output voltage is controlled by automatically adjusting the current reference through the first singlechip, so that the purpose of stabilizing the output current is finally achieved, and the control complexity is reduced.
Of course, it is not necessary for any one product to practice the application to achieve all of the advantages set forth above at the same time.
Description of the embodiments
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. The following description of at least one exemplary embodiment is merely exemplary in nature and is in no way intended to limit the application, its application, or uses.
In order to keep the following description of the embodiments of the present application clear and concise, the detailed description of known functions and known components thereof have been omitted.
Referring to fig. 1, in this embodiment, a constant voltage and constant current common control loop is provided, which includes: the first singlechip corresponds to U3 in the picture, resistance R9, resistance R10 has been connected gradually to first singlechip, resistance R9 is connected with Pin6 of first singlechip, resistance R10 is connected with Pin5 of first singlechip, resistance R10 is connected with first logic AND gate module, first logic AND gate module corresponds to U2-A in the picture, first logic AND gate module is connected with first comparator, first comparator corresponds to U1-A in the picture, first comparator has connected gradually second singlechip, resistance R2, resistance R9 is connected with second logic AND gate module, U2-B in the second logic AND gate module corresponds to the picture, second logic AND gate module is connected with the second comparator, the second comparator has connected gradually third singlechip, resistance R13, the second singlechip, the third singlechip is the master control singlechip.
The application of one aspect of the embodiment is: in the diagram, DA+ is a voltage or current reference given by a master control singlechip, VI+ is an actual output current signal voltage, the current signal voltage VI+ is compared with a reference voltage DA+ given by the master control singlechip, VI+ is smaller than DA+, a first comparator U1-A outputs a high level, a pulse voltage is output to a first singlechip Pin5 through a resistor R10 after passing through a first logic AND gate module U2-A, and the first singlechip Pin7 outputs PWM with a large duty ratio, so that the actual current reference COM_IREF is increased; VI+ is larger than DA+, the second comparator U1-B outputs high level, the pulse voltage is output to the single chip microcomputer Pin6 through the second logic AND gate module U2-B and then is output to the first single chip microcomputer Pin7 through the R9, the PWM with small duty ratio is output by the first single chip microcomputer Pin7, the actual current reference COM_IREF is reduced, COM_IREF and DA+ are controlled and switched and output by the main control single chip microcomputer through the electronic switch to serve as loop reference VREF, DA+ serves as a reference in a voltage mode, COM_IREF serves as a reference in a current mode, and therefore the voltage and the current modes can share the same loop. It should be noted that the electric equipment in the application can be powered by a storage battery or an external power supply.
The circuit power supply works in the current mode by sharing the same loop through the voltage and current modes, and under the condition of changing output impedance, the output voltage is controlled by automatically adjusting the current reference through the first singlechip, so that the purpose of stabilizing the output current is finally achieved, and the control complexity is reduced.
As shown in fig. 1, a resistor R1 is connected between the first comparator and the second singlechip in this embodiment. The first comparator is connected with a resistor R3, and the resistor R3 and the first logic AND gate module are connected with the same Pin of the first comparator.
As shown in fig. 1, a resistor R12 is connected between the second comparator and the third singlechip in this embodiment. The second comparator is connected with a resistor R175, and the resistor R175 and the second logic AND gate module are connected with the same Pin of the second comparator.
As shown in fig. 1, the first single-chip microcomputer of the embodiment is sequentially connected with a resistor R4, a resistor R5, a resistor R6, a resistor R7 and a resistor R11, the resistor R11 is connected with a resistor R8, the resistor R4 is connected with the Pin4 of the first single-chip microcomputer, the resistor R5 is connected with the Pin1 of the first single-chip microcomputer, the resistor R6 is connected with the Pin5 of the first single-chip microcomputer, the resistor R7 is connected with the Pin6 of the first single-chip microcomputer, and the resistor R11 is connected with the Pin7 of the first single-chip microcomputer.
The above embodiments may be combined with each other.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that embodiments of the application described herein may be implemented in sequences other than those illustrated or otherwise described herein.
In the description of the present application, it should be understood that the azimuth or positional relationships indicated by the azimuth terms such as "front, rear, upper, lower, left, right", "lateral, vertical, horizontal", and "top, bottom", etc., are generally based on the azimuth or positional relationships shown in the drawings, merely to facilitate description of the present application and simplify the description, and these azimuth terms do not indicate and imply that the apparatus or elements referred to must have a specific azimuth or be constructed and operated in a specific azimuth, and thus should not be construed as limiting the scope of protection of the present application; the orientation word "inner and outer" refers to inner and outer relative to the contour of the respective component itself.