CN114242661A - A low-warpage double-layer stacked ceramic system and packaging method - Google Patents
A low-warpage double-layer stacked ceramic system and packaging methodDownload PDFInfo
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- CN114242661A CN114242661ACN202111142017.7ACN202111142017ACN114242661ACN 114242661 ACN114242661 ACN 114242661ACN 202111142017 ACN202111142017 ACN 202111142017ACN 114242661 ACN114242661 ACN 114242661A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0009—Structural features, others than packages, for protecting a device against environmental influences
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0032—Packages or encapsulation
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
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Abstract
Translated fromChinese
Description
Technical Field
The invention relates to the technical field of integrated circuit packaging, in particular to a low-warpage double-layer stacked ceramic system and a packaging method.
Background
The system-in-package is a method for integrating a plurality of electronic components with different functions, including active chips, passive devices, micro-electro-mechanical systems and the like, into a package body to form a single standard package component. In order to improve the integration level, the stacking technology is an important means for realizing miniaturization, high density, high-speed interconnection, multifunctional integration and the like, but the stacking packaging technology has many defects while the system integration level is greatly increased and the system functionality is improved.
On one hand, the currently designed stacked package assembly adopts an i-shaped structure, although the packaging efficiency is high, the structure causes the ceramic material to generate large bending in the sintering process, and the production yield is difficult to control, for example, patent No. (CN112466864A) a three-dimensional stacked microwave assembly based on high-temperature co-fired ceramic.
On the other hand, the method of stacking and assembling ceramic substrates first and then packaging with a metal shell is adopted, although the assembly reliability is good, the volume of the packaged structural member is large, and the radio frequency active circuit chip which needs a cavity design is difficult to package, for example, a thin film ceramic circuit three-dimensional stacking structure of patent number (CN 107275317 a).
Disclosure of Invention
The invention aims to provide a double-layer stacked ceramic system with low warpage rate and a packaging method thereof, so as to reduce warpage and improve system integration level.
The technical solution for realizing the purpose of the invention is as follows:
a double-layer stacked ceramic system with low warpage rate comprises a top-layer packaging assembly, a bottom-layer packaging assembly and a printed board which are sequentially arranged from top to bottom; the adjacent layers are interconnected through BGA solder balls;
the top packaging assembly and the bottom packaging assembly respectively comprise a cover plate, an enclosing frame, a ceramic base and components arranged in the ceramic base;
the ceramic bases of the top packaging assembly and the bottom packaging assembly are both provided with a multilayer cavity structure;
the surrounding frame of the bottom layer is embedded into the top cavity of the corresponding ceramic base and supports the top of the ceramic base of the bottom layer; after the cover plate of the bottom layer is embedded into the surrounding frame of the bottom layer and is packaged with the ceramic base of the bottom layer, the top plane of the combination of the cover plate of the bottom layer and the surrounding frame of the bottom layer is not higher than the top of the ceramic base of the bottom layer;
the top layer of the enclosure frame is arranged at the top of the corresponding ceramic base and forms a cavity structure; the cover plate of the top layer is arranged on the top of the surrounding frame of the top layer.
A packaging method of a low warpage rate double-layer stacked ceramic system comprises the following steps:
packaging the element in the cavity of the ceramic base; the ceramic base and the surrounding frame are welded by brazing; irradiating the joint of the cover plate at the bottom and the corresponding enclosure frame by adopting laser to ensure that the edge of the cover plate at the bottom is fused with the edge of the enclosure frame to form sealing; welding the surrounding frame and the corresponding cover plate at the top by adopting parallel seal welding, generating heat through connecting contact resistors of the surrounding frame and the cover plate, melting the contact welding cover plate and the surrounding frame, and forming sealing; adopting BGA welding balls with smaller temperature gradient to weld the top of the ceramic base at the bottom layer and the bottom of the ceramic base at the top layer, avoiding the laser sealing cover plate and the surrounding frame area at the top of the ceramic base at the bottom layer, and taking other areas as welding interconnection areas; and adopting BGA welding balls with larger temperature gradient to weld the bottom of the bottom layer ceramic base and the corresponding welding pad position of the printed board.
Compared with the prior art, the invention has the following remarkable advantages:
(1) in consideration of the warping problem caused by inconsistent shrinkage rate generated in the sintering process of the ceramic material, the cavity structure with the concave structure is adopted, so that only one upward warping compensation direction is provided, the process parameters are easy to control, and further, the embedded enclosure frame is arranged in the bottom ceramic base to support the ceramic material to a certain extent, so that the low warping rate is ensured.
(2) The bottom ceramic base adopts the design of concave structure, and the great active chip of calorific capacity can be placed to the good heat conduction passageway of bottom large tracts of land ground formation, and the top layer encloses the frame unanimously with top ceramic base appearance, is the loop configuration, and the biggest planar area of utilizing pottery can hold and assemble more components and parts, improves the system integration level.
(3) And the ceramic base and the fittings are assembled by adopting a plurality of welding materials and welding methods with different temperature gradients, so that the airtight packaging of the components is realized.
Drawings
Fig. 1 is an overall exploded view of the present invention.
Fig. 2 is a schematic overall appearance of the present invention.
Fig. 3 is a cross-sectional view of a low-level ceramic submount.
Fig. 4 is a cross-sectional exploded view of a lower ceramic pedestal.
FIG. 5 is a cross-sectional view of the top ceramic susceptor.
FIG. 6 is a cross-sectional exploded view of the top ceramic susceptor.
Detailed Description
The invention is further described with reference to the following figures and embodiments.
Referring to fig. 1, the low warpage double-layer stacked ceramic system of the present embodiment includes a top-level package assembly a1, a bottom-level package assembly a3, and a printed board a5, which are sequentially disposed from top to bottom; the top packaging component a1 and the bottom packaging component a3 are connected through an interlayer BGA solder ball a 2; the bottom packaging component a3 is connected with a printed board a5 through bottom BGA solder balls a 4;
the bottom packaging assembly a3 comprises a bottom cover plate b1, a bottom surrounding frame b2, a bottom ceramic base b3, a bottom chip and a slide b 4; the bottom ceramic base b3 is made of high-temperature co-fired ceramic material; the bottom layer surrounding frame b2 and the bottom layer cover plate b1 are made of kovar metal materials, the bottom of the bottom layer surrounding frame b2 is brazed inside a cavity of the bottom layer ceramic base b3 through welding materials, a step structure is arranged at the upper end of the bottom layer surrounding frame b2, the bottom layer cover plate b1 is installed in the step structure of the bottom layer surrounding frame, and the upper surface of the bottom layer cover plate b1 is flush with the top of the bottom layer surrounding frame b 2. The top plane of the combination of the bottom layer surrounding frame b2 and the bottom layer cover plate b1 is not higher than the top of the bottom layer ceramic base b 3. The cavity structure of the bottom ceramic base b3 does not exceed three nested cavities at most, and the bottom enclosure frame b2 is embedded in the cavity of the highest layer of the bottom ceramic base b 3; the bottom chip and slide b4 are disposed in the lowest cavity,
the top packaging assembly a1 is composed of a top cover plate c1, a top frame c2, a top ceramic base c3, a top chip and a carrier c 4. The top ceramic base c3 is made of high-temperature co-fired ceramic material; the top layer surrounding frame c2 and the top layer cover plate c1 are made of kovar metal materials. The top surrounding frame c2 is in a ring structure, which is consistent with the shape of the top ceramic base c3, the bottom of the top surrounding frame c2 is welded around the top of the top ceramic base c3 by solder, a cavity structure is formed on the top ceramic base c3, and the top cover plate c1 covers the top of the top surrounding frame c 2. The top peripheral frame c2 is in a ring structure, which is identical to the top ceramic base c3 in shape, the bottom of the top peripheral frame c2 is brazed around the top of the bottom ceramic base c3 by using solder, a cavity structure is formed on the top ceramic base c3, and the cover plate c1 covers the top of the top peripheral frame c 2.
The structure of bottom ceramic base b3, top ceramic base c3 all adopt concave type structure, and cavity structure is no longer than three-layer nested cavity at most, and the thickness to ceramic base bottom is not less than 1mm in the cavity of lowest floor, and cavity plane dimension is no longer than 80% of ceramic base plane dimension, and ceramic base's peripheral size is no longer than 25mm, and the purpose of design restraint is in order to guarantee that ceramic base's warped height is no longer than 0.5% of ceramic base longest diagonal, and the biggest warpage of basic ceramic is no longer than 0.175 mm.
The packaging method of the low warpage double-layer stacked ceramic comprises the following steps:
step 1, manufacturing a ceramic base: the bottom ceramic base b3 and the top ceramic base c3 are used as packaging main bodies, raw ceramic chips are manufactured respectively based on a designed structure and circuit graphs, a high-temperature-resistant tungsten slurry printed circuit is adopted, size compensation processing is carried out on the raw ceramic chips according to the ceramic base structure, each layer of raw ceramic chips are aligned and laminated, an internal cavity is formed after pressing, the ceramic main bodies are sintered at high temperature, and the ceramic main bodies can be heated again to carry out flatness adjustment after sintering. The bottom ceramic base b3 and the top ceramic base c3 are of concave structures, the cavity structure is not more than three layers of nested cavities at most, the thickness from the inside of the cavity at the lowest layer to the bottom of the ceramic base is not less than 1mm, the plane size of the cavity is not more than 80% of the plane size of the ceramic base, the peripheral size of the ceramic base is not more than 25mm multiplied by 25mm, the design constraint aims to ensure that the warping height of the ceramic base is not more than 0.5% of the longest diagonal line of the ceramic base, and the maximum warping degree is not more than 0.175 mm.
Step 2, welding the top layer surrounding frame c2 or the bottom layer surrounding frame b2 with the corresponding ceramic base:
electroplating a layer of metal nickel on the tungsten layer on the surface of the ceramic base. Welding the metal enclosure frame and the ceramic base by using high-temperature brazing solder, wherein the welding temperature is 500-800 ℃, welding nickel electroplated on the surface with the metal enclosure frame, and the enclosure frame is mainly made of kovar alloy materials and plated with gold on the surface. The ceramic base plating material is not limited to metallic nickel, and other metals or alloys may be used, including but not limited to various alloys of gold, silver, copper, tungsten, nickel, etc.
Step 3, assembling components inside the ceramic base cavity:
the chip carrier plate can be made of molybdenum-copper material with expansion coefficient close to that of ceramic, the chip can be assembled on the carrier plate by eutectic welding, the carrier plate is adhered to the inside of the ceramic cavity by conductive adhesive, the chip and the internal circuit of the ceramic base are connected by gold wire bonding after the conductive adhesive is cured at high temperature, and the assembly temperature in the assembly process is not more than 280 ℃.
And 4, sealing the lower-layer assembly and the top-layer assembly: assembling the corresponding cover plate and the surrounding frame:
the sealing of the low-layer assembly a3 is realized by irradiating high-energy laser on the joint of the bottom cover plate b1 and the bottom surrounding frame b2, so that the edge of the bottom cover plate b1 is fused with the edge of the bottom surrounding frame b2 to form the sealing. The top plane of the combination of the bottom layer surrounding frame b2 and the bottom layer cover plate b1 is 0.5mm lower than the top of the bottom layer ceramic base b3, and the stacking welding is not influenced by the protrusion. High-energy laser is adopted to irradiate the joint of the bottom cover plate and the bottom surrounding frame, so that the edge of the cover plate is fused with the edge of the surrounding frame, a gap between the sealed bottom cover plate b1 and the edge of the bottom surrounding frame b2 is not more than 0.1mm, and the laser melting depth is not more than 0.5 mm.
The sealing of the top layer assembly a1 adopts parallel seal welding to weld the top layer surrounding frame c2 and the top layer cover plate c1, and adopts parallel seal welding to weld the surrounding frame and the cover plate, namely, high pressure is connected at the joint, high heat is generated through the connecting contact resistance of the surrounding frame and the cover plate, and the cover plate and the surrounding frame are welded by melting contacts to form sealing. The method comprises connecting high voltage at the joint, connecting the positive and negative electrodes of the power supply with two rollers with oblique angles on the side surfaces, contacting the roller with the cover plate twice, generating high heat instantly by the contact resistance of the connecting contact, melting the contact, and welding the cover plate and the enclosure frame to form a seal.
Step 5, stacking and welding the double-layer assembly:
and carrying out interlayer BGA solder ball a2 ball implantation on a pad at the bottom of the top layer assembly, fixing the top layer assembly and the bottom layer assembly module by using a clamp after the ball implantation is finished, aligning the BGA solder ball a2 and the pad to be welded, putting the clamp and the assembly into a reflow soldering furnace, melting the BGA solder ball a2 and connecting and welding the top layer assembly a1 and the bottom layer assembly a3 by heating the reflow soldering furnace, completing the welding, and forming a double-layer stacking microsystem. The process is repeated to solder the bottom layer BGA solder ball a4, so that the soldering of the double-layer stacked microsystem and the printed board a5 is completed, and the whole assembly is completed. And welding the top of the bottom ceramic base and the bottom of the layer ceramic base by using high-temperature BGA welding balls, avoiding the laser sealing cover plate and the surrounding frame region at the top of the bottom ceramic base, and taking other regions as welding interconnection regions. The bottom of the underlying ceramic base and the printed board to pad locations are soldered with low temperature BGA solder balls. The interlayer BGA solder ball a2 and the bottom layer BGA solder ball a4 can adopt BGA solder balls with different compositions to form a temperature gradient, firstly the solder balls with the temperature gradient of 180 ℃ are adopted for interlayer welding, and then the solder balls with the temperature gradient of 150 ℃ are adopted for welding on the bottom layer printed board, wherein the composition of the BGA solder balls comprises but is not limited to one or more alloys of gold, tin, lead, silver and bismuth materials.
Claims (10)
Translated fromChinesePriority Applications (1)
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114823558A (en)* | 2022-04-26 | 2022-07-29 | 四川九洲电器集团有限责任公司 | Package body and package-on-package method for stacking multiple layers of substrates of silicon-based chip |
| CN115469275A (en)* | 2022-08-31 | 2022-12-13 | 航天科工微电子系统研究院有限公司 | A SiP design method for Ku/Ka dual-band TR components |
| CN115602636A (en)* | 2022-11-02 | 2023-01-13 | 中国电子科技集团公司第二十九研究所（Cn） | A three-dimensional hermetic packaging structure and packaging method |
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| CN115602636A (en)* | 2022-11-02 | 2023-01-13 | 中国电子科技集团公司第二十九研究所（Cn） | A three-dimensional hermetic packaging structure and packaging method |
| CN115602636B (en)* | 2022-11-02 | 2025-09-19 | 中国电子科技集团公司第二十九研究所 | Three-dimensional airtight packaging structure and packaging method |
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