CN114242143A - Writing method of flash memory - Google Patents

Abstract

The invention provides a writing method of a flash memory, which is characterized in that when the memory is written, a first voltage is applied to a selected bit line, a second voltage is applied to a non-selected bit line, the first voltage is a negative voltage, the second voltage is a positive voltage, and the difference value between the first voltage and the second voltage is 4.6-4.7V.

Description

Writing method of flash memory

Technical Field

The present invention relates to the field of semiconductor technologies, and in particular, to a writing method for a flash memory.

Background

A flash memory is a nonvolatile memory having a data memorizing function. The flash memory may be read and written in units of pages. Flash memories have a large storage capacity, and thus are widely used in various electronic devices. However, in the application process of the flash memory, it is found that after some data are written into the memory cells and read for many times, the flash memory has a problem of write disturbance, and therefore a new method for writing the flash memory is needed.

Disclosure of Invention

The invention aims to provide a writing method of a flash memory, which aims to solve the problem of writing interference of the flash memory.

In order to solve the above technical problem, the present invention provides a writing method of a flash memory, where the flash memory includes at least two sectors, a plurality of bit lines and a plurality of source lines, each of the sectors includes a plurality of memory cells, the memory cells are arranged in a rectangular array, the memory cells in the same column are connected to the same bit line, and the memory cells in the same row are connected to the same source line, the writing method of the flash memory includes: selecting at least one memory cell on the same bit line from the plurality of memory cells to write; applying a first voltage on the selected bit line and a second voltage on the unselected bit line to write to the selected memory cell; wherein the difference between the first voltage and the second voltage is 4.6V-4.7V.

Optionally, in the writing method of the flash memory, the first voltage is (V)_CC-5.3) V, the second voltage being (V)_CC-V_t) V, wherein V_CC=1V~2V，V_t=0.7V~0.8V。

Optionally, in the writing method of the flash memory, each memory cell includes a control transistor and a selection transistor; the control transistor comprises a floating gate, a control gate and a source electrode, the floating gate is formed on the substrate, the control gate covers the floating gate, and the source electrode is formed in the substrate on one side, far away from the selection transistor, of the control gate; the selection transistor comprises a dummy gate, a selection gate and a drain electrode, the dummy gate is formed on the substrate, the selection gate covers the dummy gate, and the drain electrode is formed in the substrate on one side of the selection gate away from the control transistor; and an active drain junction is formed in the substrate between the selection gate and the control gate.

Optionally, in the writing method of the flash memory, the control gates of the control transistors in the same row are connected together, and the selection gates of the selection transistors in the same row are connected together.

Optionally, in the writing method of the flash memory, the sources of the control transistors in the same row are connected to the same source line, and the drains of the selection transistors in the same column are connected to the same bit line.

Optionally, in the writing method of the flash memory, the writing method of the flash memory further includes: when writing the selected memory cell, applying a third voltage to the selection gate of the selected memory cell, applying the second voltage to the selection gates of the non-selected memory cells which are positioned in the same sector and in different rows with the selected memory cell, and applying the second voltage to the selection gates of the non-selected memory cells which are positioned in different sectors with the selected memory cell, wherein the third voltage is (V)_CC-7.3）V。

Optionally, in the writing method of the flash memory, the writing method of the flash memory further includes: when writing the selected memory cell, applying a fourth voltage on the control gate of the selected memory cell, applying the fourth voltage on the control gates of the unselected memory cells in the same sector with the selected memory cell, and applying the second voltage on the control gates of all the memory cells in different sectors with the selected memory cell, wherein the fourth voltage is (V)_CC+8.8）V。

Optionally, in the writing method of the flash memory, when writing is performed on the selected memory cell, the second voltage is further applied to the source line of the selected memory cell and the source line located in the same sector as the selected memory cell, and the second voltage is applied to the source line located in a different sector from the selected memory cell.

Optionally, in the writing method of the flash memory, a shallow trench isolation structure is formed in a substrate between the control transistor and the selection transistor, and a doped region is formed in the substrate at the bottom of the shallow trench isolation structure.

Optionally, in the writing method of the flash memory, the doping ions in the doping region are boron ions or gallium ions.

In the writing method of the flash memory provided by the invention, when the memory is written, a first voltage is applied to a selected bit line, a second voltage is applied to a non-selected bit line, the first voltage is a negative voltage, the second voltage is a positive voltage, and the difference value between the first voltage and the second voltage is 4.6-4.7V.

Drawings

Fig. 1 is a flow chart illustrating a writing method of a flash memory according to an embodiment of the invention.

Fig. 2 is a schematic structural diagram of a flash memory according to an embodiment of the invention.

Fig. 3 is a schematic cross-sectional view of a select transistor according to an embodiment of the invention.

Fig. 4 is a circuit diagram of a memory cell of a flash memory according to an embodiment of the present invention.

100-a substrate; 101-a storage unit; 101-a well region; 102-shallow trench isolation structures; 103-doped region; 110-a control transistor; 111-floating gate; 112-a control gate; 113-a source; 114-source drain junction; 115-first oxide layer; 116-a first inter-gate dielectric layer; 120-select transistor; 121-dummy gate; 122-select gate; 123-drain electrode; 124-a second oxide layer; 125-a second inter-gate dielectric layer; CG1, CG2, CG3, CG 4-first control line; SG1, SG2, SG3, SG4 — second control line; BL1, BL2, BL 3-bit lines; SL1, SL 2-source line.

Detailed Description

The following describes the writing method of the flash memory according to the present invention in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Fig. 1 is a flow chart illustrating a writing method of a flash memory according to an embodiment of the invention. Fig. 2 is a schematic structural diagram of a flash memory according to an embodiment of the invention. FIG. 3 is a schematic cross-sectional view of a select transistor of an embodiment of the present invention; fig. 4 is a circuit diagram of a memory cell of a flash memory according to an embodiment of the present invention. Here, fig. 2 is a schematic cross-sectional view along a first direction of the flash memory, and fig. 3 is a schematic cross-sectional view along a second direction of the flash memory, the first direction being perpendicular to the second direction. As shown in fig. 2 and 4, the flash memory includes at least two sectors, a plurality of source lines SL1, SL2, and a plurality of bit lines BL1, BL2, BL 3. In this embodiment, the flash memory includes two sectors, namely, a sector I and a sector II, each of the sectors includes a plurality ofmemory cells 101, and the plurality ofmemory cells 101 are arranged in a rectangular array.

As shown in fig. 4, thememory cells 101 in the same sector I may be connected to the same source line SL1, and thememory cells 101 in the same column are connected to the same bit line BL 1. For simplicity, fig. 4 shows only the case where three bit lines (BL1, BL2, BL3) and two source lines (SL1, GSL2) are included. However, it can be understood by those skilled in the art that in practical applications, the number of the bit lines and the source lines can be set according to needs, and is not limited thereto.

In the present embodiment, as shown in fig. 2, eachmemory cell 101 includes acontrol transistor 110 and aselection transistor 120, and thecontrol transistor 110 and theselection transistor 120 may be PMOS transistors. The operation of the selected fixedaddress memory cell 101 can be selected or deselected by theselect transistor 120. Thecontrol transistor 110 is used to store "0/1". Thecontrol transistor 110 is caused to exhibit different electrical characteristics (e.g., different threshold voltages) by a specific operation, thereby representing either a "0" or a "1". In eachmemory cell 101, theselect transistor 120 and thecontrol transistor 110 are connected in series, thereby forming amemory cell 101 for storing data.

Specifically, as shown in fig. 2, thecontrol transistor 110 includes afloating gate 111, acontrol gate 112 and asource 113, thefloating gate 111 is formed on thesubstrate 100, thecontrol gate 112 covers thefloating gate 111, and thesource 113 is formed in thesubstrate 100 on a side of thecontrol gate 112 away from theselect transistor 120. Thefloating gate 111 is used for storing electrons, and the thickness thereof may be, for example, 100 to 200 angstroms. Thefloating gate 111 and thecontrol gate 112 are made of doped polysilicon, a through opening is formed in thefloating gate 111, thecontrol gate 112 is filled in the opening and extends to cover thefloating gate 111, and a first inter-gate dielectric layer (e.g., an ONO layer) 116 for isolation is formed between thefloating gate 111 and thecontrol gate 112. Further, afirst oxide layer 114 is formed between thefloating gate 111 and thesubstrate 100, and thefirst oxide layer 114 is used for isolating thesubstrate 100 from thefloating gate 111. Further, asource drain junction 114 is formed in thesubstrate 100 between theselect gate 122 and thecontrol gate 112.

As shown in fig. 4, thecontrol gates 112 of thecontrol transistors 110 in the same row are connected together, for example, by first control lines SG1, SG2, SG3, SG 4. Thesources 113 of thecontrol transistors 110 in the same row are connected to the same source lines SL1, SL 2.

As shown in fig. 2 and 3, theselect transistor 120 includes adummy gate 121, aselect gate 122, and adrain 123, thedummy gate 121 is formed on thesubstrate 100, and thedummy gate 121 may be formed in the same process step as thefloating gate 111 to save processes.

As shown in fig. 3, theselect gate 122 covers thedummy gate 121, and thedrain 123 is formed in thesubstrate 100 at a side of theselect gate 122 away from thecontrol transistor 110. Asecond oxide layer 124 is further formed between theselect gate 122 and thesubstrate 100, thesecond oxide layer 124 is used for isolating thesubstrate 100 from thedummy gate 121, and thesecond oxide layer 124 and thefirst oxide layer 115 can be formed in the same process.

In this embodiment, as shown in fig. 3, thedummy gate 121 has a through groove therein, and theselect gate 122 fills the through groove and extends to cover thedummy gate 121. A second inter-gatedielectric layer 125 is formed on the sidewall and the bottom of the groove, the second inter-gatedielectric layer 125 and the first inter-gatedielectric layer 116 may be formed in the same process, and both the first inter-gatedielectric layer 116 and the second inter-gatedielectric layer 125 may be a stacked structure of a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer.

In this embodiment, theselect gate 122 is made of doped polysilicon. Theselect gate 122 may be formed in the same process as thecontrol gate 112 to save process steps.

In this embodiment, as shown in fig. 2 and 4, theselect gates 122 of theselect transistors 120 in the same row are connected together, for example, through second control lines SG1, SG2, SG3 and SG 4. Thedrains 123 of theselect transistors 120 in the same column are connected to the same bit lines BL1, BL2, BL 3.

In addition, as shown in fig. 2 and fig. 3, awell region 101 is formed in thesubstrate 100, thewell region 101 is an N-type well region (N-well), and thesource 113, the source-drain junction 124, and thedrain 123 are all formed in thewell region 101.

In this embodiment, as shown in fig. 3, the flash memory further includes a shallowtrench isolation structure 102 formed in asubstrate 100, the shallowtrench isolation structure 102 is located in thesubstrate 100 at the bottom of theselect gate 122, the shallowtrench isolation structure 102 is aligned with a groove in thedummy gate 121, and adoped region 103 is formed in thesubstrate 100 at the bottom of the shallowtrench isolation structure 102. The doped ions in thedoped region 103 are boron ions, gallium ions or other P-type ions, the implantation energy range is 25 KeV-38 KeV, and the ion concentration range is 20 × 10¹²/cm²～60×10¹²/cm². Thedoped region 103 may protect theselect transistor 120 from write crosstalk failure due to leakage current entering the device, thereby further reducing or avoiding interference during the write process. Further, the dopedregion 103 may be formed in the same step as the threshold voltage modification region of the select transistor 120 (located in thewell region 101 and near the conductive channel of theselect transistor 120 or overlapping the conductive channel) to save mask.

As shown in fig. 1, the writing method of the flash memory includes: step S1: selecting at least one memory cell on the same bit line from the plurality of memory cells to write; step S2: applying a first voltage on the selected bit line and a second voltage on the unselected bit line to write to the selected memory cell; the first voltage is a negative voltage, the second voltage is a positive voltage, and the difference between the first voltage and the second voltage is 4.6-4.7V.

In this embodiment, when writing to the memory, a first voltage is applied to the selected bit line, and a second voltage is applied to the unselected bit line, where the first voltage is a negative voltage, the second voltage is a positive voltage, and a difference between the first voltage and the second voltage is 4.6V to 4.7V, so that a voltage difference between the selected bit line and the unselected bit line can be reduced during the writing process, and interference during the writing process can be reduced or avoided.

The writing method of the flash memory provided by the present embodiment will be described in more detail below.

As shown in fig. 4, in step S1, at least one memory cell on the same bit line is selected from the plurality of memory cells and written. Here, onememory cell 101 on selected bit line BL1 is taken as an example. In other embodiments, two, three, or four memory cells, etc. on bit line BL1 may be selected, e.g., may be written to by peripheral circuitry selectingmemory cell 101. The peripheral circuits include a row decoder, a column decoder, and the like, and are conventional and will not be described herein.

In step S2, a first voltage is applied to the selected bit line BL1, and a second voltage is applied to the unselected bit lines BL2 and BL3, so as to write to the selected memory cell; the first voltage is a negative voltage, the second voltage is a positive voltage, and the difference between the first voltage and the second voltage is 4.6-4.7V. When the memory is written, a first voltage is applied to a selected bit line, a second voltage is applied to a non-selected bit line, the first voltage is a negative voltage, the second voltage is a positive voltage, and the difference value between the first voltage and the second voltage is 4.6-4.7VDisturbances in the writing process are reduced or avoided. Specifically, the first voltage is (V)_CC-5.3) V, the second voltage being (V)_CC-V_t) V, wherein V_CCRepresents a power supply voltage and V_CC=1V~2V，V_t=0.7V~0.8V。

In addition, when writing to the selectedmemory cell 101, a third voltage is applied to the select gate of the selected memory cell, and the second voltage is applied to the select gates of the non-selected memory cells located in the same sector and in a different row from the selected memory cell, and the second voltage is applied to the select gates of the non-selected memory cells located in a different sector from the selected memory cell. And applying a fourth voltage to the control gates of the selected memory cells, applying the fourth voltage to the control gates of the unselected memory cells in the same sector as the selected memory cell, and applying the second voltage to the control gates of all the memory cells in a different sector from the selected memory cell, wherein the third voltage is (V)_CC-7.3) V, the fourth voltage being (V)_CC+ 8.8) V to effect a write tomemory cell 101 on the selected bit line.

In this embodiment, when writing to a selected memory cell, the second voltage is also applied to the selected memory cell and the source line SL1 located in the same sector as the selected memory cell, and the second voltage is also applied to the source line located in a different sector from the selected memory cell.

In addition, the writing method of the flash memory of the embodiment is used for a 55nm embedded flash memory.

In summary, in the writing method of the flash memory provided by the invention, when the memory is written, the first voltage is applied to the selected bit line, and the second voltage is applied to the unselected bit line, the first voltage is a negative voltage, the second voltage is a positive voltage, and the difference between the first voltage and the second voltage is 4.6V-4.7V.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims (10)

Translated fromChinese

1.一种闪存存储器的写入方法，所述闪存存储器包括至少两个扇区、多条位线以及多条源线，每个所述扇区包括多个存储单元，所述多个存储单元呈矩形阵列式排布，位于同一列的存储单元连接至同一条位线，位于同一行的存储单元连接至同一条源线，其特征在于，所述闪存存储器的写入方法包括：1. A method for writing a flash memory, the flash memory comprising at least two sectors, a plurality of bit lines and a plurality of source lines, each of the sectors comprising a plurality of storage units, the plurality of storage units Arranged in a rectangular array, the memory cells located in the same column are connected to the same bit line, and the memory cells located in the same row are connected to the same source line, characterized in that the writing method of the flash memory includes:从所述多个存储单元中选择同一条位线上的至少一个存储单元进行写入；Selecting at least one memory cell on the same bit line from the plurality of memory cells for writing;在选中的所述位线上施加第一电压，以及在非选中的位线上施加第二电压，以对选中的所述存储单元进行写入；其中，所述第一电压为负电压，所述第二电压为正电压，且所述第一电压与所述第二电压之间的差值为4.6V~4.7V。A first voltage is applied on the selected bit lines, and a second voltage is applied on the unselected bit lines to write the selected memory cells; wherein, the first voltage is a negative voltage, so The second voltage is a positive voltage, and the difference between the first voltage and the second voltage is 4.6V˜4.7V.2.如权利要求1所述的闪存存储器的写入方法，其特征在于，所述第一电压为（V_CC-5.3）V，所述第二电压为（V_CC-V_t）V，其中，V_CC=1V~2V，V_t=0.7V~0.8V。2 . The method for writing a flash memory according to claim 1 , wherein the first voltage is (V_CC -5.3)V, and the second voltage is (V_CC -V_t )V, wherein , V_CC =1V~2V, V_t =0.7V~0.8V.3.如权利要求1所述的闪存存储器的写入方法，其特征在于，每个所述存储单元包括控制晶体管和选择晶体管；3. The method for writing a flash memory according to claim 1, wherein each of the storage cells comprises a control transistor and a selection transistor;所述控制晶体管包括浮栅、控制栅以及源极，所述浮栅形成于衬底上，所述控制栅覆盖所述浮栅，所述源极形成于所述控制栅远离所述选择晶体管一侧的衬底内；The control transistor includes a floating gate, a control gate, and a source, the floating gate is formed on the substrate, the control gate covers the floating gate, and the source is formed at a distance from the control gate to the selection transistor. inside the substrate on the side;所述选择晶体管包括伪栅、选择栅和漏极，所述伪栅形成于所述衬底上，所述选择栅覆盖所述伪栅，所述漏极形成于所述选择栅远离所述控制晶体管一侧的衬底内；The select transistor includes a dummy gate formed on the substrate, a select gate overlying the dummy gate, and a drain formed on the select gate away from the control Inside the substrate on one side of the transistor;其中，所述选择栅和所述控制栅之间的衬底内形成有源漏结。Wherein, a source-drain junction is formed in the substrate between the selection gate and the control gate.4.如权利要求3所述的闪存存储器的写入方法，其特征在于，位于同一行的所述控制晶体管的控制栅连接在一起，以及位于同一行的所述选择晶体管的选择栅连接在一起。4. The method for writing a flash memory according to claim 3, wherein the control gates of the control transistors located in the same row are connected together, and the selection gates of the selection transistors located in the same row are connected together .5.如权利要求3所述的闪存存储器的写入方法，其特征在于，位于同一行的所述控制晶体管的源极连接至同一条所述源线，以及位于同一列的所述选择晶体管的漏极连接至同一条所述位线。5 . The writing method of the flash memory according to claim 3 , wherein the source electrodes of the control transistors located in the same row are connected to the same source line, and the source electrodes of the selection transistors located in the same column are connected to the same source line. 6 . The drain is connected to the same bit line.6.如权利要求3所述的闪存存储器的写入方法，其特征在于，所述闪存存储器的写入方法还包括：6. The writing method of the flash memory according to claim 3, wherein the writing method of the flash memory further comprises:在对选中的所述存储单元进行写入时，在选中的存储单元的选择栅上施加第三电压，以及在与选中的存储单元位于同一扇区且不同行的非选中的存储单元的选择栅上施加所述第二电压，以及在与选中的存储单元位于不同扇区的非选中的存储单元的选择栅上施加所述第二电压，其中，所述第三电压为（V_CC-7.3）V。When writing the selected memory cells, a third voltage is applied to the select gates of the selected memory cells, and the select gates of unselected memory cells located in the same sector and different rows as the selected memory cells are applied with a third voltage and applying the second voltage on the select gates of unselected memory cells located in different sectors from the selected memory cells, wherein the third voltage is (V_CC -7.3) V.7.如权利要求3所述的闪存存储器的写入方法，其特征在于，所述闪存存储器的写入方法还包括：7. The writing method of the flash memory according to claim 3, wherein the writing method of the flash memory further comprises:在对选中的所述存储单元进行写入时，还在选中的存储单元的控制栅上施加第四电压，并且在与选中的存储单元位于同一扇区的非选中的存储单元的控制栅上施加所述第四电压，以及在与选中的存储单元位于不同扇区的所有存储单元的控制栅上施加所述第二电压，其中，所述第四电压为（V_CC+8.8）V。When writing to the selected memory cells, a fourth voltage is also applied to the control gates of the selected memory cells, and applied to the control gates of unselected memory cells located in the same sector as the selected memory cells the fourth voltage, and applying the second voltage on the control gates of all memory cells located in different sectors from the selected memory cell, wherein the fourth voltage is (V_CC +8.8)V.8.如权利要求1所述的闪存存储器的写入方法，其特征在于，在对选中的存储单元进行写入时，还在选中的存储单元的源线以及与选中的存储单元位于同一扇区的源线上施加所述第二电压，以及在与选中的存储单元位于不同扇区的源线上施加所述第二电压。8. The method for writing a flash memory according to claim 1, wherein when writing to the selected storage unit, the source line of the selected storage unit and the selected storage unit are located in the same sector The second voltage is applied on the source line of the memory cell, and the second voltage is applied on the source line in a different sector from the selected memory cell.9.如权利要求2所述的闪存存储器的写入方法，其特征在于，所述闪存存储器还包括形成于所述衬底中的浅沟槽隔离结构，所述浅沟槽隔离结构位于所述选择栅底部的所述衬底中，并且所述浅沟槽隔离结构底部的所述衬底中形成有掺杂区。9 . The method for writing a flash memory according to claim 2 , wherein the flash memory further comprises a shallow trench isolation structure formed in the substrate, the shallow trench isolation structure located in the A doped region is formed in the substrate at the bottom of the select gate, and in the substrate at the bottom of the shallow trench isolation structure.10.如权利要求9所述的闪存存储器的写入方法，其特征在于，所述掺杂区中的掺杂离子为硼离子或者镓离子。10 . The method for writing a flash memory according to claim 9 , wherein the doping ions in the doping region are boron ions or gallium ions. 11 .

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