CN114220765B - Memory and method of making the same - Google Patents

Abstract

Translated fromChinese

本申请提供一种存储器及其制造方法，所述制造方法包括：提供衬底；在所述衬底中形成沿第一方向延伸的若干相互平行的第一隔离结构；所述第一方向平行于所述衬底表面；所述第一隔离结构的第一厚度小于所述衬底的厚度；在所述衬底中形成沿第二方向延伸的若干相互平行的第一沟槽；所述第二方向平行于所述衬底表面且与所述第一方向垂直；所述第一沟槽与所述第一隔离结构将所述衬底划分为多个沟道柱；在所述第一沟槽内形成字线结构和第二隔离结构；其中，所述字线结构和所述第二隔离结构并列排布，且沿所述第一沟槽的侧壁延伸；在所述字线结构相邻的所述沟道柱的表面形成存储结构。

The present application provides a memory and a method for manufacturing the same. The manufacturing method includes: providing a substrate; forming a plurality of mutually parallel first isolation structures extending along a first direction in the substrate; the first direction is parallel to the surface of the substrate; the first thickness of the first isolation structure is smaller than the thickness of the substrate; a plurality of mutually parallel first trenches extending along a second direction are formed in the substrate; the second the direction is parallel to the surface of the substrate and perpendicular to the first direction; the first trench and the first isolation structure divide the substrate into a plurality of channel pillars; in the first trench A word line structure and a second isolation structure are formed inside; wherein, the word line structure and the second isolation structure are arranged side by side and extend along the sidewall of the first trench; adjacent to the word line structure The surface of the channel pillar forms a storage structure.

Description

Translated fromChinese

存储器及其制造方法Memory and method of making the same

技术领域technical field

本申请涉及半导体技术领域，具体是涉及一种存储器及其制造方法。The present application relates to the field of semiconductor technology, and in particular, to a memory and a method for manufacturing the same.

背景技术Background technique

随着当今科学技术的不断发展，存储器被广泛地应用于各种电子设备。随机存取存储器（Random Access Memory，RAM）是一种易失性存储器，是计算机中常用的半导体存储器件。With the continuous development of today's science and technology, memory is widely used in various electronic devices. Random access memory (Random Access Memory, RAM) is a kind of volatile memory, which is a semiconductor storage device commonly used in computers.

随机存取存储器由多个重复的存储单元组成，每一个存储单元主要由一个晶体管与一个由晶体管所操控的电容所构成，且每一个存储单元通过字线与位线彼此电连接。然而，这种随机存取存储器存在存储单元占用面积较大、布线复杂，制造工艺难度大等问题。The random access memory is composed of a plurality of repeated memory cells, each memory cell is mainly composed of a transistor and a capacitor controlled by the transistor, and each memory cell is electrically connected to each other through word lines and bit lines. However, such a random access memory has problems such as a large storage area occupied by a storage unit, complicated wiring, and a difficult manufacturing process.

发明内容SUMMARY OF THE INVENTION

有鉴于此，本申请实施例提供了一种存储器及其制造方法。In view of this, embodiments of the present application provide a memory and a method for manufacturing the same.

第一方面，本申请实施例提供了一种存储器的制造方法，所述方法包括：In a first aspect, an embodiment of the present application provides a method for manufacturing a memory, the method comprising:

提供衬底；provide a substrate;

在所述衬底中形成沿第一方向延伸的若干相互平行的第一隔离结构；所述第一方向平行于所述衬底表面；所述第一隔离结构的第一厚度小于所述衬底的厚度；A plurality of mutually parallel first isolation structures extending along a first direction are formed in the substrate; the first direction is parallel to the surface of the substrate; the first thickness of the first isolation structures is smaller than that of the substrate thickness of;

在所述衬底中形成沿第二方向延伸的若干相互平行的第一沟槽；所述第二方向平行于所述衬底表面且与所述第一方向垂直；所述第一沟槽与所述第一隔离结构将所述衬底划分为多个沟道柱；A plurality of mutually parallel first trenches extending along a second direction are formed in the substrate; the second direction is parallel to the surface of the substrate and perpendicular to the first direction; the first trench and the first isolation structure divides the substrate into a plurality of channel pillars;

在所述第一沟槽内形成字线结构和第二隔离结构；其中，所述字线结构和所述第二隔离结构并列排布，且沿所述第一沟槽的侧壁延伸；A word line structure and a second isolation structure are formed in the first trench; wherein, the word line structure and the second isolation structure are arranged side by side and extend along the sidewall of the first trench;

在所述字线结构相邻的所述沟道柱的表面形成存储结构。A storage structure is formed on the surface of the channel pillar adjacent to the word line structure.

在一些实施例中，所述方法还包括：In some embodiments, the method further includes:

在所述第一沟槽底部形成第二厚度的第三隔离结构；所述第二厚度小于所述第一沟槽的深度；所述字线结构和所述第二隔离结构形成于所述第三隔离结构上方。A third isolation structure with a second thickness is formed at the bottom of the first trench; the second thickness is smaller than the depth of the first trench; the word line structure and the second isolation structure are formed on the first trench Above the three isolation structures.

在一些实施例中，所述方法还包括：In some embodiments, the method further includes:

形成覆盖所述第一沟槽内壁的第一氧化层；forming a first oxide layer covering the inner wall of the first trench;

形成覆盖所述第一氧化层的第一保护层；forming a first protective layer covering the first oxide layer;

所述在所述第一沟槽底部形成第二厚度的第三隔离结构，包括：The forming a third isolation structure with a second thickness at the bottom of the first trench includes:

在内壁覆盖有所述第一氧化层和所述第一保护层的所述第一沟槽内，形成所述第三隔离结构。The third isolation structure is formed in the first trench whose inner wall is covered with the first oxide layer and the first protective layer.

在一些实施例中，所述在内壁覆盖有所述第一氧化层和所述第一保护层的所述第一沟槽内，形成所述第三隔离结构，包括：In some embodiments, forming the third isolation structure in the first trench whose inner wall is covered with the first oxide layer and the first protective layer includes:

在内壁覆盖有所述第一氧化层和所述第一保护层的所述第一沟槽内，填充绝缘材料；Filling insulating material in the first trench whose inner wall is covered with the first oxide layer and the first protective layer;

去除至少部分所述绝缘材料，使所述第一沟槽底部保留所述第二厚度的所述绝缘材料以形成所述第三隔离结构；removing at least part of the insulating material so that the second thickness of the insulating material remains at the bottom of the first trench to form the third isolation structure;

去除所述第三隔离结构上方的所述第一保护层。The first protective layer over the third isolation structure is removed.

在一些实施例中，所述在所述第一沟槽内形成字线结构和第二隔离结构，包括：In some embodiments, forming a word line structure and a second isolation structure in the first trench includes:

在所述第三隔离结构上方，形成覆盖所述第一沟槽的第一侧壁的第一牺牲层，并形成覆盖所述第一沟槽的第二侧壁的第二牺牲层；其中，所述第一侧壁和所述第二侧壁为所述第一沟槽内相对的不同侧壁；Above the third isolation structure, a first sacrificial layer covering the first sidewall of the first trench is formed, and a second sacrificial layer covering the second sidewall of the first trench is formed; wherein, The first sidewall and the second sidewall are different opposite sidewalls in the first trench;

在所述第一牺牲层和所述第二牺牲层之间形成间隔层；forming a spacer layer between the first sacrificial layer and the second sacrificial layer;

去除所述第一牺牲层，形成第二沟槽；removing the first sacrificial layer to form a second trench;

在所述第二沟槽中形成所述字线结构；forming the word line structure in the second trench;

去除所述第二牺牲层，形成第三沟槽；removing the second sacrificial layer to form a third trench;

在所述第三沟槽中形成所述第二隔离结构。The second isolation structure is formed in the third trench.

在一些实施例中，所述形成覆盖所述第一沟槽的第一侧壁的第一牺牲层，并形成覆盖所述第一沟槽的第二侧壁的第二牺牲层，包括：In some embodiments, forming a first sacrificial layer covering a first sidewall of the first trench and forming a second sacrificial layer covering a second sidewall of the first trench includes:

在所述第一沟槽内形成覆盖所述第一沟槽内壁的牺牲层；forming a sacrificial layer covering the inner wall of the first trench in the first trench;

去除所述第三隔离结构上表面的部分所述牺牲层，形成相互分离的所述第一牺牲层和所述第二牺牲层。Part of the sacrificial layer on the upper surface of the third isolation structure is removed to form the first sacrificial layer and the second sacrificial layer separated from each other.

在一些实施例中，所述去除所述第一牺牲层，形成第二沟槽，包括：In some embodiments, the removing the first sacrificial layer to form the second trench includes:

在所述第二牺牲层靠近所述衬底表面的一端上形成第四沟槽；forming a fourth trench on one end of the second sacrificial layer close to the surface of the substrate;

在所述第四沟槽中形成覆盖所述第二牺牲层的第二保护层；forming a second protective layer covering the second sacrificial layer in the fourth trench;

去除所述第一牺牲层，形成所述第二沟槽。The first sacrificial layer is removed to form the second trench.

在一些实施例中，所述去除所述第二牺牲层，形成第三沟槽，包括：In some embodiments, the removing the second sacrificial layer to form the third trench includes:

去除所述第二保护层；removing the second protective layer;

去除所述第二牺牲层，形成所述第三沟槽。The second sacrificial layer is removed to form the third trench.

在一些实施例中，所述在所述第二沟槽中形成所述字线结构，包括：In some embodiments, the forming the word line structure in the second trench includes:

去除所述间隔层和所述第二沟槽中的第一氧化层；removing the spacer layer and the first oxide layer in the second trench;

在所述第二沟槽的侧壁形成栅氧化层；forming a gate oxide layer on the sidewall of the second trench;

在所述第二沟槽中填充导电材料；filling the second trenches with conductive material;

去除至少部分所述导电材料，形成具有第三厚度的字线，所述第三厚度小于所述第二沟槽的深度；removing at least a portion of the conductive material to form wordlines having a third thickness, the third thickness being less than the depth of the second trench;

在所述第二沟槽中的所述字线上填充绝缘材料，形成栅保护层；其中所述字线结构包括所述栅氧化层、所述字线和所述栅保护层。An insulating material is filled on the word line in the second trench to form a gate protection layer; wherein the word line structure includes the gate oxide layer, the word line and the gate protection layer.

在一些实施例中，所述在所述第三沟槽中形成所述第二隔离结构，包括：In some embodiments, the forming the second isolation structure in the third trench includes:

在所述第三沟槽中填充绝缘材料，形成中间具有空气间隙的所述第二隔离结构。An insulating material is filled in the third trench to form the second isolation structure with an air gap therebetween.

在一些实施例中，所述方法还包括：In some embodiments, the method further includes:

对所述沟道柱的第一端进行掺杂，形成晶体管的源极；Doping the first end of the channel column to form the source of the transistor;

对所述沟道柱的第二端进行掺杂，形成所述晶体管的漏极。Doping the second end of the channel pillar forms the drain of the transistor.

在一些实施例中，所述在所述字线结构相邻的所述沟道柱的表面形成存储结构，包括：In some embodiments, forming a storage structure on the surface of the channel pillar adjacent to the word line structure includes:

在所述字线结构相邻的所述源极的表面上形成存储电容。A storage capacitor is formed on the surface of the source electrode adjacent to the word line structure.

在一些实施例中，所述对所述沟道柱的第二端进行掺杂，形成所述晶体管的漏极，包括：In some embodiments, doping the second end of the channel pillar to form the drain of the transistor includes:

对所述衬底的背面进行减薄，直至暴露所述第三隔离结构；thinning the backside of the substrate until the third isolation structure is exposed;

对所述第三隔离结构相邻的所述沟道柱的第二端进行掺杂，形成所述晶体管的漏极。Doping the second end of the channel column adjacent to the third isolation structure to form the drain of the transistor.

在一些实施例中，所述方法还包括：In some embodiments, the method further includes:

在所述衬底的背面，形成连接所述晶体管的漏极的位线。On the backside of the substrate, bit lines are formed that connect the drains of the transistors.

在一些实施例中，所述在所述衬底的背面，形成连接所述晶体管的漏极的位线，包括：In some embodiments, forming a bit line connected to the drain of the transistor on the backside of the substrate includes:

在所述漏极表面形成位线接触结构；forming a bit line contact structure on the surface of the drain;

在所述位线接触结构上形成所述位线。The bit line is formed on the bit line contact structure.

另一方面，本申请实施例还提供了一种存储器，所述存储器包括：On the other hand, an embodiment of the present application further provides a memory, and the memory includes:

衬底；substrate;

位于所述衬底中且沿第一方向延伸的若干相互平行的第一隔离结构；所述第一方向平行于所述衬底表面；所述第一隔离结构的第一厚度小于或等于所述衬底的厚度；a plurality of mutually parallel first isolation structures located in the substrate and extending along a first direction; the first direction is parallel to the surface of the substrate; the first thickness of the first isolation structures is less than or equal to the the thickness of the substrate;

位于所述衬底中且沿第二方向延伸的若干相互平行的第一沟槽；所述第二方向平行于所述衬底表面且与所述第一方向垂直；所述第一沟槽与所述第一隔离结构将所述衬底划分为多个沟道柱；A plurality of mutually parallel first trenches located in the substrate and extending along a second direction; the second direction is parallel to the surface of the substrate and perpendicular to the first direction; the first trenches and the first isolation structure divides the substrate into a plurality of channel pillars;

位于所述第一沟槽内的字线结构和第二隔离结构；其中，所述字线结构和所述第二隔离结构并列排布，且沿所述第一沟槽的侧壁延伸；a word line structure and a second isolation structure located in the first trench; wherein the word line structure and the second isolation structure are arranged side by side and extend along the sidewall of the first trench;

位于所述字线结构相邻的所述沟道柱的表面的存储结构。A storage structure located on a surface of the channel pillar adjacent to the word line structure.

在一些实施例中，所述存储器还包括：In some embodiments, the memory further includes:

位于所述第一沟槽底部的具有第二厚度的第三隔离结构；所述第二厚度小于所述第一沟槽的深度；所述字线结构和所述第二隔离结构位于所述第三隔离结构上方。a third isolation structure with a second thickness at the bottom of the first trench; the second thickness is less than the depth of the first trench; the word line structure and the second isolation structure are located in the first trench Above the three isolation structures.

在一些实施例中，所述存储器还包括：In some embodiments, the memory further includes:

第一保护层，位于所述第三隔离结构和所述第一沟槽的内壁之间；a first protective layer, located between the third isolation structure and the inner wall of the first trench;

第一氧化层，位于所述第一保护层和所述第一沟槽的内壁之间。The first oxide layer is located between the first protective layer and the inner wall of the first trench.

在一些实施例中，所述字线结构包括：In some embodiments, the word line structure includes:

字线，位于所述第三隔离结构上方；a word line located above the third isolation structure;

栅氧化层，位于所述字线和相邻的所述沟道柱之间；a gate oxide layer, located between the word line and the adjacent channel pillar;

栅保护层，位于所述字线上方。A gate protection layer is located above the word lines.

在一些实施例中，所述第二隔离结构中具有空气间隙。In some embodiments, the second isolation structure has an air gap therein.

在一些实施例中，所述沟道柱包括：In some embodiments, the channel pillars include:

位于所述沟道柱第一端的晶体管的源极；the source of the transistor at the first end of the channel pillar;

位于所述沟道柱第二端的所述晶体管的漏极。a drain of the transistor at the second end of the channel pillar.

在一些实施例中，所述存储结构包括：In some embodiments, the storage structure includes:

存储电容，位于所述源极的表面且连接所述源极。The storage capacitor is located on the surface of the source electrode and connected to the source electrode.

在一些实施例中，所述存储器还包括：In some embodiments, the memory further includes:

位线，位于所述衬底的背面，所述位线连接所述漏极。A bit line is located on the backside of the substrate, and the bit line is connected to the drain.

在一些实施例中，所述存储器还包括：In some embodiments, the memory further includes:

位线接触结构，位于所述漏极的表面，所述位线接触结构连接所述漏极和所述位线。A bit line contact structure is located on the surface of the drain electrode, and the bit line contact structure connects the drain electrode and the bit line.

本申请实施例提供的存储器的制造方法，在第一沟槽中形成并列排布的字线结构和第二隔离结构，并在字线结构相邻的沟道柱的表面形成存储结构。如此，一方面，通过形成垂直排列的晶体管，极大地缩小了存储单元的面积；另一方面，可以将存储器中源极和漏极所连接的不同结构分别设计在衬底相对的两个面上，从而简化了存储器内部的电路布局，降低了存储器制造的工艺难度。In the method for manufacturing a memory provided by an embodiment of the present application, a word line structure and a second isolation structure arranged in parallel are formed in a first trench, and a storage structure is formed on the surface of a channel column adjacent to the word line structure. In this way, on the one hand, by forming vertically arranged transistors, the area of the memory cell is greatly reduced; on the other hand, the different structures connected to the source and drain in the memory can be designed on two opposite sides of the substrate. , thereby simplifying the circuit layout inside the memory and reducing the technological difficulty of memory manufacturing.

附图说明Description of drawings

图1A为本申请实施例提供的一种晶体管的结构示意图；FIG. 1A is a schematic structural diagram of a transistor according to an embodiment of the present application;

图1B为本申请实施例提供的一种晶体管的结构示意图；FIG. 1B is a schematic structural diagram of a transistor according to an embodiment of the present application;

图1C为本申请实施例提供的一种存储单元的示意图；1C is a schematic diagram of a storage unit provided by an embodiment of the present application;

图1D为本申请实施例提供的一种存储单元阵列的示意图；FIG. 1D is a schematic diagram of a memory cell array provided by an embodiment of the present application;

图1E至图1G为本申请实施例提供的一种存储单元阵列的结构示意图；1E to FIG. 1G are schematic structural diagrams of a memory cell array according to an embodiment of the present application;

图2为本申请实施例提供的一种存储器的制造方法的步骤流程图；FIG. 2 is a flowchart of steps of a method for manufacturing a memory according to an embodiment of the present application;

图3A至图3G为本申请实施例提供的一种存储器的制造方法的工艺过程示意图；3A to 3G are schematic process diagrams of a method for manufacturing a memory according to an embodiment of the present application;

图4为本申请实施例提供的一种形成第三隔离结构的结构示意图；4 is a schematic structural diagram of forming a third isolation structure according to an embodiment of the present application;

图5为本申请实施例提供的一种形成第三隔离结构的结构示意图；FIG. 5 is a schematic structural diagram of forming a third isolation structure according to an embodiment of the present application;

图6A至图6C为本申请实施例提供的一种形成第三隔离结构的工艺过程示意图；6A to 6C are schematic diagrams of a process for forming a third isolation structure according to an embodiment of the present application;

图7为本申请实施例提供的一种形成字线结构和第二隔离结构的步骤流程图；7 is a flowchart of steps for forming a word line structure and a second isolation structure provided by an embodiment of the present application;

图8A至图8F为本申请实施例提供的一种形成字线结构和第二隔离结构的工艺过程示意图；8A to 8F are schematic diagrams of a process for forming a word line structure and a second isolation structure according to an embodiment of the present application;

图9A和图9B为本申请实施例提供的一种形成第一牺牲层和第二牺牲层的工艺过程示意图；9A and 9B are schematic diagrams of a process for forming a first sacrificial layer and a second sacrificial layer according to an embodiment of the present application;

图10A至图10D为本申请实施例提供的一种形成第二沟槽的工艺过程示意图；10A to 10D are schematic diagrams of a process for forming a second trench according to an embodiment of the present application;

图11A至图11E为本申请实施例提供的一种形成字线结构的工艺过程示意图；11A to 11E are schematic diagrams of a process for forming a word line structure according to an embodiment of the present application;

图12A和图12B为本申请实施例提供的一种形成第三沟槽的工艺过程示意图；12A and 12B are schematic diagrams of a process for forming a third trench according to an embodiment of the present application;

图13为本申请实施例提供的一种形成第二隔离结构的结构示意图；13 is a schematic structural diagram of forming a second isolation structure according to an embodiment of the present application;

图14A和图14B为本申请实施例提供的一种形成第三保护层的工艺过程示意图；14A and 14B are schematic diagrams of a process for forming a third protective layer according to an embodiment of the present application;

图15为本申请实施例提供的一种形成晶体管的源极和漏极的结构示意图；15 is a schematic structural diagram of forming a source electrode and a drain electrode of a transistor according to an embodiment of the present application;

图16为本申请实施例提供的一种形成存储结构的结构示意图；FIG. 16 is a schematic structural diagram of forming a storage structure according to an embodiment of the present application;

图17A和图17B为本申请实施例提供的一种形成晶体管的漏极的工艺过程示意图；17A and 17B are schematic diagrams of a process for forming a drain of a transistor according to an embodiment of the present application;

图18为本申请实施例提供的一种形成位线的结构示意图；FIG. 18 is a schematic structural diagram of forming a bit line according to an embodiment of the present application;

图19为本申请实施例提供的一种形成位线接触结构的结构示意图；19 is a schematic structural diagram of forming a bit line contact structure according to an embodiment of the present application;

图20A和图20B为本申请实施例提供的一种存储器的结构示意图；20A and 20B are schematic structural diagrams of a memory provided by an embodiment of the present application;

图21为本申请实施例提供的一种存储器中第三隔离结构的结构示意图；21 is a schematic structural diagram of a third isolation structure in a memory according to an embodiment of the present application;

图22为本申请实施例提供的一种存储器中第一保护层和第一氧化层的结构示意图；22 is a schematic structural diagram of a first protective layer and a first oxide layer in a memory provided by an embodiment of the present application;

图23为本申请实施例提供的一种存储器中字线结构的结构示意图；23 is a schematic structural diagram of a word line structure in a memory according to an embodiment of the present application;

图24为本申请实施例提供的一种存储器中空气间隙的结构示意图；24 is a schematic structural diagram of an air gap in a memory according to an embodiment of the present application;

图25为本申请实施例提供的一种存储器中第三保护层的结构示意图；FIG. 25 is a schematic structural diagram of a third protection layer in a memory according to an embodiment of the present application;

图26为本申请实施例提供的一种存储器中晶体管的源极和漏极的结构示意图；26 is a schematic structural diagram of a source and a drain of a transistor in a memory according to an embodiment of the present application;

图27为本申请实施例提供的一种存储器中存储结构的结构示意图；27 is a schematic structural diagram of a storage structure in a memory according to an embodiment of the present application;

图28A至图28C为本申请实施例提供的一种存储器中存储电容的结构示意图；28A to 28C are schematic structural diagrams of a storage capacitor in a memory provided by an embodiment of the present application;

图29A和图29B为本申请实施例提供的一种存储器中存储电容的排布示意图；29A and 29B are schematic diagrams of the arrangement of storage capacitors in a memory provided by an embodiment of the present application;

图30为本申请实施例提供的一种存储器中位线的结构示意图；30 is a schematic structural diagram of a bit line in a memory according to an embodiment of the present application;

图31为本申请实施例提供的一种存储器中位线接触结构的结构示意图。FIG. 31 is a schematic structural diagram of a bit line contact structure in a memory according to an embodiment of the present application.

具体实施方式Detailed ways

为了便于理解本申请，下面将参照相关附图更详细地描述本申请公开的示例性实施方式。虽然附图中显示了本申请的示例性实施方式，然而应当理解，可以以各种形式实现本申请，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本申请，并且能够将本申请公开的范围完整的传达给本领域的技术人员。In order to facilitate understanding of the present application, exemplary embodiments disclosed in the present application will be described in more detail below with reference to the related drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited by the specific embodiments set forth herein. Rather, these embodiments are provided so that the present application will be more thoroughly understood, and will fully convey the scope of the present disclosure to those skilled in the art.

在下文的描述中，给出了大量具体的细节以便提供对本申请更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本申请可以无需一个或多个这些细节而得以实施。在一些实施例中，为了避免与本申请发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里可以不描述实际实施例的全部特征，不详细描述公知的功能和结构。In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced without one or more of these details. In some embodiments, in order to avoid confusion with the present application, some technical features known in the art are not described; that is, all features of actual embodiments may not be described herein, and well-known functions and structures may not be described in detail.

一般地，术语可以至少部分地从上下文中的使用来理解。例如，至少部分地取决于上下文，如本文中所用的术语“一个或多个”可以用于以单数意义描述任何特征、结构或特性，或者可以用于以复数意义描述特征、结构或特性的组合。类似地，诸如“一”或“所述”的术语同样可以被理解为传达单数用法或传达复数用法，这至少部分地取决于上下文。另外，属于“基于”可以被理解为不一定旨在传达排他的一组因素，并且可以替代地允许存在不一定明确地描述的附加因素，这同样至少部分地取决于上下文。In general, terms can be understood, at least in part, from their contextual usage. For example, the term "one or more" as used herein may be used to describe any feature, structure or characteristic in the singular or may be used to describe a combination of features, structures or characteristics in the plural, depending at least in part on the context . Similarly, terms such as "a" or "said" may also be understood to convey singular usage or to convey plural usage, depending at least in part on the context. Additionally, belonging to "based on" may be understood as not necessarily intended to convey an exclusive set of factors, and may instead allow for the presence of additional factors not necessarily explicitly described, again depending at least in part on context.

除非另有定义，本文所使用的术语的目的仅在于描述具体实施例并且不作为本申请的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。Unless otherwise defined, terms used herein are for the purpose of describing particular embodiments only and are not limiting of the present application. As used herein, the singular forms "a," "an," and "the/the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms "compose" and/or "include", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or components, but do not exclude one or more other The presence or addition of features, integers, steps, operations, elements, parts and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

为了彻底理解本申请，将在下列的描述中提出详细的步骤以及详细的结构，以便阐释本申请的技术方案。本申请的较佳实施例详细描述如下，然而除了这些详细描述外，本申请还可以具有其他实施方式。For a thorough understanding of the present application, detailed steps and detailed structures will be presented in the following description in order to explain the technical solutions of the present application. The preferred embodiments of the present application are described in detail below, however, the present application may have other embodiments in addition to these detailed descriptions.

在一些实施例中，存储器的晶体管包括平面晶体管（Planar）和填埋式沟道晶体管（Buried Channel Array Transistor，BCAT），然而不论是平面晶体管还是填埋式沟道晶体管，其结构上，源极和漏极均位于栅极的水平两侧。In some embodiments, the transistors of the memory include a planar transistor (Planar) and a buried channel transistor (BCAT). However, whether it is a planar transistor or a buried channel transistor, the source and drain are located on the horizontal sides of the gate.

如图1A所示为平面晶体管的结构示意图，图1B为填埋式沟道晶体管的结构示意图。应当理解，图中为了使得各结构均能被清晰示出，可能造成各结构的尺寸比例关系与实际结构不符。其中，晶体管的源极101和漏极102分别位于栅极103的两侧，如此，在水平面上源极101和漏极102分别占用了不同的位置，使得不论是平面晶体管还是填埋式沟道晶体管的水平面积都较大。此外，由于电容104（Capacitor）和位线105（Bit Line，BL）在晶体管的同侧，在加工工艺中都位于衬底的一侧。以填埋式沟道晶体管为例，电容104的接触线需要穿过位线105，使得整体的工艺复杂度较高，对于光刻工艺和对准度有极高的要求。FIG. 1A is a schematic structural diagram of a planar transistor, and FIG. 1B is a structural schematic diagram of a buried channel transistor. It should be understood that in order to make each structure clearly shown in the drawings, the dimensional proportional relationship of each structure may be inconsistent with the actual structure. Thesource electrode 101 and thedrain electrode 102 of the transistor are located on both sides of thegate electrode 103, respectively, so that thesource electrode 101 and thedrain electrode 102 occupy different positions respectively on the horizontal plane, so that whether it is a planar transistor or a buried channel The horizontal area of the transistors is larger. In addition, since the capacitor 104 (Capacitor) and the bit line 105 (Bit Line, BL) are on the same side of the transistor, they are both located on one side of the substrate in the processing process. Taking the buried channel transistor as an example, the contact line of thecapacitor 104 needs to pass through thebit line 105 , so that the overall process complexity is high, and the photolithography process and alignment degree are extremely required.

图1C为随机存取存储器中一个存储单元的示意图，图1D为随机存取存储器中存储单元阵列的示意图。其中，字线用于控制晶体管的通断，位线用于在晶体管导通时对电容进行读取和写入操作，电容的一端连接晶体管，另一端接地。1C is a schematic diagram of a memory cell in a random access memory, and FIG. 1D is a schematic diagram of a memory cell array in the random access memory. The word line is used to control the on-off of the transistor, and the bit line is used to read and write the capacitor when the transistor is on. One end of the capacitor is connected to the transistor, and the other end is grounded.

图1E为在一些实施例中存储单元阵列的晶体管的有源区的排布示意图。如图1E所示，有源区210的方向可以和位线呈18~25°夹角。1E is a schematic diagram of the arrangement of active regions of transistors of a memory cell array in some embodiments. As shown in FIG. 1E , the direction of theactive region 210 may form an included angle of 18-25° with the bit line.

图1F为在一些实施例中存储单元阵列的结构示意图。如图1F所示，字线220（WordLine，WL）和位线230互相垂直，每个有源区210与两条字线220和一条位线230相交。FIG. 1F is a schematic structural diagram of a memory cell array in some embodiments. As shown in FIG. 1F , word lines 220 (WordLine, WL) andbit lines 230 are perpendicular to each other, and eachactive region 210 intersects twoword lines 220 and onebit line 230 .

图1G为在一些实施例中存储单元阵列的局部结构示意图。如图1G所示，每个有源区210具有两个存储节点接触结构211（Storage Node Contact，SNC）和一个位线接触结构212（Bit Line Contact，BLC）。其中，两个存储节点接触结构211分别连接至两个电容，一个位线接触结构212连接至一条位线230。由此，单个位线230可以通过两条字线220的开关分别控制相邻的两个电容，从而进行读取和写入操作。从平面上看单位存储单元的尺寸为6F²（F为存储单元的最小外形尺寸，F²则表示单位面积），占用面积较大。FIG. 1G is a schematic diagram of a partial structure of a memory cell array in some embodiments. As shown in FIG. 1G , eachactive region 210 has two storage node contact structures 211 (Storage Node Contact, SNC) and one bit line contact structure 212 (Bit Line Contact, BLC). Wherein, two storagenode contact structures 211 are respectively connected to two capacitors, and one bitline contact structure 212 is connected to onebit line 230 . Thus, asingle bit line 230 can control two adjacent capacitors through the switches of the twoword lines 220, so as to perform read and write operations. From a plane view, the size of the unit storage unit is 6F² (F is the minimum external dimension of the storage unit, and F² represents the unit area), which occupies a large area.

如图2所示，本申请实施例提供了一种存储器的制造方法，其对应的结构如图3A至图3F所示，所述制造方法包括以下步骤：As shown in FIG. 2 , an embodiment of the present application provides a method for manufacturing a memory, the corresponding structure of which is shown in FIGS. 3A to 3F , and the manufacturing method includes the following steps:

步骤S10、提供衬底300；Step S10, providing asubstrate 300;

步骤S20、在所述衬底300中形成沿第一方向延伸的若干相互平行的第一隔离结构310；所述第一方向平行于所述衬底300表面；所述第一隔离结构310的第一厚度小于所述衬底300的厚度；Step S20 , forming a plurality of mutually parallelfirst isolation structures 310 extending along a first direction in thesubstrate 300 ; the first direction is parallel to the surface of thesubstrate 300 ; a thickness less than the thickness of thesubstrate 300;

步骤S30、在所述衬底300中形成沿第二方向延伸的若干相互平行的第一沟槽320；所述第二方向平行于所述衬底300表面且与所述第一方向垂直；所述第一沟槽320与所述第一隔离结构310将所述衬底300划分为多个沟道柱330；Step S30, forming a plurality of mutually parallelfirst trenches 320 extending along a second direction in thesubstrate 300; the second direction is parallel to the surface of thesubstrate 300 and perpendicular to the first direction; so Thefirst trench 320 and thefirst isolation structure 310 divide thesubstrate 300 into a plurality ofchannel pillars 330;

步骤S40、在所述第一沟槽320内形成字线结构340和第二隔离结构350；其中，所述字线结构340和所述第二隔离结构350并列排布，且沿所述第一沟槽320的侧壁延伸；Step S40, forming aword line structure 340 and asecond isolation structure 350 in thefirst trench 320; wherein, theword line structure 340 and thesecond isolation structure 350 are arranged side by side, and along the first sidewalls of thetrenches 320 extend;

步骤S50、在所述字线结构340相邻的所述沟道柱330的表面形成存储结构360。Step S50 , forming astorage structure 360 on the surface of thechannel pillar 330 adjacent to theword line structure 340 .

在本申请实施例中，衬底300可以是硅（Si）、锗（Ge）等半导体材料。在一些实施例中，衬底300还可以是掺杂的，或者在衬底中包括掺杂区域和未掺杂区域。衬底300中用于形成第一沟槽320的一面可以作为衬底300的表面，与衬底300的表面相背的一面可以作为衬底300的背面。In this embodiment of the present application, thesubstrate 300 may be a semiconductor material such as silicon (Si) or germanium (Ge). In some embodiments, thesubstrate 300 may also be doped, or include doped and undoped regions in the substrate. The side of thesubstrate 300 for forming thefirst trenches 320 can be used as the surface of thesubstrate 300 , and the side opposite to the surface of thesubstrate 300 can be used as the back surface of thesubstrate 300 .

在本申请实施例中，如图3A所示，在衬底300的表面上形成沿第一方向延伸的若干第一隔离结构310。其中，第一方向平行于衬底表面，与Y方向一致；如图3B所示，第一隔离结构310在Z方向上的第一厚度小于衬底300的厚度。可选的，通过刻蚀（Etching）和/或光刻（Photolithography）工艺在衬底300的表面形成沿第一方向延伸的若干隔离槽；然后通过沉积工艺在隔离槽中形成第一隔离结构310。第一隔离结构310的材料包括但不限于二氧化硅（SiO₂）、旋涂绝缘介质（Spin-on Dielectrics，SOD）、氮化硅（Si₃N₄）、氮氧化硅（SiON）。值得注意的是，本申请实施例中，对衬底的刻蚀是在Z方向进行的部分刻蚀，刻蚀过程不会将衬底刻穿。通常，刻蚀工艺可以分为干法刻蚀（Dry Etching）与湿法刻蚀（Wet Etching）。其中，干法刻蚀可以包括离子铣刻蚀（Ion Neam Milling Etching）、等离子体刻蚀（PlasmaEtching）、反应离子刻蚀（Reactive Ion Etching）或激光烧蚀（Laser Ablation）等；湿法刻蚀是利用溶剂或溶液来进行刻蚀，例如酸碱溶液。沉积工艺包括但不限于化学气相沉积（Chemical Vapor Deposition，CVD）、原子层沉积（Atomic Layer Deposition，ALD）或物理气相沉积（Physical Vapor Deposition，PVD）等。In this embodiment of the present application, as shown in FIG. 3A , a plurality offirst isolation structures 310 extending along the first direction are formed on the surface of thesubstrate 300 . The first direction is parallel to the surface of the substrate and is consistent with the Y direction; as shown in FIG. 3B , the first thickness of thefirst isolation structure 310 in the Z direction is smaller than the thickness of thesubstrate 300 . Optionally, a plurality of isolation trenches extending along the first direction are formed on the surface of thesubstrate 300 by an etching (Etching) and/or photolithography (Photolithography) process; then afirst isolation structure 310 is formed in the isolation trenches by a deposition process . Materials of thefirst isolation structure 310 include, but are not limited to, silicon dioxide (SiO₂ ), spin-on dielectrics (SOD), silicon nitride (Si₃ N₄ ), and silicon oxynitride (SiON). It is worth noting that, in the embodiment of the present application, the etching of the substrate is a partial etching performed in the Z direction, and the etching process will not etch through the substrate. Generally, the etching process can be divided into dry etching (Dry Etching) and wet etching (Wet Etching). Among them, dry etching may include ion milling etching (Ion Neam Milling Etching), plasma etching (Plasma Etching), reactive ion etching (Reactive Ion Etching) or laser ablation (Laser Ablation), etc.; wet etching Etching is performed using a solvent or solution, such as an acid-base solution. The deposition process includes, but is not limited to, chemical vapor deposition (Chemical Vapor Deposition, CVD), atomic layer deposition (Atomic Layer Deposition, ALD), or physical vapor deposition (Physical Vapor Deposition, PVD), and the like.

如图3C所示，在形成上述第一隔离结构310之后，可以通过刻蚀和/或光刻工艺在衬底300的表面上形成沿第二方向延伸的若干相互平行的第一沟槽320。其中，第二方向平行于衬底300表面，与X方向一致，与第一方向垂直。如图3D所示，第一沟槽320在Z方向上的深度小于衬底300的厚度。第一沟槽320与第一隔离结构310将衬底300划分为多个沟道柱330。沟道柱330的长度方向与Z方向一致，从而使得沟道柱330靠近衬底300表面和背面的两端，可以分别形成存储器中晶体管的源极和漏极，即存储器中的晶体管的方向垂直于衬底表面。由此，垂直的晶体管占用面积更小，故单位面积上存储单元的密度更大。As shown in FIG. 3C , after the above-mentionedfirst isolation structure 310 is formed, a plurality of mutually parallelfirst trenches 320 extending along the second direction may be formed on the surface of thesubstrate 300 through an etching and/or photolithography process. The second direction is parallel to the surface of thesubstrate 300, consistent with the X direction, and perpendicular to the first direction. As shown in FIG. 3D , the depth of thefirst trench 320 in the Z direction is smaller than the thickness of thesubstrate 300 . Thefirst trench 320 and thefirst isolation structure 310 divide thesubstrate 300 into a plurality ofchannel pillars 330 . The length direction of thechannel pillar 330 is consistent with the Z direction, so that thechannel pillar 330 is close to the two ends of the surface and the back of thesubstrate 300, and the source and drain of the transistor in the memory can be respectively formed, that is, the direction of the transistor in the memory is vertical. on the substrate surface. As a result, the vertical transistor occupies a smaller area, so the density of memory cells per unit area is higher.

如图3E所示，在第一沟槽320内形成字线结构340和第二隔离结构350。其中，字线结构340与第二隔离结构350在Y方向上并列排布，并在X方向上沿着第一沟槽320的侧壁延伸。字线结构340和第二隔离结构350分别覆盖第一沟槽320相对的两个侧壁，第二隔离结构350用于电隔离字线结构340和相邻晶体管中的沟道柱330。可选的，可以在第一沟槽320内分别形成字线结构340和第二隔离结构350对应的牺牲层，然后依次对牺牲层进行替换，形成字线结构340与第二隔离结构350。字线结构340可以包括字线、栅氧化层、栅保护层等结构，其中字线为导电材料，包括但不限于钨（W）、氮化钛（TiN）、铜（Cu）、银（Ag）中的一种或多种。第二隔离结构350的材料包括但不限于二氧化硅、旋涂绝缘介质、氮化硅、氮氧化硅中的一种或多种。As shown in FIG. 3E ,word line structures 340 andsecond isolation structures 350 are formed within thefirst trenches 320 . Theword line structures 340 and thesecond isolation structures 350 are arranged side by side in the Y direction and extend along the sidewalls of thefirst trenches 320 in the X direction. Theword line structure 340 and thesecond isolation structure 350 respectively cover two opposite sidewalls of thefirst trench 320, and thesecond isolation structure 350 is used to electrically isolate theword line structure 340 from thechannel pillars 330 in adjacent transistors. Optionally, sacrificial layers corresponding to theword line structure 340 and thesecond isolation structure 350 may be respectively formed in thefirst trench 320 , and then the sacrificial layers are sequentially replaced to form theword line structure 340 and thesecond isolation structure 350 . Theword line structure 340 may include structures such as word lines, gate oxide layers, gate protection layers, etc., wherein the word lines are conductive materials, including but not limited to tungsten (W), titanium nitride (TiN), copper (Cu), silver (Ag) ) one or more of. The material of thesecond isolation structure 350 includes, but is not limited to, one or more of silicon dioxide, spin-on insulating dielectric, silicon nitride, and silicon oxynitride.

如图3F所示，在字线结构340相邻的沟道柱330的表面形成存储结构360。沟道柱330的方向与Z方向一致，故可以在沟道柱330的两端，分别形成晶体管的源极和漏极，即存储器中的晶体管的方向垂直于衬底表面。存储结构360可以形成在沟道柱330任意一端的表面上，与晶体管的源极或漏极连接，沟道柱330的另一端则可以用于形成位线等结构。在随机存取存储器中，存储结构360可以是电容。由此，存储器中源极和漏极所连接的不同结构可以分别设计在衬底300相对的两个面上，从而简化了存储器内部的电路布局，降低了存储器制造的工艺难度。As shown in FIG. 3F , astorage structure 360 is formed on the surface of thechannel pillar 330 adjacent to theword line structure 340 . The direction of thechannel pillar 330 is consistent with the Z direction, so the source and drain of the transistor can be respectively formed at both ends of thechannel pillar 330 , that is, the direction of the transistor in the memory is perpendicular to the substrate surface. Thestorage structure 360 may be formed on the surface of either end of thechannel pillar 330 and connected to the source or drain of the transistor, and the other end of thechannel pillar 330 may be used to form structures such as bit lines. In random access memory,storage structure 360 may be a capacitor. Therefore, different structures connected to the source electrode and the drain electrode in the memory can be designed on two opposite sides of thesubstrate 300 respectively, thereby simplifying the circuit layout inside the memory and reducing the manufacturing process difficulty of the memory.

在一些实施例中，如图3G所示，在形成所述第一沟槽320之前，还可以在衬底300的表面上通过沉积工艺依次形成一层氧化硅层和一层氮化硅层，以在后续的工艺中保护衬底300的表面。In some embodiments, as shown in FIG. 3G, before forming thefirst trench 320, a silicon oxide layer and a silicon nitride layer may be sequentially formed on the surface of thesubstrate 300 by a deposition process, In order to protect the surface of thesubstrate 300 in subsequent processes.

在一些实施例中，如图4所示，所述方法还包括：In some embodiments, as shown in FIG. 4 , the method further includes:

在所述第一沟槽320底部形成第二厚度的第三隔离结构321；所述第二厚度小于所述第一沟槽320的深度；所述字线结构340和所述第二隔离结构350形成于所述第三隔离结构321上方。Athird isolation structure 321 with a second thickness is formed at the bottom of thefirst trench 320; the second thickness is smaller than the depth of thefirst trench 320; theword line structure 340 and thesecond isolation structure 350 formed above thethird isolation structure 321 .

在本申请实施例中，可以通过沉积等工艺在第一沟槽320的底部形成第三隔离结构321，第三隔离结构321在Z方向上的厚度小于第一沟槽320的深度。字线结构340和第二隔离结构350形成于第三隔离结构321的上方，第三隔离结构321用于防止字线结构340在第一沟槽320的底部发生漏电流现象。第三隔离结构321的材料包括但不限于二氧化硅、旋涂绝缘介质、氮化硅、氮氧化硅中的一种或多种。In this embodiment of the present application, thethird isolation structure 321 may be formed at the bottom of thefirst trench 320 by a process such as deposition, and the thickness of thethird isolation structure 321 in the Z direction is smaller than the depth of thefirst trench 320 . Theword line structure 340 and thesecond isolation structure 350 are formed above thethird isolation structure 321 , and thethird isolation structure 321 is used to prevent theword line structure 340 from leaking current at the bottom of thefirst trench 320 . The material of thethird isolation structure 321 includes, but is not limited to, one or more of silicon dioxide, spin-on insulating dielectric, silicon nitride, and silicon oxynitride.

在一些实施例中，如图5所示，所述方法还包括：In some embodiments, as shown in Figure 5, the method further includes:

形成覆盖所述第一沟槽320内壁的第一氧化层322；forming afirst oxide layer 322 covering the inner wall of thefirst trench 320;

形成覆盖所述第一氧化层322的第一保护层323；forming a firstprotective layer 323 covering thefirst oxide layer 322;

所述在所述第一沟槽320底部形成第二厚度的第三隔离结构321，包括：The forming thethird isolation structure 321 with the second thickness at the bottom of thefirst trench 320 includes:

在内壁覆盖有所述第一氧化层322和所述第一保护层323的所述第一沟槽320内，形成所述第三隔离结构321。Thethird isolation structure 321 is formed in thefirst trench 320 whose inner wall is covered with thefirst oxide layer 322 and the firstprotective layer 323 .

在本申请实施例中，可以通过沉积工艺在第一沟槽320的内壁上形成第一氧化层322，这里的内壁包括第一沟槽320的侧壁和底面，第一氧化层322可以为线形氧化层（LinerOxide），第一氧化层322可以在后续工艺中保护第一沟槽320的内壁。然后，利用沉积工艺形成覆盖在第一氧化层322上的第一保护层323，第一保护层323可以为氮化硅等材料，第一保护层323可以作为后续从背面减薄衬底300的停止层。示例性地，采用原子层沉积的方法在第一沟槽320中依次形成第一氧化层322和第一保护层323，然后在内壁覆盖有第一氧化层322和第一保护层323的第一沟槽320的底部，形成具有第二厚度的第三隔离结构321，第二厚度小于第一沟槽320的深度。In this embodiment of the present application, thefirst oxide layer 322 may be formed on the inner wall of thefirst trench 320 through a deposition process, where the inner wall includes the sidewall and the bottom surface of thefirst trench 320, and thefirst oxide layer 322 may be linear An oxide layer (LinerOxide), thefirst oxide layer 322 can protect the inner wall of thefirst trench 320 in subsequent processes. Then, a firstprotective layer 323 covering thefirst oxide layer 322 is formed by a deposition process. The firstprotective layer 323 can be made of materials such as silicon nitride, and the firstprotective layer 323 can be used for subsequent thinning of thesubstrate 300 from the rear stop layer. Exemplarily, the atomic layer deposition method is used to form thefirst oxide layer 322 and the firstprotective layer 323 in thefirst trench 320 in sequence, and then the inner wall is covered with thefirst oxide layer 322 and the firstprotective layer 323. Athird isolation structure 321 having a second thickness is formed at the bottom of thetrench 320 , and the second thickness is smaller than the depth of thefirst trench 320 .

在一些实施例中，如图6A-图6C所示，所述在内壁覆盖有所述第一氧化层322和所述第一保护层323的所述第一沟槽320内，形成所述第三隔离结构321，包括：In some embodiments, as shown in FIGS. 6A-6C , in thefirst trench 320 whose inner wall is covered with thefirst oxide layer 322 and the firstprotective layer 323 , thefirst trench 320 is formed. Threeisolation structures 321, including:

在内壁覆盖有所述第一氧化层322和所述第一保护层323的所述第一沟槽320内，填充绝缘材料；Fill insulating material in thefirst trench 320 whose inner wall is covered with thefirst oxide layer 322 and the firstprotective layer 323;

去除至少部分所述绝缘材料，使所述第一沟槽320底部保留所述第二厚度的所述绝缘材料以形成所述第三隔离结构321；removing at least part of the insulating material so that the insulating material of the second thickness remains at the bottom of thefirst trench 320 to form thethird isolation structure 321;

去除所述第三隔离结构321上方的所述第一保护层323。The firstprotective layer 323 above thethird isolation structure 321 is removed.

在本申请实施例中，如图6A所示，可以通过旋涂绝缘介质工艺，在内壁覆盖有第一氧化层322和第一保护层323的第一沟槽320内，填充绝缘材料，这里的绝缘材料可以为二氧化硅等，当然，也可以使用其他合适的工艺。如图6B所示，可以利用刻蚀等工艺，去除部分上述绝缘材料，使第一沟槽320的底部保留第二厚度的绝缘材料，从而形成第三隔离结构321。如图6C所示，可以通过选择性刻蚀，去除位于第三隔离结构321上方的第一保护层323。由于后续工艺会在第三隔离结构321上方形成字线结构340，且第一保护层323仅作为从背面减薄衬底300的停止层，相应地，可以去除第三隔离结构321上方的第一保护层323。示例性地，采用磷酸（H₃PO₄）、氢氟酸（HF）等选择性刻蚀溶液，可以去除氮化硅材料的第一保护层323，而不与第一氧化层322以及第三隔离结构321中的二氧化硅材料发生反应。In this embodiment of the present application, as shown in FIG. 6A , an insulating material may be filled in thefirst trench 320 whose inner wall is covered with thefirst oxide layer 322 and the firstprotective layer 323 by a spin coating insulating medium process. The insulating material can be silicon dioxide, etc. Of course, other suitable processes can also be used. As shown in FIG. 6B , a process such as etching may be used to remove part of the above-mentioned insulating material, so that the bottom of thefirst trench 320 remains the insulating material of the second thickness, thereby forming thethird isolation structure 321 . As shown in FIG. 6C , the firstprotective layer 323 located above thethird isolation structure 321 may be removed by selective etching. Since theword line structure 340 will be formed over thethird isolation structure 321 in the subsequent process, and the firstprotective layer 323 is only used as a stop layer for thinning thesubstrate 300 from the back side, correspondingly, thefirst protection layer 340 over thethird isolation structure 321 may be removed.Protective layer 323 . Exemplarily, by using a selective etching solution such as phosphoric acid (H₃ PO₄ ), hydrofluoric acid (HF), etc., the firstprotective layer 323 of the silicon nitride material can be removed without contact with thefirst oxide layer 322 and the third The silicon dioxide material in theisolation structure 321 reacts.

在一些实施例中，如图7所示，所述在所述第一沟槽320内形成字线结构340和第二隔离结构350，包括以下步骤，其对应的结构如图8A至图8F所示：In some embodiments, as shown in FIG. 7 , the forming of theword line structure 340 and thesecond isolation structure 350 in thefirst trench 320 includes the following steps, the corresponding structures of which are shown in FIGS. 8A to 8F . Show:

步骤S401：在所述第一沟槽320底部，形成所述第三隔离结构321；Step S401 : forming thethird isolation structure 321 at the bottom of thefirst trench 320 ;

步骤S402：在所述第三隔离结构321上方，形成覆盖所述第一沟槽320的第一侧壁的第一牺牲层324，并形成覆盖所述第一沟槽320的第二侧壁的第二牺牲层325；其中，所述第一侧壁和所述第二侧壁为所述第一沟槽320内相对的不同侧壁；Step S402 : above thethird isolation structure 321 , forming a firstsacrificial layer 324 covering the first sidewall of thefirst trench 320 and forming a second sidewall covering thefirst trench 320 The secondsacrificial layer 325; wherein, the first sidewall and the second sidewall are different sidewalls opposite to each other in thefirst trench 320;

步骤S403：在所述第一牺牲层324和所述第二牺牲层325之间形成间隔层326；Step S403: forming aspacer layer 326 between the firstsacrificial layer 324 and the secondsacrificial layer 325;

步骤S404：去除所述第一牺牲层324，形成第二沟槽327；Step S404: removing the firstsacrificial layer 324 to form asecond trench 327;

步骤S405：在所述第二沟槽327中形成所述字线结构340；Step S405 : forming theword line structure 340 in thesecond trench 327 ;

步骤S406：去除所述第二牺牲层325，形成第三沟槽328；Step S406: removing the secondsacrificial layer 325 to form athird trench 328;

步骤S407：在所述第三沟槽328中形成所述第二隔离结构350。Step S407 : forming thesecond isolation structure 350 in thethird trench 328 .

在本申请实施例中，如图8A所示，可以通过原子层沉积工艺，在第三隔离结构321上方形成第一牺牲层324和第二牺牲层325，第一牺牲层324和第二牺牲层325可以为多晶硅（Polycrystalline Silicon，Poly-Si）材料。其中，第一牺牲层324覆盖于第一沟槽320的第一侧壁上，第二牺牲层325覆盖于第一沟槽320的第二侧壁上，第一侧壁与第二侧壁为第一沟槽320在Y方向上相对的两个侧壁。第一牺牲层324和第二牺牲层325相互分离，且第一牺牲层324和第二牺牲层325之间具有空隙。第一牺牲层324和第二牺牲层325用于形成在第一沟槽320内并列排布，且沿X方向延伸的字线结构340和第二隔离结构350。In this embodiment of the present application, as shown in FIG. 8A , the firstsacrificial layer 324 and the secondsacrificial layer 325 , and the firstsacrificial layer 324 and the second sacrificial layer may be formed over thethird isolation structure 321 by an atomic layer deposition process. 325 may be a polycrystalline silicon (Polycrystalline Silicon, Poly-Si) material. The firstsacrificial layer 324 covers the first sidewall of thefirst trench 320, the secondsacrificial layer 325 covers the second sidewall of thefirst trench 320, and the first sidewall and the second sidewall are The two sidewalls of thefirst trench 320 are opposite to each other in the Y direction. The firstsacrificial layer 324 and the secondsacrificial layer 325 are separated from each other, and there is a gap between the firstsacrificial layer 324 and the secondsacrificial layer 325 . The firstsacrificial layer 324 and the secondsacrificial layer 325 are used to form theword line structure 340 and thesecond isolation structure 350 which are arranged side by side in thefirst trench 320 and extend along the X direction.

如图8B所示，可以通过沉积等工艺，在第一牺牲层324和第二牺牲层325之间的空隙中形成间隔层326，间隔层326可以为二氧化硅等材料，用于在后续去除第一牺牲层324和形成字线结构340的过程中，保护第二牺牲层325。As shown in FIG. 8B , aspacer layer 326 may be formed in the gap between the firstsacrificial layer 324 and the secondsacrificial layer 325 by a process such as deposition, and thespacer layer 326 may be made of silicon dioxide or other materials for subsequent removal. During the process of forming the firstsacrificial layer 324 and theword line structure 340, the secondsacrificial layer 325 is protected.

如图8C所示，可以通过刻蚀等工艺，去除第一牺牲层324，形成第二沟槽327，第二沟槽327用于形成字线结构340。As shown in FIG. 8C , the firstsacrificial layer 324 may be removed by a process such as etching to form asecond trench 327 , and thesecond trench 327 is used to form theword line structure 340 .

如图8D所示，可以通过沉积等工艺，在第二沟槽327中形成字线结构340。字线结构340可以包括字线、栅氧化层、栅保护层等结构，其中字线为导电材料，包括但不限于钨（W）、氮化钛（TiN）、铜（Cu）、银（Ag）中的一种或多种。As shown in FIG. 8D , theword line structure 340 may be formed in thesecond trench 327 by a process such as deposition. Theword line structure 340 may include structures such as word lines, gate oxide layers, gate protection layers, etc., wherein the word lines are conductive materials, including but not limited to tungsten (W), titanium nitride (TiN), copper (Cu), silver (Ag) ) one or more of.

如图8E所示，可以通过刻蚀等工艺，去除第二牺牲层325，形成第三沟槽328，第三沟槽328用于形成第二隔离结构350。As shown in FIG. 8E , the secondsacrificial layer 325 may be removed by a process such as etching to form athird trench 328 , and thethird trench 328 is used to form thesecond isolation structure 350 .

如图8F所示，可以通过沉积等工艺，在第三沟槽328中形成第二隔离结构350。第二隔离结构350用于电隔离字线结构340和相邻晶体管中的沟道柱330。第二隔离结构350的材料包括但不限于二氧化硅、旋涂绝缘介质、氮化硅、氮氧化硅中的一种或多种。As shown in FIG. 8F , thesecond isolation structure 350 may be formed in thethird trench 328 by a process such as deposition. Thesecond isolation structure 350 is used to electrically isolate theword line structure 340 from thechannel pillars 330 in adjacent transistors. The material of thesecond isolation structure 350 includes, but is not limited to, one or more of silicon dioxide, spin-on insulating dielectric, silicon nitride, and silicon oxynitride.

在一些实施例中，如图9A和图9B所示，所述形成覆盖所述第一沟槽320的第一侧壁的第一牺牲层324，并形成覆盖所述第一沟槽320的第二侧壁的第二牺牲层325，包括：In some embodiments, as shown in FIGS. 9A and 9B , the firstsacrificial layer 324 covering the first sidewall of thefirst trench 320 is formed, and the firstsacrificial layer 324 covering thefirst trench 320 is formed. The secondsacrificial layer 325 on the two sidewalls includes:

在所述第一沟槽320内形成覆盖所述第一沟槽320内壁的牺牲层329；forming asacrificial layer 329 covering the inner wall of thefirst trench 320 in thefirst trench 320;

去除所述第三隔离结构321上表面的部分所述牺牲层329，形成相互分离的所述第一牺牲层324和所述第二牺牲层325。Part of thesacrificial layer 329 on the upper surface of thethird isolation structure 321 is removed to form the firstsacrificial layer 324 and the secondsacrificial layer 325 which are separated from each other.

在本申请实施例中，如图9A所示，可以通过沉积等工艺，形成覆盖第一沟槽320内壁，并沿X方向延伸的牺牲层329。这里的内壁包括第一沟槽320的第一侧壁、第二侧壁和第三隔离结构321的上表面，牺牲层329可以为多晶硅材料。In the embodiment of the present application, as shown in FIG. 9A , asacrificial layer 329 covering the inner wall of thefirst trench 320 and extending along the X direction may be formed by a process such as deposition. The inner wall here includes the first sidewall, the second sidewall of thefirst trench 320 and the upper surface of thethird isolation structure 321, and thesacrificial layer 329 may be polysilicon material.

如图9B所示，可以通过干法刻蚀工艺，去除第三隔离结构321上表面的部分所述牺牲层329，使得位于第一侧壁、第二侧壁的牺牲层329相互分离，从而形成第一牺牲层324和第二牺牲层325。第一牺牲层324和第二牺牲层325用于形成在第一沟槽320内并列排布，且沿X方向延伸的字线结构340和第二隔离结构350。As shown in FIG. 9B , a part of thesacrificial layer 329 on the upper surface of thethird isolation structure 321 may be removed by a dry etching process, so that thesacrificial layers 329 on the first sidewall and the second sidewall are separated from each other, thereby forming The firstsacrificial layer 324 and the secondsacrificial layer 325 . The firstsacrificial layer 324 and the secondsacrificial layer 325 are used to form theword line structure 340 and thesecond isolation structure 350 which are arranged side by side in thefirst trench 320 and extend along the X direction.

在一些实施例中，如图10A-图10D所示，所述去除所述第一牺牲层324，形成第二沟槽327，包括：In some embodiments, as shown in FIGS. 10A-10D , the removing the firstsacrificial layer 324 to form thesecond trench 327 includes:

在所述第二牺牲层325靠近所述衬底300表面的一端上形成第四沟槽3251；forming afourth trench 3251 on one end of the secondsacrificial layer 325 close to the surface of thesubstrate 300;

在所述第四沟槽3251中形成覆盖所述第二牺牲层325的第二保护层3252；forming a secondprotective layer 3252 covering the secondsacrificial layer 325 in thefourth trench 3251;

去除所述第一牺牲层324，形成所述第二沟槽327。The firstsacrificial layer 324 is removed to form thesecond trench 327 .

在本申请实施例中，如图10A所示，可以通过刻蚀和/或光刻工艺在第二牺牲层325靠近衬底300的一端上形成第四沟槽3251，第四沟槽3251用于形成第二保护层3252，且第四沟槽3251在XY平面上的投影完全覆盖第二牺牲层325。In this embodiment of the present application, as shown in FIG. 10A , afourth trench 3251 may be formed on one end of the secondsacrificial layer 325 close to thesubstrate 300 through an etching and/or photolithography process, and thefourth trench 3251 is used for The secondprotective layer 3252 is formed, and the projection of thefourth trench 3251 on the XY plane completely covers the secondsacrificial layer 325 .

如图10B所示，可以通过沉积等工艺，在第四沟槽3251中形成覆盖所述第二牺牲层325的第二保护层3252，第二保护层3252可以为二氧化硅等材料。第二保护层3252和间隔层326将第一牺牲层324和第二牺牲层325完全分隔开，从而在后续去除第一牺牲层324和形成字线结构340的过程中，保护第二牺牲层325。As shown in FIG. 10B , a secondprotective layer 3252 covering the secondsacrificial layer 325 can be formed in thefourth trench 3251 by a process such as deposition, and the secondprotective layer 3252 can be made of a material such as silicon dioxide. The secondprotective layer 3252 and thespacer layer 326 completely separate the firstsacrificial layer 324 and the secondsacrificial layer 325, so as to protect the second sacrificial layer during subsequent removal of the firstsacrificial layer 324 and formation of theword line structure 340 325.

需要说明的是，由于第四沟槽3251与衬底300表面存在高度差，故在沉积形成第二保护层3252后，如图10C所示，第二保护层3252和衬底300的表面会存在不平整的现象，影响后续工艺。可选的，在沉积形成第二保护层3252后，可以对衬底300的表面进行平坦化处理，例如化学机械抛光（Chemical Mechanical Polishing，CMP），来去除多余的半导体材料。It should be noted that, due to the height difference between thefourth trench 3251 and the surface of thesubstrate 300, after the secondprotective layer 3252 is deposited and formed, as shown in FIG. 10C, the secondprotective layer 3252 and the surface of thesubstrate 300 will exist The uneven phenomenon affects the subsequent process. Optionally, after the secondprotective layer 3252 is deposited and formed, the surface of thesubstrate 300 may be planarized, such as chemical mechanical polishing (Chemical Mechanical Polishing, CMP), to remove excess semiconductor material.

如图10D所示，可以通过刻蚀等工艺，去除第一牺牲层324，形成第二沟槽327，第二沟槽327用于形成字线结构340。As shown in FIG. 10D , the firstsacrificial layer 324 may be removed by a process such as etching to form asecond trench 327 , and thesecond trench 327 is used to form theword line structure 340 .

在一些实施例中，如图11A-图11E所示，所述在所述第二沟槽327中形成所述字线结构340，包括：In some embodiments, as shown in FIGS. 11A-11E , the forming theword line structure 340 in thesecond trench 327 includes:

去除所述间隔层326和所述第二沟槽327中的第一氧化层322；removing thespacer layer 326 and thefirst oxide layer 322 in thesecond trench 327;

在所述第二沟槽327的侧壁形成栅氧化层341；Agate oxide layer 341 is formed on the sidewall of thesecond trench 327;

在所述第二沟槽327中填充导电材料；filling thesecond trench 327 with conductive material;

去除至少部分所述导电材料，形成具有第三厚度的字线342，所述第三厚度小于所述第二沟槽327的深度；removing at least part of the conductive material to formword lines 342 having a third thickness, the third thickness being less than the depth of thesecond trench 327;

在所述第二沟槽327中的所述字线342上填充绝缘材料，形成栅保护层343；其中所述字线结构340包括所述栅氧化层341、所述字线342和所述栅保护层343。An insulating material is filled on theword line 342 in thesecond trench 327 to form agate protection layer 343; wherein theword line structure 340 includes thegate oxide layer 341, theword line 342 and the gateProtective layer 343 .

在本申请实施例中，如图11A所示，为了在第二沟槽327的侧壁形成目标厚度且质量较好的栅氧化层，可以通过刻蚀等工艺，去除间隔层326和第二沟槽327中位于第三隔离结构321上方的部分第一氧化层322，从而暴露出相邻的沟道柱330和第二牺牲层325，以便于在第二沟槽327的侧壁上进行氧化处理形成栅氧化层。可选的，在去除间隔层326和部分第一氧化层322后，利用湿法清洗工艺，以去除第二沟槽327内部残留的污染物。In this embodiment of the present application, as shown in FIG. 11A , in order to form a gate oxide layer with a target thickness and better quality on the sidewall of thesecond trench 327 , thespacer layer 326 and the second trench can be removed by etching and other processes. A portion of thefirst oxide layer 322 in thetrench 327 above thethird isolation structure 321 is exposed, thereby exposing theadjacent channel pillars 330 and the secondsacrificial layer 325 to facilitate oxidation treatment on the sidewalls of the second trench 327 A gate oxide layer is formed. Optionally, after removing thespacer layer 326 and part of thefirst oxide layer 322 , a wet cleaning process is used to remove the remaining contaminants inside thesecond trench 327 .

如图11B所示，可以通过热氧化工艺，在第二沟槽327的侧壁形成目标厚度的栅氧化层341，热氧化工艺可以为蒸汽原位生成（In-Situ Steam Generated，ISSG）、快速热氧化工艺（Rapid Thermal Oxidation，RTO）等。值得注意的是，这里的栅氧化层341位于第二沟槽327中靠近相邻沟道柱330的侧壁上。而位于第二沟槽327中靠近第二牺牲层325的侧壁上的氧化层，则用于在后续去除第二牺牲层325的过程中，保护字线结构340。As shown in FIG. 11B , agate oxide layer 341 with a target thickness can be formed on the sidewall of thesecond trench 327 through a thermal oxidation process. The thermal oxidation process can be In-Situ Steam Generated (ISSG), rapid Thermal oxidation process (Rapid Thermal Oxidation, RTO) and so on. It is worth noting that thegate oxide layer 341 here is located on the sidewall of thesecond trench 327 close to theadjacent channel pillar 330 . The oxide layer located on the sidewall of thesecond trench 327 close to the secondsacrificial layer 325 is used to protect theword line structure 340 in the subsequent process of removing the secondsacrificial layer 325 .

如图11C所示，可以通过沉积等工艺，在具有栅氧化层341的第二沟槽327中填充导电材料，以形成字线。其中，导电材料包括但不限于钨、氮化钛、铜、银中的一种或多种。As shown in FIG. 11C , a conductive material may be filled in thesecond trenches 327 having thegate oxide layer 341 by processes such as deposition to form word lines. The conductive material includes, but is not limited to, one or more of tungsten, titanium nitride, copper, and silver.

如图11D所示，可以通过刻蚀等工艺，去除至少部分导电材料，以形成第三厚度的字线342，字线342的第三厚度小于第二沟槽327的深度，便于继续在字线342的上方形成栅保护层。As shown in FIG. 11D , at least part of the conductive material may be removed through processes such as etching to formword lines 342 with a third thickness. The third thickness of the word lines 342 is smaller than the depth of thesecond trenches 327 , which is convenient for continuing the word lines. A gate protection layer is formed above 342 .

如图11E所示，可以通过沉积等工艺，在字线342的上方填充绝缘材料，形成栅保护层343。可选的，这里的绝缘材料可以为氮化硅。栅保护层343可以防止字线342在靠近衬底300表面的一端发生漏电流现象，并在后续的工艺中保护字线342。As shown in FIG. 11E , an insulating material may be filled over the word lines 342 through a process such as deposition to form agate protection layer 343 . Optionally, the insulating material here can be silicon nitride. Thegate protection layer 343 can prevent theword line 342 from leaking current at one end close to the surface of thesubstrate 300 and protect theword line 342 in subsequent processes.

字线结构340包括上述栅氧化层341、字线342和栅保护层343。Theword line structure 340 includes thegate oxide layer 341 , theword line 342 and thegate protection layer 343 described above.

在一些实施例中，如图12A和图12B所示，所述去除所述第二牺牲层325，形成第三沟槽328，包括：In some embodiments, as shown in FIG. 12A and FIG. 12B , the removing the secondsacrificial layer 325 to form thethird trench 328 includes:

去除所述第二保护层3252；removing the secondprotective layer 3252;

去除所述第二牺牲层325，形成所述第三沟槽328。The secondsacrificial layer 325 is removed to form thethird trench 328 .

在本申请实施例中，如图12A所示，可以通过化学机械抛光等工艺，对衬底300表面进行处理，以去除第二保护层3252，和形成字线结构340后残留在衬底300表面的多余半导体材料，从而暴露出第二牺牲层325位于衬底300表面的一端，形成去除第二牺牲层325的开口。In this embodiment of the present application, as shown in FIG. 12A , the surface of thesubstrate 300 may be treated by a process such as chemical mechanical polishing, so as to remove the secondprotective layer 3252 , and theword line structure 340 remains on the surface of thesubstrate 300 after theword line structure 340 is formed. the excess semiconductor material, thereby exposing one end of the secondsacrificial layer 325 located on the surface of thesubstrate 300 , forming an opening for removing the secondsacrificial layer 325 .

如图12B所示，可以通过刻蚀等工艺，去除第二牺牲层325，形成第三沟槽328。第三沟槽328用于形成第二隔离结构350。As shown in FIG. 12B , the secondsacrificial layer 325 may be removed by a process such as etching to form athird trench 328 . Thethird trench 328 is used to form thesecond isolation structure 350 .

在一些实施例中，如图13所示，所述在所述第三沟槽328中形成所述第二隔离结构350，包括：In some embodiments, as shown in FIG. 13 , forming thesecond isolation structure 350 in thethird trench 328 includes:

在所述第三沟槽328中填充绝缘材料，形成中间具有空气间隙351（Air Gap）的所述第二隔离结构350。An insulating material is filled in thethird trench 328 to form thesecond isolation structure 350 with an air gap 351 (Air Gap) in the middle.

在本申请实施例中，如图13所示，可以通过沉积等工艺，在第三沟槽328中填充绝缘材料，并利用刻蚀等工艺，形成中间具有空气间隙351的第二隔离结构350。其中，空气间隙351在Z方向上的长度大于等于字线342的第三厚度。可选的，这里的绝缘材料可以为二氧化硅。空气间隙351可以提高第二隔离结构350的介电性能，进而改善半导体器件的性能。In this embodiment of the present application, as shown in FIG. 13 , thethird trench 328 may be filled with insulating material by processes such as deposition, and thesecond isolation structure 350 with anair gap 351 in the middle may be formed by processes such as etching. The length of theair gap 351 in the Z direction is greater than or equal to the third thickness of theword line 342 . Optionally, the insulating material here can be silicon dioxide. Theair gap 351 can improve the dielectric properties of thesecond isolation structure 350, thereby improving the performance of the semiconductor device.

在一些实施例中，如图14A和图14B所示，所述形成中间具有空气间隙351的所述第二隔离结构350之后，还包括：In some embodiments, as shown in FIG. 14A and FIG. 14B , after forming thesecond isolation structure 350 with anair gap 351 in the middle, the method further includes:

在所述第二隔离结构350靠近所述衬底300表面的一端形成第五沟槽352；Afifth trench 352 is formed at one end of thesecond isolation structure 350 close to the surface of thesubstrate 300;

在所述第五沟槽352中填充绝缘材料，形成第三保护层353。An insulating material is filled in thefifth trench 352 to form a thirdprotective layer 353 .

在本申请实施例中，如图14A所示，可以通过刻蚀等方法，在第二隔离结构350靠近衬底300表面的一端形成第五沟槽352。其中，第五沟槽352不与空气间隙351连通，第五沟槽352用于形成第三保护层353。In this embodiment of the present application, as shown in FIG. 14A , afifth trench 352 may be formed at one end of thesecond isolation structure 350 close to the surface of thesubstrate 300 by etching and other methods. Thefifth trench 352 is not communicated with theair gap 351 , and thefifth trench 352 is used to form the thirdprotective layer 353 .

如图14B所示，可以通过沉积等方法，在第五沟槽352中填充绝缘材料，形成第三保护层353。这里的绝缘材料可以为氮化硅等材料。第三保护层353可以保护空气间隙351，并提高第二隔离结构350的介电性能。由于在形成第三保护层353之后，衬底300的表面会存在不平整的现象，可选的，通过化学机械抛光工艺，对衬底300表面进行平坦化处理。As shown in FIG. 14B , an insulating material may be filled in thefifth trench 352 by means of deposition or the like to form a thirdprotective layer 353 . The insulating material here can be a material such as silicon nitride. The thirdprotective layer 353 may protect theair gap 351 and improve the dielectric properties of thesecond isolation structure 350 . Since the surface of thesubstrate 300 may be uneven after the thirdprotective layer 353 is formed, optionally, the surface of thesubstrate 300 may be planarized by a chemical mechanical polishing process.

在一些实施例中，如图15所示，所述方法还包括：In some embodiments, as shown in Figure 15, the method further includes:

对所述沟道柱330的第一端进行掺杂，形成晶体管的源极331；Doping the first end of thechannel pillar 330 to form thesource electrode 331 of the transistor;

对所述沟道柱330的第二端进行掺杂，形成所述晶体管的漏极332。Doping the second end of thechannel pillar 330 forms thedrain 332 of the transistor.

在本申请实施例中，如图15所示，可以通过离子注入（Implant）工艺，对沟道柱330的第一端和第二端进行掺杂，形成晶体管的源极331和漏极332。其中，第一端和第二端为沟道柱330在Z方向上相对的两端。可以理解的是，第一端可以为沟道柱330靠近衬底300表面的一端，也可以为沟道柱330靠近衬底300背面的一端。In this embodiment of the present application, as shown in FIG. 15 , the first end and the second end of thechannel pillar 330 may be doped through an ion implantation process to form thesource electrode 331 and thedrain electrode 332 of the transistor. The first end and the second end are opposite ends of thechannel pillar 330 in the Z direction. It can be understood that, the first end may be the end of thechannel pillar 330 close to the surface of thesubstrate 300 , or the end of thechannel pillar 330 close to the backside of thesubstrate 300 .

在一些实施例中，由于衬底300的表面存在氧化硅层、氮化硅层等残留材料，在形成晶体管的源极331和/或漏极332后，需要通过刻蚀、化学机械抛光等工艺去除残留物，以暴露出源极331和/或漏极332。In some embodiments, since residual materials such as a silicon oxide layer and a silicon nitride layer exist on the surface of thesubstrate 300, after thesource electrode 331 and/or thedrain electrode 332 of the transistor are formed, processes such as etching and chemical mechanical polishing are required. The residue is removed to exposesource 331 and/or drain 332 .

在一些实施例中，如图16所示，所述在所述字线结构340相邻的所述沟道柱330的表面形成存储结构360，包括：In some embodiments, as shown in FIG. 16 , forming astorage structure 360 on the surface of thechannel pillar 330 adjacent to theword line structure 340 includes:

在所述字线结构340相邻的所述源极331的表面上形成存储电容361。Astorage capacitor 361 is formed on the surface of thesource electrode 331 adjacent to theword line structure 340 .

在本申请实施例中，如图16所示，字线结构340相邻的源极331是指靠近栅氧化层341一侧的沟道柱330中的源极331。可以理解的是，存储电容361既可以形成在源极331的表面上，也可以形成在漏极332的表面上。存储电容361的一端与源极331或者漏极332连接，另一端接地。In the embodiment of the present application, as shown in FIG. 16 , thesource electrode 331 adjacent to theword line structure 340 refers to thesource electrode 331 in thechannel pillar 330 on the side close to thegate oxide layer 341 . It can be understood that, thestorage capacitor 361 may be formed on the surface of thesource electrode 331 or the surface of thedrain electrode 332 . One end of thestorage capacitor 361 is connected to thesource electrode 331 or thedrain electrode 332, and the other end is grounded.

在一些实施例中，如图17A和图17B所示，所述对所述沟道柱330的第二端进行掺杂，形成所述晶体管的漏极332，包括：In some embodiments, as shown in FIGS. 17A and 17B , doping the second end of thechannel pillar 330 to form thedrain 332 of the transistor includes:

对所述衬底300的背面进行减薄，直至暴露所述第三隔离结构321；thinning the backside of thesubstrate 300 until thethird isolation structure 321 is exposed;

对所述第三隔离结构321相邻的所述沟道柱330的第二端进行掺杂，形成所述晶体管的漏极332。Doping the second end of thechannel column 330 adjacent to thethird isolation structure 321 to form thedrain 332 of the transistor.

在本申请实施例中，如图17A所示，利用化学机械抛光等工艺对衬底300的背面进行减薄，直至暴露第三隔离结构321底部的第一保护层323，第一保护层323可以作为化学机械抛光工艺的停止层。In this embodiment of the present application, as shown in FIG. 17A , the backside of thesubstrate 300 is thinned by a process such as chemical mechanical polishing until the firstprotective layer 323 at the bottom of thethird isolation structure 321 is exposed. The firstprotective layer 323 may be As a stop layer for the chemical mechanical polishing process.

如图17B所示，通过离子注入（Implant）工艺，对第三隔离结构321相邻的沟道柱330的第二端进行掺杂，形成晶体管的漏极332，这里的第二端指的是沟道柱330靠近衬底300背面的一端。可以理解的是，也可以在沟道柱330靠近衬底300背面的一端形成晶体管的源极331。As shown in FIG. 17B , the second end of thechannel column 330 adjacent to thethird isolation structure 321 is doped through an ion implantation process to form thedrain 332 of the transistor, where the second end refers to One end of thechannel pillar 330 is close to the back surface of thesubstrate 300 . It can be understood that, thesource electrode 331 of the transistor can also be formed at one end of thechannel pillar 330 close to the back surface of thesubstrate 300 .

在一些实施例中，如图18所示，所述方法还包括：In some embodiments, as shown in Figure 18, the method further includes:

在所述衬底300的背面，形成连接所述晶体管的漏极332的位线370。On the backside of thesubstrate 300, abit line 370 is formed connecting thedrain 332 of the transistor.

在本申请实施例中，如图18所示，在衬底300的背面，形成连接晶体管的漏极332的位线370，位线370为导电材料。当字线342控制源极331和漏极332之间导通时，位线370对存储电容361进行数据的读取和写入操作。可以理解的是，位线370与存储电容361分别形成于衬底300相对的两个面上，从而简化了存储器内部的电路布局，降低了存储器制造的工艺难度。In this embodiment of the present application, as shown in FIG. 18 , on the backside of thesubstrate 300 , abit line 370 connecting thedrain electrode 332 of the transistor is formed, and thebit line 370 is made of conductive material. When theword line 342 controls the conduction between thesource electrode 331 and thedrain electrode 332 , thebit line 370 performs data read and write operations on thestorage capacitor 361 . It can be understood that thebit line 370 and thestorage capacitor 361 are respectively formed on two opposite surfaces of thesubstrate 300, thereby simplifying the circuit layout inside the memory and reducing the difficulty of the memory manufacturing process.

在一些实施例中，如图19所示，所述在所述衬底300的背面，形成连接所述晶体管的漏极332的位线370，包括：In some embodiments, as shown in FIG. 19 , forming abit line 370 connected to thedrain 332 of the transistor on the backside of thesubstrate 300 includes:

在所述漏极332表面形成位线接触结构371；forming a bitline contact structure 371 on the surface of thedrain electrode 332;

在所述位线接触结构371上形成所述位线370。Thebit line 370 is formed on the bitline contact structure 371 .

在本申请实施例中，如图19所示，在漏极332表面形成位线接触结构371，并在位线接触结构371上形成位线370。位线接触结构371为导电材料，用于连接漏极332和位线370。In this embodiment of the present application, as shown in FIG. 19 , a bitline contact structure 371 is formed on the surface of thedrain electrode 332 , and abit line 370 is formed on the bitline contact structure 371 . The bitline contact structure 371 is a conductive material for connecting thedrain electrode 332 and thebit line 370 .

如图20A和图20B所示，本申请实施例还提供了一种存储器40，所述存储器40包括：As shown in FIG. 20A and FIG. 20B , an embodiment of the present application further provides a memory 40, where the memory 40 includes:

衬底400；substrate 400;

位于所述衬底400中且沿第一方向延伸的若干相互平行的第一隔离结构410；所述第一方向平行于所述衬底400表面；所述第一隔离结构410的第一厚度小于或等于所述衬底400的厚度；A plurality of mutually parallelfirst isolation structures 410 located in thesubstrate 400 and extending along a first direction; the first direction is parallel to the surface of thesubstrate 400 ; the first thickness of thefirst isolation structures 410 is less than or equal to the thickness of thesubstrate 400;

位于所述衬底400中且沿第二方向延伸的若干相互平行的第一沟槽420；所述第二方向平行于所述衬底400表面且与所述第一方向垂直；所述第一沟槽420与所述第一隔离结构410将所述衬底划分为多个沟道柱430；A plurality of mutually parallelfirst trenches 420 located in thesubstrate 400 and extending along a second direction; the second direction is parallel to the surface of thesubstrate 400 and perpendicular to the first direction; the first direction Thetrench 420 and thefirst isolation structure 410 divide the substrate into a plurality ofchannel pillars 430;

位于所述第一沟槽420内的字线结构440和第二隔离结构450；其中，所述字线结构440和所述第二隔离结构450并列排布，且沿所述第一沟槽420的侧壁延伸；Theword line structure 440 and thesecond isolation structure 450 located in thefirst trench 420 ; wherein theword line structure 440 and thesecond isolation structure 450 are arranged side by side and along thefirst trench 420 extension of the side wall;

位于所述字线结构440相邻的所述沟道柱430的表面的存储结构460。Thestorage structure 460 is located on the surface of thechannel pillar 430 adjacent to theword line structure 440 .

在本申请实施例中，衬底400可以是硅（Si）、锗（Ge）等半导体材料。在一些实施例中，衬底400还可以是掺杂的，或者在衬底400中包括掺杂区域和未掺杂区域。衬底400中第一沟槽420所在的一面可以作为衬底400的表面，与衬底400的表面相背的一面可以作为衬底400的背面。In this embodiment of the present application, thesubstrate 400 may be a semiconductor material such as silicon (Si) or germanium (Ge). In some embodiments, thesubstrate 400 may also be doped, or include doped and undoped regions in thesubstrate 400 . The side of thesubstrate 400 where thefirst trenches 420 are located may serve as the surface of thesubstrate 400 , and the side opposite to the surface of thesubstrate 400 may serve as the backside of thesubstrate 400 .

如图20A所示，第一隔离结构410位于衬底400的表面，且沿着第一方向延伸。其中，第一方向平行于衬底400表面，与Y方向一致。第一隔离结构410在Z方向上的第一厚度小于或等于衬底400的厚度。图20A中未示出存储结构460。As shown in FIG. 20A , thefirst isolation structure 410 is located on the surface of thesubstrate 400 and extends along the first direction. The first direction is parallel to the surface of thesubstrate 400 and is consistent with the Y direction. The first thickness of thefirst isolation structure 410 in the Z direction is less than or equal to the thickness of thesubstrate 400 .Storage structure 460 is not shown in Figure 20A.

如图20A所示，第一沟槽420位于衬底400的表面，且沿着第二方向延伸。其中，第二方向平行于衬底400表面，与X方向一致，与第一方向垂直。如图20B所示，第一沟槽420在Z方向上的深度小于或等于衬底400的厚度。第一沟槽420与第一隔离结构410将衬底400划分为多个沟道柱430。沟道柱430的长度方向与Z方向一致，从而使得沟道柱430靠近衬底400表面和背面的两端，可以分别形成存储器中晶体管的源极和漏极，即存储器中的晶体管的方向垂直于衬底400表面。由此，垂直的晶体管占用面积更小，故单位面积上存储单元的密度更大。As shown in FIG. 20A , thefirst trench 420 is located on the surface of thesubstrate 400 and extends along the second direction. The second direction is parallel to the surface of thesubstrate 400, consistent with the X direction, and perpendicular to the first direction. As shown in FIG. 20B , the depth of thefirst trench 420 in the Z direction is less than or equal to the thickness of thesubstrate 400 . Thefirst trench 420 and thefirst isolation structure 410 divide thesubstrate 400 into a plurality ofchannel pillars 430 . The length direction of thechannel pillar 430 is consistent with the Z direction, so that thechannel pillar 430 is close to the two ends of the surface and the back side of thesubstrate 400, and the source and drain of the transistor in the memory can be respectively formed, that is, the direction of the transistor in the memory is vertical. on the surface of thesubstrate 400 . As a result, the vertical transistor occupies a smaller area, so the density of memory cells per unit area is higher.

如图20A所示，字线结构440与第二隔离结构450在Y方向上并列排布，并在X方向上沿着第一沟槽420的侧壁延伸。如图20B所示，字线结构440和第二隔离结构450分别覆盖第一沟槽420相对的两个侧壁，第二隔离结构450用于电隔离字线结构440和相邻晶体管中的沟道柱430。字线结构440可以包括字线、栅氧化层、栅保护层等结构，其中字线为导电材料，包括但不限于钨（W）、氮化钛（TiN）、铜（Cu）、银（Ag）中的一种或多种。第二隔离结构450的材料包括但不限于二氧化硅、旋涂绝缘介质、氮化硅、氮氧化硅中的一种或多种。As shown in FIG. 20A , theword line structures 440 and thesecond isolation structures 450 are arranged side by side in the Y direction and extend along the sidewalls of thefirst trenches 420 in the X direction. As shown in FIG. 20B , theword line structure 440 and thesecond isolation structure 450 respectively cover two opposite sidewalls of thefirst trench 420 , and thesecond isolation structure 450 is used to electrically isolate theword line structure 440 from the trenches in the adjacent transistors.Column 430. Theword line structure 440 may include structures such as word lines, gate oxide layers, gate protection layers, etc., wherein the word lines are conductive materials, including but not limited to tungsten (W), titanium nitride (TiN), copper (Cu), silver (Ag) ) one or more of. The material of thesecond isolation structure 450 includes, but is not limited to, one or more of silicon dioxide, spin-on insulating dielectric, silicon nitride, and silicon oxynitride.

如图20B所示，存储结构460位于字线结构440相邻的沟道柱430的表面。可以理解的是，存储结构460可以位于沟道柱430任意一端的表面上，与晶体管的源极或漏极连接，沟道柱430的另一端则可以连接位线等结构。在随机存取存储器中，存储结构460可以是电容。由此，存储器中源极和漏极所连接的不同结构可以分别设计在衬底400相对的两个面上，从而简化了存储器内部的电路布局，降低了存储器制造的工艺难度。As shown in FIG. 20B , thestorage structure 460 is located on the surface of thechannel pillar 430 adjacent to theword line structure 440 . It can be understood that thestorage structure 460 may be located on the surface of either end of thechannel pillar 430 and connected to the source or drain of the transistor, and the other end of thechannel pillar 430 may be connected to a structure such as a bit line. In random access memory,storage structure 460 may be a capacitor. Therefore, different structures connected to the source electrode and the drain electrode in the memory can be designed on two opposite sides of thesubstrate 400 respectively, thereby simplifying the circuit layout inside the memory and reducing the process difficulty of memory manufacturing.

在一些实施例中，如图21所示，所述存储器还包括：In some embodiments, as shown in Figure 21, the memory further includes:

位于所述第一沟槽420底部的具有第二厚度的第三隔离结构421；所述第二厚度小于所述第一沟槽420的深度；所述字线结构440和所述第二隔离结构450位于所述第三隔离结构421上方。Athird isolation structure 421 with a second thickness at the bottom of thefirst trench 420; the second thickness is smaller than the depth of thefirst trench 420; theword line structure 440 and thesecond isolation structure 450 is located above thethird isolation structure 421 .

在本申请实施例中，第三隔离结构421位于第一沟槽420的底部，第三隔离结构421在Z方向上的厚度小于第一沟槽420的深度。字线结构440和第二隔离结构450位于第三隔离结构421的上方，第三隔离结构421用于防止字线结构440在第一沟槽420的底部发生漏电流现象。第三隔离结构421的材料包括但不限于二氧化硅、旋涂绝缘介质、氮化硅、氮氧化硅中的一种或多种。In the embodiment of the present application, thethird isolation structure 421 is located at the bottom of thefirst trench 420 , and the thickness of thethird isolation structure 421 in the Z direction is smaller than the depth of thefirst trench 420 . Theword line structure 440 and thesecond isolation structure 450 are located above thethird isolation structure 421 , and thethird isolation structure 421 is used to prevent theword line structure 440 from leaking current at the bottom of thefirst trench 420 . The material of thethird isolation structure 421 includes, but is not limited to, one or more of silicon dioxide, spin-on insulating dielectric, silicon nitride, and silicon oxynitride.

在一些实施例中，如图22所示，所述存储器还包括：In some embodiments, as shown in Figure 22, the memory further includes:

第一保护层423，位于所述第三隔离结构421和所述第一沟槽420的内壁之间；a firstprotective layer 423, located between thethird isolation structure 421 and the inner wall of thefirst trench 420;

第一氧化层422，位于所述第一保护层423和所述第一沟槽420的内壁之间。Thefirst oxide layer 422 is located between the firstprotective layer 423 and the inner wall of thefirst trench 420 .

在本申请实施例中，第一保护层423位于第三隔离结构421和第一沟槽420的内壁之间，第一保护层423可以为氮化硅等材料；第一氧化层422位于第一保护层423和第一沟槽420的内壁之间，第一氧化层422可以为线形氧化层。第一保护层423和第一氧化层422可以提高第三隔离结构421的介电性能，防止字线结构440在第一沟槽420的底部发生漏电流现象。In the embodiment of the present application, the firstprotective layer 423 is located between thethird isolation structure 421 and the inner wall of thefirst trench 420 , and the firstprotective layer 423 can be made of materials such as silicon nitride; thefirst oxide layer 422 is located in the first Between theprotective layer 423 and the inner wall of thefirst trench 420, thefirst oxide layer 422 may be a linear oxide layer. The firstprotective layer 423 and thefirst oxide layer 422 can improve the dielectric properties of thethird isolation structure 421 and prevent theword line structure 440 from leaking current at the bottom of thefirst trench 420 .

在一些实施例中，如图23所示，所述字线结构440包括：In some embodiments, as shown in FIG. 23, theword line structure 440 includes:

字线442，位于所述第三隔离结构421上方；word lines 442 located above thethird isolation structure 421;

栅氧化层441，位于所述字线442和相邻的所述沟道柱430之间；Thegate oxide layer 441 is located between theword line 442 and theadjacent channel pillar 430;

栅保护层443，位于所述字线442上方。Thegate protection layer 443 is located above the word lines 442 .

在本申请实施例中，字线结构440包括：字线442、栅氧化层441和栅保护层443。其中，字线442位于第三隔离结构421上方，字线442的顶端低于衬底400表面，字线442为导电材料，包括但不限于钨、氮化钛、铜、银中的一种或多种。In the embodiment of the present application, theword line structure 440 includes: aword line 442 , agate oxide layer 441 and agate protection layer 443 . Theword line 442 is located above thethird isolation structure 421, the top of theword line 442 is lower than the surface of thesubstrate 400, and theword line 442 is a conductive material, including but not limited to one of tungsten, titanium nitride, copper, and silver or variety.

栅氧化层441位于字线442和相邻的沟道柱430之间，栅氧化层441可以通过对第一沟槽420的侧壁进行热氧化工艺形成。Thegate oxide layer 441 is located between theword line 442 and theadjacent channel pillar 430 , and thegate oxide layer 441 may be formed by thermally oxidizing the sidewall of thefirst trench 420 .

栅保护层443覆盖于字线442上方，栅保护层443可以为氮化硅材料，用于防止字线442在靠近衬底400表面的一端发生漏电流现象。Thegate protection layer 443 covers theword line 442 , and thegate protection layer 443 may be made of silicon nitride material to prevent leakage current from occurring at one end of theword line 442 close to the surface of thesubstrate 400 .

在一些实施例中，如图24所示，所述第二隔离结构450中具有空气间隙451。In some embodiments, as shown in FIG. 24 , thesecond isolation structure 450 has anair gap 451 therein.

在本申请实施例中，第二隔离结构450中具有空气间隙451。其中，第二隔离结构450可以为二氧化硅等绝缘材料；空气间隙451在Z方向上的长度大于等于字线442在Z方向上的长度，空气间隙451可以提高第二隔离结构450的介电性能，进而改善半导体器件的性能。In the embodiment of the present application, thesecond isolation structure 450 has anair gap 451 therein. Thesecond isolation structure 450 can be an insulating material such as silicon dioxide; the length of theair gap 451 in the Z direction is greater than or equal to the length of theword line 442 in the Z direction, and theair gap 451 can improve the dielectric of thesecond isolation structure 450 performance, thereby improving the performance of semiconductor devices.

在一些实施例中，如图25所示，所述第二隔离结构450还包括：In some embodiments, as shown in FIG. 25 , thesecond isolation structure 450 further includes:

第三保护层453，位于空气间隙451上方。The thirdprotective layer 453 is located above theair gap 451 .

在本申请实施例中，第三保护层453位于空气间隙451上方，第三保护层453可以为氮化硅等绝缘材料，用于保护空气间隙451，并提高第二隔离结构450的介电性能。In the embodiment of the present application, the thirdprotective layer 453 is located above theair gap 451 , and the thirdprotective layer 453 may be an insulating material such as silicon nitride, which is used to protect theair gap 451 and improve the dielectric performance of thesecond isolation structure 450 .

在一些实施例中，如图26所示，所述沟道柱430包括：In some embodiments, as shown in FIG. 26 , thechannel pillar 430 includes:

位于所述沟道柱430第一端的晶体管的源极431；thesource electrode 431 of the transistor located at the first end of thechannel pillar 430;

位于所述沟道柱430第二端的所述晶体管的漏极432。Thedrain 432 of the transistor is located at the second end of thechannel pillar 430 .

在本申请实施例中，晶体管的源极431和漏极432分别位于沟道柱430在Z方向上相对的两端。可以理解的是，晶体管的源极431既可以位于沟道柱430靠近衬底400表面的一端，也可以为沟道柱430靠近衬底400背面的一端。In the embodiment of the present application, thesource electrode 431 and thedrain electrode 432 of the transistor are located at opposite ends of thechannel pillar 430 in the Z direction, respectively. It can be understood that thesource electrode 431 of the transistor can be located either at the end of thechannel pillar 430 close to the surface of thesubstrate 400 , or at the end of thechannel pillar 430 close to the backside of thesubstrate 400 .

在一些实施例中，如图27所示，所述存储结构460包括：In some embodiments, as shown in FIG. 27, thestorage structure 460 includes:

存储电容461，位于所述源极431的表面且连接所述源极431。Thestorage capacitor 461 is located on the surface of thesource electrode 431 and connected to thesource electrode 431 .

在本申请实施例中，存储电容461位于源极431的表面且连接所述源极431，用于存储写入的数据。可以理解的是，存储电容461既可以位于源极431的表面上，也可以位于漏极432的表面上。存储电容461的一端与源极431或者漏极432连接，另一端接地。In the embodiment of the present application, thestorage capacitor 461 is located on the surface of thesource electrode 431 and connected to thesource electrode 431 for storing written data. It can be understood that thestorage capacitor 461 may be located on the surface of thesource electrode 431 or the surface of thedrain electrode 432 . One end of thestorage capacitor 461 is connected to thesource electrode 431 or thedrain electrode 432, and the other end is grounded.

在一些实施例中，如图28A至图28C所示，所述存储电容461包括但不限于：杯形（Cup-Type）电容、筒形（Cylinder-Type）电容、柱形（Pillar-Type）电容。In some embodiments, as shown in FIGS. 28A to 28C , thestorage capacitor 461 includes, but is not limited to, a Cup-Type capacitor, a Cylinder-Type capacitor, and a Pillar-Type capacitor. capacitance.

在本申请实施例中，如图28A所示为杯形电容的结构示意图，其中下电极4611为向上开口的杯形，上电极4612位于下电极4611的内侧。In the embodiment of the present application, FIG. 28A is a schematic structural diagram of a cup-shaped capacitor, wherein thelower electrode 4611 is a cup-shaped opening upward, and theupper electrode 4612 is located inside thelower electrode 4611 .

如图28B所示为筒形电容的结构示意图，其中下电极4611为向上开口的杯形；上电极4612包围下电极4611的内侧和外侧。28B is a schematic structural diagram of a cylindrical capacitor, wherein thelower electrode 4611 is a cup-shaped opening upward; theupper electrode 4612 surrounds the inner and outer sides of thelower electrode 4611 .

如图28C所示为柱形电容的结构示意图，其中下电极4611为柱形，上电极4612包围下电极4611且向下开口。FIG. 28C is a schematic structural diagram of a columnar capacitor, wherein thelower electrode 4611 is columnar, and theupper electrode 4612 surrounds thelower electrode 4611 and opens downward.

上电极4612和下电极4611均为导电材料，包括金属和金属氮化物材料，如钨、镍、钽、氮化钽和氮化钛中的一种或多种；电容介质层4613为高K介电材料，如氧化钛、氧化锆、氧化铪等。Theupper electrode 4612 and thelower electrode 4611 are both conductive materials, including metals and metal nitride materials, such as one or more of tungsten, nickel, tantalum, tantalum nitride and titanium nitride; thecapacitor dielectric layer 4613 is a high-K dielectric. Electrical materials, such as titanium oxide, zirconium oxide, hafnium oxide, etc.

在一些实施例中，如图29A和图29B所示，所述存储电容461在衬底400表面上的排布包括但不限于：正方形排布、六边形排布。In some embodiments, as shown in FIGS. 29A and 29B , the arrangement of thestorage capacitors 461 on the surface of thesubstrate 400 includes, but is not limited to, a square arrangement and a hexagonal arrangement.

在本申请实施例中，如图29A所示为存储电容461在衬底400表面上呈正方形排布的示意图，各个存储电容461在X和Y方向上的间距可以与各个沟道柱430的间距相等。存储电容461在XY平面上的中心可以相对沟道柱430的中心有一定的偏移。In this embodiment of the present application, as shown in FIG. 29A , a schematic diagram of thestorage capacitors 461 arranged in a square on the surface of thesubstrate 400 is shown. equal. The center of thestorage capacitor 461 on the XY plane may have a certain offset relative to the center of thechannel pillar 430 .

如图29B所示为存储电容461在衬底400表面上呈六边形排布的示意图，相邻的两行存储电容461可以沿X方向错位排布。FIG. 29B is a schematic diagram showing that thestorage capacitors 461 are arranged in a hexagonal shape on the surface of thesubstrate 400 , and thestorage capacitors 461 in two adjacent rows may be staggered along the X direction.

在一些实施例中，存储电容461在Z方向上的截面形状可以为椭圆形，且存储电容461的椭圆截面的轴线与X方向不平行，以减小电容占用的面积。In some embodiments, the cross-sectional shape of thestorage capacitor 461 in the Z direction may be an ellipse, and the axis of the elliptical cross-section of thestorage capacitor 461 is not parallel to the X direction, so as to reduce the area occupied by the capacitor.

在一些实施例中，如图30所示，所述存储器还包括：In some embodiments, as shown in Figure 30, the memory further includes:

位线470，位于所述衬底400的背面，所述位线470连接所述漏极432。Abit line 470 is located on the backside of thesubstrate 400 , and thebit line 470 is connected to thedrain electrode 432 .

在本申请实施例中，位线470位于衬底400的背面，且连接至漏极432，位线470为导电材料。当字线442控制源极431和漏极432之间导通时，位线470对存储电容461进行数据的读取和写入操作。可以理解的是，位线470与存储电容461分别形成于衬底400相对的两个面上，从而简化了存储器内部的电路布局，降低了存储器制造的工艺难度。In the embodiment of the present application, thebit line 470 is located on the backside of thesubstrate 400 and is connected to thedrain electrode 432 , and thebit line 470 is made of conductive material. When theword line 442 controls the conduction between thesource electrode 431 and thedrain electrode 432 , thebit line 470 performs data read and write operations on thestorage capacitor 461 . It can be understood that thebit line 470 and thestorage capacitor 461 are respectively formed on two opposite sides of thesubstrate 400 , thereby simplifying the circuit layout inside the memory and reducing the difficulty of manufacturing the memory.

在一些实施例中，如图31所示，所述存储器还包括：In some embodiments, as shown in Figure 31, the memory further includes:

位线接触结构471，位于所述漏极432的表面，所述位线接触结构471连接所述漏极432和所述位线470。The bitline contact structure 471 is located on the surface of thedrain electrode 432 , and the bitline contact structure 471 connects thedrain electrode 432 and thebit line 470 .

在本申请实施例中，位线接触结构471位于漏极432的表面，位线接触结构471为导电材料，且连接位线470和漏极432。In the embodiment of the present application, the bitline contact structure 471 is located on the surface of thedrain electrode 432 , the bitline contact structure 471 is a conductive material, and connects thebit line 470 and thedrain electrode 432 .

需要说明的是，本申请所提供的实施例，可以应用于随机存取存储器（RAM）、动态随机存取存储器（DRAM）、铁电随机存取存储器（FRAM）、相变随机存取存储器（PCRAM）、磁性随机存取存储器（MRAM）等。It should be noted that the embodiments provided in this application can be applied to random access memory (RAM), dynamic random access memory (DRAM), ferroelectric random access memory (FRAM), phase change random access memory ( PCRAM), Magnetic Random Access Memory (MRAM), etc.

需要说明的是，本申请所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。It should be noted that, the features disclosed in several method or device embodiments provided in this application may be combined arbitrarily under the condition of no conflict to obtain new method embodiments or device embodiments.

以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。The above are only specific embodiments of the present application, but the protection scope of the present application is not limited to this. should be covered within the scope of protection of this application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims (24)

1. A method of manufacturing a memory, the method comprising:

providing a substrate;

forming a plurality of first isolation structures which extend along a first direction and are parallel to each other in the substrate; the first direction is parallel to the substrate surface; a first thickness of the first isolation structure is less than a thickness of the substrate;

forming a plurality of first grooves which extend along a second direction and are parallel to each other in the substrate; the second direction is parallel to the substrate surface and perpendicular to the first direction; the first trench and the first isolation structure divide the substrate into a plurality of channel columns; wherein the first trench has opposing first and second sidewalls;

forming a word line structure and a second isolation structure in the first trench; the word line structures and the second isolation structures are arranged in parallel and extend along the side wall of the first groove;

forming a storage structure on the surface of the channel column adjacent to the word line structure;

wherein, the forming of the word line structure and the second isolation structure in the first trench includes:

forming a first sacrificial layer covering the first sidewall and a second sacrificial layer covering the second sidewall;

removing the first sacrificial layer, and forming a word line structure at the position where the first sacrificial layer is removed;

and removing the second sacrificial layer, and forming a second isolation structure at the position where the second sacrificial layer is removed.

2. The method of claim 1, further comprising:

forming a third isolation structure with a second thickness at the bottom of the first trench; the second thickness is less than the depth of the first trench; the word line structure and the second isolation structure are formed over the third isolation structure.

3. The method of claim 2, further comprising:

forming a first oxide layer covering the inner wall of the first groove;

forming a first protective layer covering the first oxide layer;

the forming a third isolation structure of a second thickness at the bottom of the first trench includes:

and forming the third isolation structure in the first groove with the inner wall covered with the first oxide layer and the first protective layer.

4. The method of claim 3, wherein forming the third isolation structure in the first trench having the inner wall covered with the first oxide layer and the first protection layer comprises:

filling an insulating material in the first groove with the inner wall covered with the first oxide layer and the first protective layer;

removing at least part of the insulating material to enable the bottom of the first trench to remain a second thickness of the insulating material so as to form a third isolation structure;

and removing the first protective layer above the third isolation structure.

5. The method of claim 4, wherein forming a word line structure and a second isolation structure within the first trench comprises:

forming a first sacrificial layer covering a first sidewall of the first trench and a second sacrificial layer covering a second sidewall of the first trench over the third isolation structure;

forming a spacer layer between the first sacrificial layer and the second sacrificial layer;

removing the first sacrificial layer to form a second groove;

forming the word line structure in the second trench;

removing the second sacrificial layer to form a third groove;

forming the second isolation structure in the third trench.

6. The method of claim 5, wherein forming a first sacrificial layer covering a first sidewall of the first trench and forming a second sacrificial layer covering a second sidewall of the first trench comprises:

forming a sacrificial layer covering the inner wall of the first groove in the first groove;

and removing part of the sacrificial layer on the upper surface of the third isolation structure to form the first sacrificial layer and the second sacrificial layer which are separated from each other.

7. The method of claim 5, wherein the removing the first sacrificial layer to form a second trench comprises:

forming a fourth groove on one end, close to the surface of the substrate, of the second sacrificial layer;

forming a second protective layer in the fourth trench to cover the second sacrificial layer;

and removing the first sacrificial layer to form the second groove.

8. The method of claim 7, wherein the removing the second sacrificial layer to form a third trench comprises:

removing the second protective layer;

and removing the second sacrificial layer to form the third groove.

9. The method of claim 5, wherein forming the word line structure in the second trench comprises:

removing the first oxide layer in the spacing layer and the second groove;

forming a gate oxide layer on the side wall of the second groove;

filling a conductive material in the second trench;

removing at least part of the conductive material to form a word line with a third thickness, wherein the third thickness is smaller than the depth of the second groove;

filling an insulating material on the word line in the second groove to form a gate protection layer; wherein the word line structure includes the gate oxide layer, the word line, and the gate protection layer.

10. The method of claim 5, wherein said forming the second isolation structure in the third trench comprises:

and filling an insulating material in the third groove to form the second isolation structure with an air gap in the middle.

11. The method of claim 2, further comprising:

doping the first end of the channel column to form a source electrode of the transistor;

and doping the second end of the channel column to form the drain electrode of the transistor.

12. The method of claim 11, wherein forming a storage structure on a surface of the channel pillar adjacent to the word line structure comprises:

and forming a storage capacitor on the surface of the source electrode adjacent to the word line structure.

13. The method of claim 11, wherein doping the second end of the channel pillar to form a drain of the transistor comprises:

thinning the back surface of the substrate until the third isolation structure is exposed;

and doping the second end of the channel column adjacent to the third isolation structure to form the drain electrode of the transistor.

14. The method of claim 13, further comprising:

and forming a bit line connected with the drain electrode of the transistor on the back surface of the substrate.

15. The method of claim 14, wherein forming a bit line connecting the drain of the transistor on the back side of the substrate comprises:

forming a bit line contact structure on the surface of the drain electrode;

the bit line is formed on the bit line contact structure.

16. A memory, comprising:

a substrate;

the first isolation structures are located in the substrate and extend along a first direction; the first direction is parallel to the substrate surface; a first thickness of the first isolation structure is less than or equal to a thickness of the substrate;

a plurality of first grooves which are parallel to each other and are positioned in the substrate and extend along a second direction; the second direction is parallel to the substrate surface and perpendicular to the first direction; the first trench and the first isolation structure divide the substrate into a plurality of channel columns; wherein the first trench has opposing first and second sidewalls;

the word line structure and the second isolation structure are positioned in the first groove; the word line structures and the second isolation structures are arranged in parallel and extend along the side wall of the first groove;

a memory structure located on a surface of the channel pillar adjacent to the word line structure;

wherein the forming of the word line structure and the second isolation structure comprises:

forming a first sacrificial layer covering the first sidewall and a second sacrificial layer covering the second sidewall;

removing the first sacrificial layer, and forming the word line structure at the position of removing the first sacrificial layer;

and removing the second sacrificial layer, and forming the second isolation structure at the position where the second sacrificial layer is removed.

17. The memory of claim 16, further comprising:

a third isolation structure having a second thickness at the bottom of the first trench; the second thickness is less than the depth of the first trench; the word line structure and the second isolation structure are located above the third isolation structure.

18. The memory of claim 17, further comprising:

a first protective layer between the third isolation structure and an inner wall of the first trench;

and the first oxidation layer is positioned between the first protection layer and the inner wall of the first groove.

19. The memory of claim 17, wherein the word line structure comprises:

word lines over the third isolation structures;

the gate oxide layer is positioned between the word line and the adjacent channel column;

and the gate protection layer is positioned above the word line.

20. The memory of claim 17, wherein the second isolation structure has an air gap therein.

21. The memory of claim 16, wherein the channel pillar comprises:

a source of a transistor at a first end of the channel pillar;

a drain of the transistor at the channel pillar second end.

22. The memory of claim 21, wherein the storage structure comprises:

and the storage capacitor is positioned on the surface of the source electrode and connected with the source electrode.

23. The memory of claim 21, further comprising:

and the bit line is positioned on the back surface of the substrate and is connected with the drain electrode.

24. The memory as recited in claim 23, further comprising:

and the bit line contact structure is positioned on the surface of the drain electrode and is connected with the drain electrode and the bit line.

Images