CN114203736A - Array substrate and preparation method thereof, and display panel - Google Patents

Abstract

The application provides an array substrate, a preparation method thereof and a display panel; according to the array substrate, the active layers at least comprise the first active layer and the second active layer, different doping factors can be doped into the active layers in sequence when the active layers are formed, and the active layers at least comprise the first active layer and the second active layer are formed, so that the doping times of the active layers are reduced, ion implantation and extra exposure processes are reduced, and the preparation efficiency of the array substrate is improved.

Description

Array substrate, preparation method thereof and display panel

Technical Field

The application relates to the technical field of display, in particular to an array substrate, a preparation method of the array substrate and a display panel.

Background

In order to improve the display effect and reduce the power consumption of the display device, a low-temperature polysilicon technology is adopted to replace an amorphous silicon technology. However, when the low temperature polysilicon thin film transistor is manufactured, since the active layer of the low temperature polysilicon thin film transistor needs to be doped for many times, an ion implantation process needs to be performed by an ion implantation machine, and an additional exposure process is needed, so that the manufacturing process of the display device has more process flows and higher cost.

Therefore, the prior display device has the technical problem of low preparation efficiency caused by the need of doping polycrystalline silicon for multiple times in the preparation process.

Disclosure of Invention

The embodiment of the application provides an array substrate, a preparation method thereof and a display panel, which are used for relieving the technical problem of low preparation efficiency caused by the fact that polycrystalline silicon needs to be doped for many times in the preparation process of the existing display device.

An embodiment of the present application provides an array substrate, which includes:

a substrate;

a light shielding layer disposed on one side of the substrate;

the buffer layer is arranged on one side, far away from the substrate, of the light shielding layer;

the active layer is arranged on one side, far away from the light shielding layer, of the buffer layer;

the gate insulating layer is arranged on one side, far away from the buffer layer, of the active layer;

the grid electrode layer is arranged on one side, far away from the active layer, of the grid electrode insulating layer;

the interlayer insulating layer is arranged on one side of the grid electrode layer, which is far away from the grid electrode insulating layer;

the source drain electrode layer is arranged on one side, far away from the grid layer, of the interlayer insulating layer;

the active layer at least comprises a first active layer and a second active layer, and the doping factors of the first active layer and the second active layer are different.

In some embodiments, the doping factor of the first active layer comprises boron particles and phosphorus particles of a first mass, the doping factor of the second active layer comprises phosphorus particles of a second mass, the first mass is less than the second mass, the first active layer comprises a channel region and a lightly doped region, and the second active layer comprises an ohmic contact region.

In some embodiments, the active layer further comprises a third active layer having a different doping factor than the first active layer, the third active layer having a different doping factor than the second active layer.

In some embodiments, the first active layer is disposed on a side of the third active layer away from the gate insulating layer, and the second active layer is disposed between the first active layer and the third active layer.

In some embodiments, the doping factor of the first active layer comprises boron particles, the doping factor of the second active layer comprises phosphorus particles of a third mass, the doping factor of the third active layer comprises phosphorus particles of a fourth mass, the third mass is less than the fourth mass, the first active layer comprises a channel region, the second active layer comprises a lightly doped region, and the third active layer comprises an ohmic contact region.

In some embodiments, the second active layer is symmetrically disposed about the channel region, and the second active layer is disconnected at the channel region.

In some embodiments, the third active layer is symmetric about a region of the lightly doped region and the channel region, and the third active layer is disconnected at the lightly doped region and the channel region.

In some embodiments, the thickness of the first active layer is equal to the thickness of the second active layer, which is equal to the thickness of the third active layer.

Meanwhile, an embodiment of the present application provides a method for manufacturing an array substrate, including:

providing a substrate, and sequentially forming a light shielding layer and a buffer layer on the substrate;

depositing amorphous silicon on the buffer layer, and sequentially introducing boron fluoride, phosphine of a fifth mass and phosphine of a sixth mass in the amorphous silicon film forming process to form an active layer at least comprising a first active layer and a second active layer; the fifth mass is less than the sixth mass;

defining an active layer area and a channel area by using a semi-transparent photomask, and covering the active layer area by using a photoresist; the thickness of the photoresistance positioned in the channel region is smaller than that of the photoresistance positioned in the non-channel region;

etching the photoresist and the active layer by dry etching and photoresist ashing processes to obtain a pattern of the active layer, and stripping the photoresist;

and sequentially forming a gate insulating layer, a gate electrode layer, an interlayer insulating layer and a source drain electrode layer on the active layer.

Meanwhile, an embodiment of the present application provides a display panel, which includes an array substrate, the array substrate includes:

a substrate;

a light shielding layer disposed on one side of the substrate;

the buffer layer is arranged on one side, far away from the substrate, of the light shielding layer;

the active layer is arranged on one side, far away from the light shielding layer, of the buffer layer;

the gate insulating layer is arranged on one side, far away from the buffer layer, of the active layer;

the grid electrode layer is arranged on one side, far away from the active layer, of the grid electrode insulating layer;

the interlayer insulating layer is arranged on one side of the grid electrode layer, which is far away from the grid electrode insulating layer;

the source drain electrode layer is arranged on one side, far away from the grid layer, of the interlayer insulating layer;

the active layer at least comprises a first active layer and a second active layer, and the doping factors of the first active layer and the second active layer are different.

Has the advantages that: the application provides an array substrate, a preparation method thereof and a display panel; the array substrate comprises a substrate, a shading layer, a buffer layer, an active layer, a grid insulating layer, a grid layer, an interlayer insulating layer and a source drain layer, wherein the shading layer is arranged on one side of the substrate, the buffer layer is arranged on one side, far away from the substrate, of the shading layer, the active layer is arranged on one side, far away from the shading layer, of the buffer layer, the grid insulating layer is arranged on one side, far away from the active layer, of the active layer, the grid layer is arranged on one side, far away from the active layer, of the active layer, the interlayer insulating layer is arranged on one side, far away from the grid insulating layer, of the grid layer, the source drain layer is arranged on one side, far away from the grid layer, of the interlayer insulating layer, the active layer at least comprises a first active layer and a second active layer, and doping factors of the first active layer and the second active layer are different. According to the method, the active layer at least comprises the first active layer and the second active layer, different doping factors can be doped into the active layer in sequence when the active layer is formed, and the active layer at least comprises the first active layer and the second active layer is formed, so that the doping times of the active layer are reduced, ion implantation and extra exposure processes are reduced, and the preparation efficiency of the array substrate is improved.

Drawings

The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.

Fig. 1 is a schematic view of a conventional array substrate according to an embodiment of the present disclosure.

Fig. 2 is a schematic view of an array substrate according to an embodiment of the present disclosure.

Fig. 3 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present disclosure.

Fig. 4 is a first schematic view of an array substrate corresponding to each step of the array substrate preparation method provided in the embodiment of the present application.

Fig. 5 is a second schematic view of the array substrate corresponding to each step of the array substrate preparation method provided in the embodiment of the present application.

Fig. 6 is a third schematic view of the array substrate corresponding to each step of the array substrate preparation method provided in the embodiment of the present application.

Fig. 7 is a fourth schematic view of the array substrate corresponding to each step of the array substrate preparation method provided in the embodiment of the present application.

Fig. 8 is a schematic view of a display panel according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

As shown in fig. 1, the conventional array substrate includes asubstrate 11, alight shielding metal 12, abuffer material 13, apolysilicon layer 14, agate insulating layer 15, agate layer 16, aninterlayer insulating layer 17, and a source/drain layer 18, the polysilicon layer includes achannel region 143, a lightly dopedregion 142 and anohmic contact region 141, in the preparation process of the prior array substrate, after a polycrystalline silicon layer is exposed to form a pattern, the polycrystalline silicon layer is doped for many times in an ion implanter, namely, boron doping, a small amount of phosphorus doping and a large amount of phosphorus doping are respectively carried out to form a channel region, a lightly doped region and an ohmic contact region, so that an ion implanter and additional exposure are required in the preparation process of the array substrate, the cost is increased, and the additional exposure and multiple ion implantation processes result in more process flows, lower preparation efficiency of the display device, therefore, the prior display device has the technical problem of low preparation efficiency caused by the need of doping polycrystalline silicon for multiple times in the preparation process.

In view of the above technical problems, embodiments of the present application provide an array substrate, a method for manufacturing the array substrate, and a display panel, so as to alleviate the above technical problems.

As shown in fig. 2, an embodiment of the present application provides an array substrate, where thearray substrate 2 includes:

asubstrate 211;

a light-shielding layer 212 provided on thesubstrate 211;

abuffer layer 213 disposed on a side of the light-shielding layer 212 away from thesubstrate 211;

anactive layer 214 disposed on a side of thebuffer layer 213 away from the light-shielding layer 212;

agate insulating layer 215 disposed on a side of theactive layer 214 away from thebuffer layer 213;

agate electrode layer 216 disposed on a side of thegate insulating layer 215 away from theactive layer 214;

an interlayer insulatinglayer 217 disposed on a side of thegate electrode layer 216 away from thegate insulating layer 215;

asource drain layer 218 disposed on a side of the interlayer insulatinglayer 217 away from thegate layer 216;

theactive layer 214 includes at least a firstactive layer 214a and a secondactive layer 214b, and the doping factors of the firstactive layer 214a and the secondactive layer 214b are different.

The embodiment of the application provides an array substrate, and the array substrate enables an active layer to at least comprise a first active layer and a second active layer, so that different doping factors can be doped into the active layer in sequence when the active layer is formed, the active layer at least comprising the first active layer and the second active layer is formed, the doping times of the active layer are reduced, ion implantation and additional exposure processes are reduced, and the preparation efficiency of the array substrate is improved.

It should be noted that, in the active layer in the embodiment of the present application, at least the first active layer and the second active layer may sequentially add doping particles in the active layer process, without causing a problem of mixing different particles, and multiple times of doping are not required, so that multiple layers of film layers with different doping factors may be correspondingly formed, and the active layer having at least the first active layer and the second active layer is obtained, thereby reducing the number of times of doping, reducing ion implantation and additional exposure processes, and improving the preparation efficiency of the array substrate.

It should be noted that the doping factors in the embodiments of the present application include the element and the mass of the element, that is, when either of the two doping factors is different, it is determined that the two doping factors are different, for example, the doping particles of the first active layer are phosphorus particles with the mass of 1, and the doping particles of the second active layer are phosphorus particles with the mass of 2, and even if the doping elements of the first active layer and the second active layer are both phosphorus, the doping factors of the first active layer and the second active layer are different due to the different mass of the doped phosphorus. Similarly, when the doped elements have the same mass but different doped elements, or the doped elements and the doped elements have different masses, the doping factors of the two active layers are different.

In one embodiment, the doping factor of the first active layer includes boron particles and phosphorus particles of a first mass, the doping factor of the second active layer includes phosphorus particles of a second mass, the first mass is less than the second mass, the first active layer includes a channel region and a lightly doped region, and the second active layer includes an ohmic contact region. The first active layer is doped with boron particles and phosphorus particles of a first mass, and the second active layer is doped with phosphorus particles of a second mass, so that when the second active layer is formed, phosphorus-containing substances are directly introduced to realize doping of the second active layer, and phosphorus doping is performed without using additional exposure and ion implantation modes, so that the exposure and ion implantation steps are reduced, and the preparation efficiency of the array substrate is improved.

Specifically, the particles referred to in the embodiments of the present application include ions, but the embodiments of the present application are not limited thereto, and when it is necessary to dope molecules or atoms, the particles may also refer to molecules or atoms.

Specifically, the second active layer is arranged on one side, far away from the buffer layer, of the first active layer, the second active layer is connected with the source drain layer, the lightly doped region of the first active layer is in contact with the second active layer, the lightly doped region of the first active layer exceeds the arrangement of the second active layer, the channel region is located between the lightly doped regions on two sides, the second active layer is arranged on the lightly doped regions, the channel region is arranged between the lightly doped regions on two sides, when voltage is input to the source drain, the voltage can sequentially pass through the ohmic contact region, the lightly doped region and the channel region, the source drain is conducted, and conduction of the thin film transistor is achieved.

The problem that the ion implantation process is still needed when the active layer is provided with two layers is solved. In one embodiment, as shown in fig. 2, the active layer further includes a thirdactive layer 214c, the thirdactive layer 214c has a doping factor different from that of the firstactive layer 214a, and the thirdactive layer 214c has a doping factor different from that of the secondactive layer 214 b. By making the doping factors of the first active layer, the second active layer and the third active layer different, when the active layers are formed, the doping factor of the first active layer, the doping factor of the second active layer and the doping factor of the third active layer can be sequentially introduced, so that the first active layer, the second active layer and the third active layer can be sequentially formed, and the first active layer, the second active layer and the third active layer are doped without using ion implantation and extra exposure process, thereby improving the preparation efficiency of the array substrate. And because the doping factors are introduced in sequence, the ions in the first active layer, the second active layer and the third active layer are not mixed, and the performance of each doping area is not influenced.

In one embodiment, as shown in fig. 2, the firstactive layer 214a is disposed on a side of the thirdactive layer 214c away from thegate insulating layer 215, and the secondactive layer 214b is disposed between the firstactive layer 214a and the thirdactive layer 214 c. By sequentially arranging the first active layer, the second active layer and the third active layer, particles can be sequentially doped in the first active layer, the second active layer and the third active layer, so that the doping of the first active layer, the second active layer and the third active layer is completed, and the doped particles of the first active layer, the second active layer and the third active layer are prevented from being mixed.

In one embodiment, the doping factor of the first active layer comprises boron particles, the doping factor of the second active layer comprises phosphorus particles of a third mass, the doping factor of the third active layer comprises phosphorus particles of a fourth mass, the third mass is less than the fourth mass, the first active layer comprises a channel region, the second active layer comprises a lightly doped region, and the third active layer comprises an ohmic contact region. By doping the first active layer, the second active layer and the third active layer with boron particles, phosphorus particles of a third mass and phosphorus particles of a fourth mass in sequence, the active layer with a channel region, a lightly doped region and an ohmic contact region can be formed in sequence, so that doping of each region of the active layer is completed, multiple times of doping are not needed, and the preparation efficiency of the array substrate is improved.

Specifically, the third active layer is connected with the source drain layer and the source drain layer through the third active layer, so that the third active layer is connected with the source drain layer, and when voltage is applied, the thin film transistor is switched on through the first active layer, the second active layer and the third active layer.

In one embodiment, the second active layer is symmetrically disposed about the channel region, and the second active layer is disconnected at the channel region. The second active layer is symmetrically arranged relative to the channel region, and the active layer is disconnected, so that when voltage is applied, the second active layer is not directly conducted, and the performance of the thin film transistor is affected.

In one embodiment, the third active layer is symmetrical with respect to a region formed by the lightly doped region and the channel region, and the third active layer is disconnected between the lightly doped region and the channel region, so that voltage is not directly conducted from the first active layer by disconnecting the third active layer between the lightly doped region and the channel region, which results in that performance of the thin film transistor is affected, and the lightly doped region and the channel region can be exposed, so that the thin film transistor operates normally.

In one embodiment, the thickness of the first active layer is equal to that of the second active layer, and the thickness of the second active layer is equal to that of the third active layer, that is, when the first active layer, the second active layer and the third active layer are provided, the thicknesses of the active layers including the channel region, the lightly doped region and the ohmic contact region can still be made the same, and the performance of the thin film transistor is not affected.

Specifically, the thickness of the first active layer ranges from 10 nm to 100 nm, the thickness of the second active layer ranges from 10 nm to 100 nm, and the thickness of the third active layer ranges from 10 nm to 100 nm.

In one embodiment, as shown in fig. 2, thearray substrate 2 further includes aplanarization layer 219, afirst electrode layer 220, apassivation layer 221, and asecond electrode layer 222.

Meanwhile, as shown in fig. 3, an embodiment of the present application provides a method for manufacturing an array substrate, including:

s1, providing a substrate, and sequentially forming a light shielding layer and a buffer layer on the substrate; the structure of the array substrate corresponding to this step is shown in fig. 4 (a);

s2, depositing amorphous silicon on the buffer layer, and sequentially introducing boron fluoride, phosphine of a fifth mass and phosphine of a sixth mass in the amorphous silicon film forming process to form an active layer at least comprising a first active layer and a second active layer; the fifth mass is less than the sixth mass; the structure of the array substrate corresponding to this step is shown in fig. 4 (a);

s3, defining an active layer region and a channel region by using a semi-transparent mask, and covering the active layer region with aphotoresist 31; the thickness of thephotoresist 31 in the channel region is smaller than that in the non-channel region; the structure of the array substrate corresponding to this step is shown in fig. 4 (b);

s4, etching the photoresist and the active layer through dry etching and photoresist ashing processes to obtain the active layer pattern, and stripping the photoresist; the structure of the array substrate corresponding to this step is shown in fig. 5 to 7;

s5, sequentially forming a gate insulating layer, a gate layer, an interlayer insulating layer and a source drain layer on the active layer; the structure of the array substrate corresponding to this step is shown in fig. 2.

The embodiment of the application provides a method for manufacturing an array substrate, and the method for manufacturing the array substrate includes the steps of doping different doping factors into an active layer in sequence when the active layer is formed, so that the active layer at least comprising a first active layer and a second active layer is formed, the doping times of the active layer are reduced, ion implantation and extra exposure processes are reduced, and the manufacturing efficiency of the array substrate is improved.

Specifically, the steps of etching the photoresist and the active layer through the dry etching and photoresist ashing processes to obtain the pattern of the active layer, and stripping the photoresist include:

removing the active layer in the area without the photoresist coverage by using a dry etching process; the structure of the array substrate corresponding to this step is shown in fig. 5 (a);

thinning the photoresist by using a photoresist ashing process, and leaking out the channel region; the structure of the array substrate corresponding to this step is shown in fig. 5 (b);

etching the third active layer of the channel region by using a dry etching process; the structure of the array substrate corresponding to this step is shown in fig. 6 (a);

the photoresist is retreated by using a photoresist ashing process, and the retreated length of the photoresist is equal to the length of a lightly doped region required by the thin film transistor; the structure of the array substrate corresponding to this step is shown in fig. 6 (b);

etching the second active layer of the channel region and the third active layer of the lightly doped region by using a dry etching process; the structure of the array substrate corresponding to this step is shown in fig. 7 (a);

stripping the photoresist; the structure of the array substrate corresponding to this step is shown in fig. 7 (b).

As can be known from the preparation method of the array substrate provided in the embodiment of the present application, when the active layer is formed, boron fluoride, phosphine of a fifth mass, and phosphine of a sixth mass are sequentially introduced to form a first active layer doped with boron particles, a second active layer doped with phosphorus particles, and a third active layer doped with phosphorus particles, where the phosphorus particles doped with the second active layer are less than the phosphorus particles doped with the third active layer, so that doping of the active layer is completed, ion implantation and exposure processes are not required, and a channel region, a lightly doped region, and an ohmic contact region are formed by etching, so that the thin film transistor operates normally.

Meanwhile, as shown in fig. 8, an embodiment of the present application provides a display panel including an array substrate, the array substrate including:

asubstrate 211;

a light-shielding layer 212 provided on thesubstrate 211;

abuffer layer 213 disposed on a side of the light-shielding layer 212 away from thesubstrate 211;

anactive layer 214 disposed on a side of thebuffer layer 213 away from the light-shielding layer 212;

agate insulating layer 215 disposed on a side of theactive layer 214 away from thebuffer layer 213;

agate electrode layer 216 disposed on a side of thegate insulating layer 215 away from theactive layer 214;

an interlayer insulatinglayer 217 disposed on a side of thegate electrode layer 216 away from thegate insulating layer 215;

asource drain layer 218 disposed on a side of the interlayer insulatinglayer 217 away from thegate layer 216;

theactive layer 214 includes at least a firstactive layer 214a and a secondactive layer 214b, and the doping factors of the firstactive layer 214a and the secondactive layer 214b are different.

The embodiment of the application provides a display panel, which comprises an array substrate, wherein the array substrate enables an active layer to at least comprise a first active layer and a second active layer, different doping factors can be doped into the active layer in sequence when the active layer is formed, the active layer at least comprising the first active layer and the second active layer is formed, the doping times of the active layer are reduced, ion implantation and additional exposure processes are reduced, and the preparation efficiency of the array substrate is improved.

In one embodiment, as shown in fig. 8, the display panel is an OLED (Organic Light-Emitting Diode) display panel, and further includes apixel electrode layer 411, apixel defining layer 412, a Light-Emittingmaterial layer 413, acommon electrode layer 414, and anencapsulation layer 415.

In one embodiment, the display panel further includes a liquid crystal display panel, and the liquid crystal display panel further includes a liquid crystal layer and a color film substrate.

According to the above embodiment:

the embodiment of the application provides an array substrate, a preparation method thereof and a display panel; the array substrate comprises a substrate, a shading layer, a buffer layer, an active layer, a grid insulating layer, a grid layer, an interlayer insulating layer and a source drain layer, wherein the shading layer is arranged on one side of the substrate, the buffer layer is arranged on one side, far away from the substrate, of the shading layer, the active layer is arranged on one side, far away from the shading layer, of the buffer layer, the grid insulating layer is arranged on one side, far away from the active layer, of the active layer, the grid layer is arranged on one side, far away from the active layer, of the active layer, the interlayer insulating layer is arranged on one side, far away from the grid insulating layer, of the grid layer, the source drain layer is arranged on one side, far away from the grid layer, of the interlayer insulating layer, the active layer at least comprises a first active layer and a second active layer, and doping factors of the first active layer and the second active layer are different. According to the method, the active layer at least comprises the first active layer and the second active layer, different doping factors can be doped into the active layer in sequence when the active layer is formed, and the active layer at least comprises the first active layer and the second active layer is formed, so that the doping times of the active layer are reduced, ion implantation and extra exposure processes are reduced, and the preparation efficiency of the array substrate is improved.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

The array substrate, the manufacturing method thereof, and the display panel provided in the embodiments of the present application are described in detail above, and specific examples are applied in the present application to explain the principle and the implementation manner of the present application, and the description of the above embodiments is only used to help understanding the technical solution and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims (10)

1. An array substrate, comprising:

a substrate;

a light shielding layer disposed on one side of the substrate;

the buffer layer is arranged on one side, far away from the substrate, of the light shielding layer;

the active layer is arranged on one side, far away from the light shielding layer, of the buffer layer;

the gate insulating layer is arranged on one side, far away from the buffer layer, of the active layer;

the grid electrode layer is arranged on one side, far away from the active layer, of the grid electrode insulating layer;

the interlayer insulating layer is arranged on one side of the grid electrode layer, which is far away from the grid electrode insulating layer;

the source drain electrode layer is arranged on one side, far away from the grid layer, of the interlayer insulating layer;

the active layer at least comprises a first active layer and a second active layer, and the doping factors of the first active layer and the second active layer are different.

2. The array substrate of claim 1, wherein the doping factor of the first active layer comprises boron particles and a first mass of phosphorus particles, the doping factor of the second active layer comprises a second mass of phosphorus particles, the first mass is less than the second mass, the first active layer comprises a channel region and a lightly doped region, and the second active layer comprises an ohmic contact region.

3. The array substrate of claim 1, wherein the active layers further comprise a third active layer, the third active layer having a doping factor different from the first active layer, the third active layer having a doping factor different from the second active layer.

4. The array substrate of claim 3, wherein the first active layer is disposed on a side of the third active layer away from the gate insulating layer, and the second active layer is disposed between the first active layer and the third active layer.

5. The array substrate of claim 4, wherein the doping factor of the first active layer comprises boron particles, the doping factor of the second active layer comprises phosphorus particles of a third mass, the doping factor of the third active layer comprises phosphorus particles of a fourth mass, the third mass is less than the fourth mass, the first active layer comprises a channel region, the second active layer comprises a lightly doped region, and the third active layer comprises an ohmic contact region.

6. The array substrate of claim 5, wherein the second active layer is symmetrically disposed about the channel region, and the second active layer is disconnected at the channel region.

7. The array substrate of claim 5, wherein the third active layer is symmetrical with respect to a region consisting of the lightly doped region and the channel region, and the third active layer is disconnected at the lightly doped region and the channel region.

8. The array substrate of claim 3, wherein a thickness of the first active layer is equal to a thickness of the second active layer, and wherein a thickness of the second active layer is equal to a thickness of the third active layer.

9. A preparation method of an array substrate is characterized by comprising the following steps:

providing a substrate, and sequentially forming a light shielding layer and a buffer layer on the substrate;

depositing amorphous silicon on the buffer layer, and sequentially introducing boron fluoride, phosphine of a fifth mass and phosphine of a sixth mass in the amorphous silicon film forming process to form an active layer at least comprising a first active layer and a second active layer; the fifth mass is less than the sixth mass;

defining an active layer area and a channel area by using a semi-transparent photomask, and covering the active layer area by using a photoresist; the thickness of the photoresistance positioned in the channel region is smaller than that of the photoresistance positioned in the non-channel region;

etching the photoresist and the active layer by dry etching and photoresist ashing processes to obtain a pattern of the active layer, and stripping the photoresist;

and sequentially forming a gate insulating layer, a gate electrode layer, an interlayer insulating layer and a source drain electrode layer on the active layer.

10. A display panel, comprising an array substrate, the array substrate comprising:

a substrate;

a light shielding layer disposed on one side of the substrate;

the buffer layer is arranged on one side, far away from the substrate, of the light shielding layer;

the active layer is arranged on one side, far away from the light shielding layer, of the buffer layer;

the gate insulating layer is arranged on one side, far away from the buffer layer, of the active layer;

the grid electrode layer is arranged on one side, far away from the active layer, of the grid electrode insulating layer;

the interlayer insulating layer is arranged on one side of the grid electrode layer, which is far away from the grid electrode insulating layer;

the source drain electrode layer is arranged on one side, far away from the grid layer, of the interlayer insulating layer;

the active layer at least comprises a first active layer and a second active layer, and the doping factors of the first active layer and the second active layer are different.

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