CN114203568A - Multilayer stack memory and manufacturing method thereof - Google Patents

Abstract

The invention discloses a multilayer stack memory and a manufacturing method thereof, wherein the manufacturing method of the multilayer stack memory comprises the following steps: preparing a memory chip and a substrate, and stacking the memory chip on the substrate by micro-bump welding in a hot-press bonding mode; another layer of memory chips are welded and stacked on the previous layer of memory chips through the micro-bumps to form a stacked module; filling plastic packaging materials or underfill between the substrate and the memory chips and between the upper and lower adjacent memory chips, and performing plastic packaging on the stacked module; and dividing the stacked module after plastic packaging into independent packages. The manufacturing method of the multilayer stack memory can effectively reduce the production cost of the multilayer stack memory.

Description

Multilayer stack memory and manufacturing method thereof

Technical Field

The invention relates to the technical field of semiconductor manufacturing, in particular to a method for manufacturing a multilayer stacked memory and the multilayer stacked memory manufactured by the method.

Background

With the development of cloud computing and mobile interconnection, the demand of servers such as data centers is increasing dramatically. High-end servers require high capacity, large bandwidth, and low power consumption for memory devices. To meet this demand, companies have successively introduced multi-layer storage packaging products based on three-dimensional stacking technology. As shown in fig. 1, the multi-layer memory package stacked module vertically interconnects a plurality of memory chips 2 (DRAMs) by using Through-Silicon vias 13(TSV, Through Silicon Via), and performs data interaction with the outside Through the substrate 1 at the bottom layer, and since the TSV 13 has the advantages of high density and short vertical interconnection distance, the data transmission speed is greatly increased.

Currently, a Thermal Compression Bond (TCB) process is used for stacking a multilayer chip of a high bandwidth memory, and themicrobumps 3 are connected with theback pads 14 of the chip and theback pads 14 of the chip are connected with the throughsilicon vias 13 of the chip by rapid heating. At present, the composition of themicro bump 3 is mainly a copper-tin structure, and the main composition of the chipback bonding pad 14 is a nickel-gold structure. The final stacked module is protected by a molding compound 5(EMC), and finally the package solder balls 7 are connected with the outside. Because the distance between themicro bumps 3 is small, in order to prevent short circuit between themicro bumps 3, thenon-conductive adhesive 15 is generally filled between themicro bumps 3 to play a role in protection. At present, two using modes of thenon-conductive adhesive 15 exist, one mode is shown in fig. 2, thenon-conductive adhesive 15 is made into a film structure, is coated on the lower surface of thememory chip 2 in advance, covers the micro-bumps 3, and then is welded with an upper chip and a lower chip; alternatively, as shown in fig. 3, anon-conductive adhesive 15 is applied to the upper surface of thememory chip 2, and then theupper memory chip 2 is bonded to the lower wafer through the non-conductive adhesive.

Such non-conductive adhesive materials are expensive because thenon-conductive adhesive 15 is applied before the bonding of themicro bumps 3, and thenon-conductive adhesive 15 on the bonding surface needs to be completely removed from the bonding interface during the bonding process, which has extremely high requirements on the characteristics of the non-conductive adhesive materials. Moreover, thenon-conductive adhesive 15 needs to be completely extruded, and no bubbles need to be generated, so that the requirements on a hot-press welding bonding process and equipment are high, the process debugging difficulty is high, and the cost is increased.

Disclosure of Invention

The invention aims to provide a method for manufacturing a multilayer stack memory, which can effectively reduce the production cost of the multilayer stack memory.

In order to achieve the above object, the present invention provides a method for manufacturing a multi-layer stacked memory, comprising the following steps:

s10, preparing a memory chip and a substrate, and stacking the memory chip on the substrate by micro-bump welding in a hot-press bonding mode;

s20, stacking another layer of memory chip on the previous layer of memory chip by micro-bump welding in a thermal compression bonding mode;

s30, if the number of layers of the memory chips stacked on the substrate is equal to the set number of layers, the memory chips are stacked to form a stacked module, and then the step S40 is executed; if the number of layers of the memory chips stacked on the substrate is less than the set number of layers, executing step S20;

s40, mounting a heat sink on the upper surface of the memory chip at the top layer of the stacked module;

s50, placing the stacked module provided with the radiating fins into a plastic package mold, filling plastic package materials into the plastic package mold, and carrying out plastic package on the stacked module, wherein the plastic package materials are filled between the substrate and the memory chips and between the upper and lower adjacent memory chips, and the upper surfaces of the radiating fins are positioned on the outer sides of the plastic package materials;

and S60, dividing the stacked module after being molded into independent packages.

Preferably, in the step S40, a heat dissipation adhesive is applied between the heat dissipation plate and the top surface of the top memory chip.

Further preferably, the material of the heat sink is copper or stainless steel.

Preferably, the plastic package material filled into the plastic package mold is a plastic package underfill material.

Preferably, in step S10, when the lower surface of the substrate has solder balls, the substrate is firstly attached to a temporary carrier by a temporary bonding adhesive, and then the memory chips are stacked on the substrate; in step S60, the temporary bonding adhesive and the temporary carrier are removed first, and then the stack module after plastic package is divided into independent packages;

in the step S10, when there are no solder balls on the lower surface of the substrate, in the step S60, the solder balls are first attached to the lower surface of the substrate, and then the stack module after being molded is divided into individual packages.

In order to achieve the above object, the present invention further provides a method for manufacturing a multi-layer stacked memory, comprising the following steps:

s10, preparing a memory chip and a substrate, and stacking the memory chip on the substrate by micro-bump welding in a hot-press bonding mode;

s20, stacking another layer of memory chip on the previous layer of memory chip by micro-bump welding in a thermal compression bonding mode;

s30, if the number of layers of the memory chips stacked on the substrate is equal to the set number of layers, the memory chips are stacked to form a stacked module, and then the step S40 is executed; if the number of layers of the memory chips stacked on the substrate is less than the set number of layers, executing step S20;

s40, placing a silica gel partition plate on the substrate, wherein the silica gel partition plate surrounds all stacked memory chips of each stacked module, and the lower surface of the silica gel partition plate is tightly attached to the upper surface of the substrate;

s50, filling underfill in the silica gel partition plate, filling underfill between the substrate and the memory chips and between the upper and lower adjacent memory chips, and heating and curing;

s60, removing the silica gel partition plate, putting the stacking module with the silica gel partition plate removed into a plastic package mold, filling plastic package materials into the plastic package mold, and carrying out plastic package on the stacking module;

and S70, dividing the stacked module after being molded into independent packages.

Preferably, in step S40, the top surface of the silicone partition board is lower than the top surface of the top memory chip.

Preferably, in step S40, the distance between the silicone partition and the memory chip of the stacked module is 0.3-0.5 mm.

Preferably, in the step S40, a pressing plate is placed on the silicone partition board; in the step S60, the pressing plate is removed simultaneously with or before the silicone partition is removed.

Further preferably, the pressing plate is a stainless steel plate.

Preferably, in step S60, after the stack module is molded, the molding compound is ground, so that the upper surface of the uppermost memory chip of the stack module is exposed from the molding compound.

Preferably, in step S10, when the lower surface of the substrate has solder balls, the substrate is firstly attached to a temporary carrier by a temporary bonding adhesive, and then the memory chips are stacked on the substrate; in step S70, the temporary bonding adhesive and the temporary carrier are removed first, and then the stack module after plastic package is divided into independent packages;

in the step S10, when there are no solder balls on the lower surface of the substrate, in the step S70, the solder balls are first attached to the lower surface of the substrate, and then the stack module after being molded is divided into individual packages.

The manufacturing method of the multilayer stacked memory is different from the prior art in that the manufacturing method of the multilayer stacked memory provided by the invention changes the production process that the non-conductive adhesive is coated on the memory chip and then the hot-pressing bonding is carried out in the prior art into the production process that the hot-pressing bonding is carried out on the memory chip, and then the underfill or the plastic packaging material is filled between the upper and lower adjacent memory chips and between the memory chip and the substrate, namely, the manufacturing method effectively reduces the manufacturing difficulty of the multilayer stacked memory chip by the way of stacking and then filling, and simultaneously uses the traditional underfill or plastic packaging material to replace the pre-coating of the non-conductive adhesive, so that the cost of the manufacturing material is reduced. Therefore, the manufacturing method of the multilayer stack memory can effectively reduce the production cost of the multilayer stack memory.

Another object of the present invention is to provide a multi-layer stacked memory having advantages of low production cost.

In order to achieve the purpose, the technical scheme of the invention is realized as follows:

a multilayer stack memory comprises a plastic package material and a stack module located in the plastic package material, wherein the stack module comprises a substrate and memory chips located on the substrate, the memory chips are stacked on the substrate in a hot-press bonding mode, when the memory chips are in multiple layers, the memory chips on the upper layer are stacked on the memory chips on the lower layer in the hot-press bonding mode, and bottom filling glue or plastic package materials are filled between the substrate and the memory chips and between the memory chips which are adjacent up and down.

According to the multilayer stacked memory provided by the invention, the underfill or the plastic package material is used for replacing the existing non-conductive adhesive to be filled between the substrate and the memory chips and between the vertically adjacent memory chips so as to prevent short circuit between the micro bumps, and the underfill or the plastic package material is lower in price compared with the non-conductive adhesive, so that the multilayer stacked memory provided by the invention has the advantage of low production cost.

Drawings

FIG. 1 is a schematic diagram of a conventional multi-level stacked memory;

FIG. 2 is a schematic diagram of a structure in which the lower surface of a memory chip is pre-coated with a non-conductive adhesive;

FIG. 3 is a schematic diagram of a structure in which the upper surface of a memory chip is pre-coated with a non-conductive adhesive;

FIG. 4 is a flow chart of a method for fabricating a multi-level stack memory according to an embodiment of the invention;

fig. 5 is a schematic structural view of a memory chip stacked on a substrate;

FIG. 6 is a schematic structural diagram of a stacked module formed by stacking 4 memory chips on a substrate;

fig. 7 is a schematic view of the stacked module of fig. 6 with heat sinks mounted thereon;

FIG. 8 is a schematic view of the stacked module underfill encapsulant of FIG. 7;

FIG. 9 is a schematic view of the stack mold of FIG. 7 after molding;

fig. 10 is a schematic structural view of the individual packages separated after solder balls are attached to the plastic stack mold shown in fig. 9;

FIG. 11 is a flow chart of a method for fabricating a multi-level stacked memory according to another embodiment of the present invention;

fig. 12 is a schematic view of a structure in which memory chips are stacked on a substrate with a temporary bonding paste and a temporary carrier under the substrate;

fig. 13 is a schematic structural diagram of a stacked module formed by stacking 4 layers of memory chips on a substrate with temporary bonding glue and a temporary carrier plate under the substrate;

FIG. 14 is a schematic view of the stacked module of FIG. 13 with silicone spacers and compression plates disposed thereon;

FIG. 15 is a schematic view of a plurality of the stacked modules and silicone spacers of FIG. 14, without a platen;

FIG. 16 is a schematic view of the underfill dispensing configuration of the stacked module of FIG. 14;

FIG. 17 is a schematic view of the silicone septum and platen of FIG. 16 with the septum and platen removed;

FIG. 18 is a schematic view of the stack module of FIG. 17 after molding;

FIG. 19 is a schematic view of the stacked module of FIG. 17 after molding, wherein the top surface of the top memory chip is exposed from the molding;

fig. 20 is a schematic structural view of the stacked module shown in fig. 19, after removing the temporary bonding adhesive and the temporary carrier, and dividing the stacked module into individual packages;

in the drawings, the components represented by the respective reference numerals are listed below:

1-a substrate; 2-a memory chip; 3-micro convex points; 4-a heat sink; 5-plastic packaging material; 6-heat dissipation glue; 7-solder balls; 8-temporary bonding glue; 9-temporary carrier plate; 10-a silica gel spacer; 11-bottom filling glue; 12-a platen; 13-through silicon vias; 14-a pad; 15-non-conductive glue; 16-a barrier film; 20-stacking the modules.

Detailed Description

The principles and features of this invention are described below in conjunction with the following drawings, which are set forth by way of illustration only and are not intended to limit the scope of the invention.

The main object of the present invention is to provide a method for manufacturing a multi-layer stacked memory without applying a non-conductive adhesive before a thermocompression bonding process, which can reduce the difficulty of the thermocompression bonding process, and at the same time, can reduce the overall production cost by using a low-cost material.

In one embodiment of the present invention, as shown in fig. 4, a method for fabricating a multi-layer stacked memory includes the following steps:

s10, preparing amemory chip 2 and a substrate 1, and welding and stacking thememory chip 2 on the substrate 1 through amicro bump 3 in a hot-press bonding mode; as shown in fig. 5, throughsilicon vias 13 are disposed on thememory chip 2, and themicro bumps 3 on the lower surface of thememory chip 2 are soldered to thepads 14 on the substrate 1, where the substrate 1 may be a Buffer chip. The silicon throughhole 13 is formed by punching a vertical through hole on a chip and filling metal, an I/O signal on a pad on the upper surface (front surface) of the chip induces amicro bump 3 on the lower surface (back surface) of the chip, and the vertical interconnection between chips in each layer is realized by welding themicro bump 3 and thepad 14.

S20, stacking another layer ofmemory chips 2 on the upper layer ofmemory chips 2 by micro-bump welding in a hot-press bonding mode; wherein the upper layer ofmemory chips 2 refers to thememory chips 2 located below the other layer ofmemory chips 2. As shown in fig. 6, themicro bumps 3 of theupper memory chip 2 are soldered to thepads 14 of thelower memory chip 2.

S30, if the number of layers of thememory chips 2 stacked on the substrate 1 is equal to the set number of layers, thememory chips 2 are completely stacked to form the stackedmodule 20, and then the step S40 is executed; if the number of layers of thememory chips 2 stacked on the substrate 1 is less than the set number of layers, performing step S20; wherein the set number of layers is determined according to the number of layers of the multi-layer stacked memory design, such as 2 layers, 3 layers, 4 layers or more.

S40, mounting a heat sink 4 on the top surface of thememory chip 2 on the top layer of the stackedmodule 20; the material of the heat sink 4 may be selected from various materials having high thermal conductivity, such as copper (Cu) and stainless steel (SUS). In order to further improve the heat dissipation effect of the heat sink 4, it is preferable to apply the heat dissipation paste 6 between the heat sink 4 and the top surface of thetop memory chip 2, that is, before the heat sink 4 is mounted, the heat dissipation paste 6 is applied to the top surface of thetop memory chip 2 or the heat dissipation paste 6 is applied to the bottom surface of the heat sink 4.

S50, the stacking module provided with the radiating fins 4 is placed into a plastic package mold, the top of the stacking module is provided with an isolatingfilm 16, as shown in fig. 8,plastic package materials 5 are filled into the plastic package mold, the stacking module is subjected to plastic package, theplastic package materials 5 are filled between the substrate 1 and thestorage chips 2 and between theupper storage chip 2 and thelower storage chip 2 which are adjacent to each other, as shown in fig. 9, after the plastic package is completed, the isolatingfilm 16 placed at the top of the stacking module is removed, and the upper surface of the radiating fins 4 of the stackingmodule 20 after the plastic package is positioned outside theplastic package materials 5. Theplastic molding material 5 filled into the plastic molding mold is preferably a plastic Underfill (MUF). It should be noted that fig. 5-10 only show the process of filling themolding compound 5 with one stacked module, but in actual production, a plurality ofmemory chips 2 are generally stacked on the substrate 1 at the same time to form a plurality of stacked modules, and the distribution of the plurality of stacked modules is shown in fig. 15.

And S60, dividing the stacked module after being molded into independent packages.

In the above embodiment, if the lower surface of the substrate 1 has the solder balls 7 before thememory chips 2 are stacked, that is, in the step S10, when the lower surface of the substrate 1 has the solder balls 7, the substrate 1 is first adhered to thetemporary carrier board 9 by thetemporary bonding adhesive 8, and then thememory chips 2 are stacked on the substrate 1; and in the step S60, the temporary bonding glue and the temporary carrier are removed first, and then the stack module after being molded is divided into independent packages.

In the above embodiment, if the solder balls 7 are not mounted on the lower surface of the substrate 1 before thememory chips 2 are stacked, that is, when the solder balls 7 are not mounted on the lower surface of the substrate 1 in the step S10, the solder balls 7 are first mounted on the lower surface of the substrate 1 in the step S60, and then the stacked module after being molded is divided into individual packages.

The method for manufacturing the multilayer stacked memory provided in the above embodiment changes the production method that the Non-conductive Film 15 (NCF) is coated on thememory chip 2 and then the thermocompression bonding is performed in the prior art into the production method that the thermocompression bonding is performed on thememory chip 2 and then the bottom molding compound is filled between the upper and loweradjacent memory chips 2 and between thememory chip 2 and the substrate 1, that is, the method for manufacturing the multilayer stacked memory chip effectively reduces the difficulty in manufacturing the multilayer stacked memory chip by stacking and then filling, and uses the conventional molding compound to replace the precoating of the Non-conductive Film, so that the cost of the manufacturing material is reduced.

In the above embodiment, by adopting the exposed heat sink structure, that is, the back surface of the heat sink 4 is exposed outside themolding compound 5, the flow of themolding compound 5 can be improved during plastic packaging, the filling capability of themolding compound 5 can be improved, and the process of first stacking and then filling can be realized.

In another embodiment of the present invention, as shown in fig. 11, a method for fabricating a multi-layer stacked memory includes the following steps:

s10, preparing amemory chip 2 and a substrate 1, and welding and stacking thememory chip 2 on the substrate 1 through amicro bump 3 in a hot-press bonding mode; as shown in fig. 12 and 13, through-silicon vias 13 are formed in thememory chip 2, and themicro bumps 3 on the lower surface of thememory chip 2 are soldered to thepads 14 on the substrate 1, where the substrate 1 may be a Buffer chip. The silicon throughhole 13 is formed by punching a vertical through hole on a chip and filling metal, an I/O signal on a pad on the upper surface (front surface) of the chip induces amicro bump 3 on the lower surface (back surface) of the chip, and the vertical interconnection between chips in each layer is realized by welding themicro bump 3 and thepad 14.

S20, stacking another layer ofmemory chips 2 on the upper layer ofmemory chips 2 by micro-bump welding in a hot-press bonding mode; wherein the upper layer ofmemory chips 2 refers to thememory chips 2 located below the other layer ofmemory chips 2. As shown in fig. 13, themicro bumps 3 of theupper memory chip 2 are soldered to thepads 14 of thelower memory chip 2.

S30, if the number of layers of thememory chips 2 stacked on the substrate 1 is equal to the set number of layers, thememory chips 2 are completely stacked to form the stackedmodule 20, and then the step S40 is executed; if the number of layers of thememory chips 2 stacked on the substrate 1 is less than the set number of layers, performing step S20; wherein the set number of layers is determined according to the number of layers of the multi-layer stacked memory design, such as 2 layers, 3 layers, 4 layers or more. A stackedmodule 20 having 4 layers ofmemory chips 2 is shown in fig. 13.

S40, placing asilicone partition 10 on the substrate 1, wherein thesilicone partition 10 surrounds all thestacked memory chips 2 of each of the stackedmodules 20, that is, as shown in fig. 14, thesilicone partition 10 is disposed around four layers ofmemory chips 2 of the stackedmodules 20. The lower surface of the silicagel partition board 10 is closely attached to the upper surface of the substrate 1. Thesilica gel spacer 10 is a spacer made of silica gel. In order to ensure that the lower surface of the silicagel partition board 10 can be sufficiently attached to the substrate 1, a pressingboard 12 is preferably disposed on the silicagel partition board 10, and thepressing board 12 may be made of various appropriate materials with relatively large mass, preferably a stainless steel board. The height of the upper surface of thesilicone partition plate 10 should be higher than the lower surface of thetop memory chip 2, and preferably, the height of the upper surface of thesilicone partition plate 10 is lower than the upper surface of thetop memory chip 2. The distance between thesilicone spacer 10 and thememory chip 2 of the stackedmodule 20 is preferably 0.3-0.5 mm.

Although only one stacked module is shown in fig. 12-14 and 16-15, in actual production, a plurality ofmemory chips 2 are generally stacked on the substrate 1 at the same time to form a plurality of stackedmodules 20, and the distribution of the plurality of stackedmodules 20 is shown in fig. 15.

And S50, fillingunderfill 11 in the silicagel partition plate 10, fillingunderfill 11 between the substrate 1 and thememory chips 2 and between the verticallyadjacent memory chips 2, and heating and curing. When theunderfill 11 is filled, a dispenser may be used for filling.

S60, removing thesilicone partition board 10, when thepressing plate 12 is disposed on thesilicone partition board 10, thepressing plate 12 may be removed at the same time as thesilicone partition board 10 is removed, or thepressing plate 12 may be removed before thesilicone partition board 10 is removed, and the stacked module of thesilicone partition board 10 is removed is shown in fig. 17. And (3) placing the stacked module without the silicagel partition plate 10 into a plastic package mold, filling aplastic package material 5 into the plastic package mold, and carrying out plastic package on the stacked module. As shown in fig. 18, after the plastic package is completed, thestorage chip 2 and theunderfill 11 are completely wrapped by themolding compound 5. After thestack module 20 is subjected to plastic packaging, if the upper surface of thememory chip 2 on the uppermost layer is wrapped by theplastic packaging material 5, theplastic packaging material 5 is ground, so that the upper surface of thememory chip 2 on the uppermost layer of thestack module 20 is exposed out of the plastic packaging, as shown in fig. 19, and thus the heat dissipation capability of the memory chip is improved.

S70, dividing the stacked module into independent packages, as shown in fig. 20.

In the above embodiment, if the lower surface of the substrate 1 has the solder balls 7 before thememory chips 2 are stacked, that is, in the step S10, when the lower surface of the substrate 1 has the solder balls 7, the substrate 1 is first adhered to thetemporary carrier board 9 by thetemporary bonding adhesive 8, and then thememory chips 2 are stacked on the substrate 1; and in the step S70, the temporary bonding glue and the temporary carrier are removed first, and then the stack module after being molded is divided into independent packages.

In the above embodiment, if the solder balls 7 are not mounted on the lower surface of the substrate 1 before thememory chips 2 are stacked, that is, when the solder balls 7 are not mounted on the lower surface of the substrate 1 in the step S10, the solder balls 7 are first mounted on the lower surface of the substrate 1 in the step S70, and then the stacked module after being molded is divided into individual packages.

The method for manufacturing the multilayer stacked memory provided in the above embodiment changes the production method that the Non-conductive Film 15 (NCF) is coated on thememory chip 2 and then the thermocompression bonding is performed in the prior art into the production method that the thermocompression bonding is performed on thememory chip 2 and then theunderfill 11 is filled between the upper and loweradjacent memory chips 2 and between thememory chip 2 and the substrate 1.

In the above embodiment, the partition structure is formed by using the silicagel partition plate 10 made of silica gel to assist the filling of theunderfill 11 in the stacked structure, and due to the non-stick property of silica gel and the soft and easy-to-adhere surface, the silica gel partition plate can be used as a shape-limiting mold cavity of theunderfill 11, and after theunderfill 11 is filled and cured, the silica gel can be peeled off, so that the process of filling after stacking can be realized.

Based on the manufacturing method of the multilayer stacked memory provided by the above embodiment, the invention further provides a multilayer stacked memory, which includes aplastic package material 5 and astacked module 20 located in theplastic package material 5, where the stackedmodule 20 includes a substrate 1 andmemory chips 2 located on the substrate 1, thememory chips 2 are stacked on the substrate 1 in a thermocompression bonding manner, when thememory chips 2 have multiple layers, thememory chips 2 on the upper layer are stacked on thememory chips 2 on the lower layer in the thermocompression bonding manner, and aunderfill 11 or theplastic package material 5 is filled between the substrate 1 and thememory chips 2 and between thememory chips 2 adjacent to each other up and down.

In conclusion, the technical scheme provided by the invention effectively reduces the manufacturing difficulty of the multilayer stacked memory chip by a mode of stacking first and then filling, and simultaneously reduces the cost of manufacturing materials by replacing pre-coating non-conductive adhesive with the traditional underfill or plastic packaging material. When the underfill is adopted to replace the non-conductive adhesive, the manufacture difficulty of multi-chip stacking is reduced by the way of stacking and then filling the underfill, the multi-chip stacking is suitable for stacking with high pin number, and meanwhile, the material cost is reduced and the total manufacturing cost can be reduced because the traditional underfill is used for replacing the pre-coating of the non-conductive adhesive. When the non-conductive adhesive is replaced by the plastic packaging material, due to the adoption of the exposed radiating fin structure, the temperature of the chip can be effectively reduced through radiating of the radiating fin, the plastic packaging material (such as MUF material) can be filled at the lower part of the chip, the phenomenon that the upper layer and the lower layer of the plastic packaging material are unbalanced in flow and a filling hole is formed at the lower part of the chip is avoided, and therefore the plastic packaging material can be replaced by the non-conductive adhesive (NCF) material, and the cost is reduced.

In the description of the present invention, it is to be understood that the terms "upper", "lower", "inside", "outside", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the device referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and should not be construed as limiting the present invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "disposed," "connected," and the like are to be construed broadly and can include, for example, fixed connections, removable connections, integral connections, or the presence of intervening components. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and not to be construed as limiting the present invention, and those skilled in the art can make changes, modifications, substitutions and alterations to the above embodiments within the scope of the present invention.

Claims (13)

Translated fromChinese

1.一种多层堆叠存储器制作方法，其特征在于,包括以下步骤：1. a multi-layer stacked memory fabrication method, is characterized in that, comprises the following steps:S10、准备存储芯片(2)和基板(1)，使用热压键合的方式将存储芯片(2)通过微凸点(3)焊接堆叠在基板(1)上；S10, preparing a memory chip (2) and a substrate (1), and using a thermocompression bonding method to weld and stack the memory chip (2) on the substrate (1) through micro-bumps (3);S20、使用热压键合的方式将另一层存储芯片(2)通过微凸点(3)焊接堆叠在上一层存储芯片(2)上；S20. The other layer of memory chips (2) is welded and stacked on the upper layer of memory chips (2) through micro-bumps (3) by means of thermocompression bonding;S30、如果所述基板(1)上堆叠的存储芯片(2)的层数等于设定的层数，则存储芯片(2)完成堆叠，形成堆叠模块(20)，然后执行步骤S40；如果所述基板(1)上堆叠的存储芯片(2)的层数小于设定的层数，则执行步骤S20；S30. If the number of layers of the memory chips (2) stacked on the substrate (1) is equal to the set number of layers, the memory chips (2) are stacked to form a stacked module (20), and then step S40 is performed; If the number of layers of the memory chips (2) stacked on the substrate (1) is less than the set number of layers, step S20 is performed;S40、在所述堆叠模块(20)的顶层的存储芯片(2)的上表面安装散热片(4)；S40, installing a heat sink (4) on the upper surface of the memory chip (2) on the top layer of the stacked module (20);S50、将安装有散热片(4)的堆叠模块放入塑封模具中，向塑封模具中填充塑封料(5)，对所述堆叠模块进行塑封，其中所述基板(1)与存储芯片(2)之间、以及上下相邻的存储芯片(2)之间均充满塑封料(5)，所述散热片(4)的上表面位于塑封料(5)外侧；S50. Put the stacked module on which the heat sink (4) is installed into a plastic sealing mold, fill the plastic sealing mold with a plastic sealing compound (5), and perform plastic sealing on the stacked module, wherein the substrate (1) and the memory chip (2) ) and between the upper and lower adjacent memory chips (2) are filled with plastic sealing compound (5), and the upper surface of the heat sink (4) is located outside the plastic sealing compound (5);S60、将塑封后的堆叠模块分割成独立封装。S60. Divide the plastic-encapsulated stacked modules into independent packages.2.根据权利要求1所述的多层堆叠存储器制作方法，其特征在于，在所述步骤S40中，在所述散热片(4)和顶层的存储芯片(2)的上表面之间涂敷散热胶(6)。2 . The method for manufacturing a multi-layer stacked memory according to claim 1 , wherein in the step S40 , coating is applied between the heat sink ( 4 ) and the upper surface of the memory chip ( 2 ) on the top layer. 3 . Thermal glue (6).3.根据权利要求2所述的多层堆叠存储器制作方法，其特征在于，所述散热片(4)的材质为铜或不锈钢。3 . The method for manufacturing a multi-layer stacked memory according to claim 2 , wherein the material of the heat sink ( 4 ) is copper or stainless steel. 4 .4.根据权利要求1所述的多层堆叠存储器制作方法，其特征在于，在所述步骤S50中，向塑封模具中填充的塑封料(5)为塑封底充料。4 . The method for manufacturing a multi-layer stacked memory according to claim 1 , wherein, in the step S50 , the plastic sealing compound ( 5 ) filled into the plastic sealing mold is a plastic sealing bottom filling material. 5 .5.根据权利要求1所述的多层堆叠存储器制作方法，其特征在于，5. The method for fabricating a multi-layer stacked memory according to claim 1, wherein,在所述步骤S10中，当所述基板(1)的下表面具有焊球(7)时，首先将所述基板(1)通过临时键合胶(8)粘贴在临时载板(9)上，然后再将存储芯片(2)堆叠在基板(1)上；并且在所述步骤S60中，首先将临时键合胶和临时载板去除，然后再将塑封后的堆叠模块分割成独立封装；In the step S10, when the lower surface of the substrate (1) has solder balls (7), firstly, the substrate (1) is pasted on the temporary carrier board (9) by a temporary bonding glue (8). , and then stack the memory chip (2) on the substrate (1); and in the step S60, first remove the temporary bonding glue and the temporary carrier plate, and then divide the plastic-encapsulated stacking module into independent packages;在所述步骤S10中，当所述基板(1)的下表面没有焊球(7)时，在所述步骤S60中，首先在基板(1)的下表面贴装焊球(7)，然后再将塑封后的堆叠模块分割成独立封装。In the step S10, when the lower surface of the substrate (1) has no solder balls (7), in the step S60, firstly, the solder balls (7) are mounted on the lower surface of the substrate (1), and then the solder balls (7) are mounted on the lower surface of the substrate (1). The plastic-encapsulated stacked modules are then divided into individual packages.6.一种多层堆叠存储器制作方法，其特征在于，包括以下步骤：6. A method for fabricating a multi-layer stacked memory, comprising the following steps:S10、准备存储芯片(2)和基板(1)，使用热压键合的方式将存储芯片(2)通过微凸点(3)焊接堆叠在基板(1)上；S10, preparing a memory chip (2) and a substrate (1), and using a thermocompression bonding method to weld and stack the memory chip (2) on the substrate (1) through micro-bumps (3);S20、使用热压键合的方式将另一层存储芯片(2)通过微凸点(3)焊接堆叠在上一层存储芯片(2)上；S20. The other layer of memory chips (2) is welded and stacked on the upper layer of memory chips (2) through micro-bumps (3) by means of thermocompression bonding;S30、如果所述基板(1)上堆叠的存储芯片(2)的层数等于设定的层数，则存储芯片(2)完成堆叠，形成堆叠模块(20)，然后执行步骤S40；如果所述基板(1)上堆叠的存储芯片(2)的层数小于设定的层数，则执行步骤S20；S30. If the number of layers of the memory chips (2) stacked on the substrate (1) is equal to the set number of layers, the memory chips (2) are stacked to form a stacked module (20), and then step S40 is performed; If the number of layers of the memory chips (2) stacked on the substrate (1) is less than the set number of layers, step S20 is performed;S40、在基板(1)上放置硅胶隔板(10)，所述硅胶隔板(10)围绕每个所述堆叠模块(20)的所有堆叠的存储芯片(2)，所述硅胶隔板(10)的下表面紧密贴合所述基板(1)的上表面；S40. Place a silica gel separator (10) on the substrate (1), the silica gel separator (10) surrounds all the stacked memory chips (2) of each of the stacked modules (20), and the silica gel separator ( The lower surface of 10) is closely attached to the upper surface of the substrate (1);S50、在所述硅胶隔板(10)内填充底充胶(11)，所述基板(1)与存储芯片(2)之间、以及上下相邻的存储芯片(2)之间均填充有底充胶(11)，并加热固化；S50. Filling underfilling glue (11) in the silica gel separator (10), between the substrate (1) and the memory chip (2) and between the upper and lower adjacent memory chips (2) are filled with Underfill glue (11), and heat to cure;S60、去除硅胶隔板(10)，将去除硅胶隔板(10)的堆叠模块放入塑封模具中，向塑封模具中填充塑封料(5)，对所述堆叠模块进行塑封；S60, removing the silica gel separator (10), placing the stacked module from which the silica gel separator (10) is removed into a plastic sealing mold, filling the plastic sealing mold with a plastic sealing compound (5), and performing plastic sealing on the stacked module;S70、将塑封后的堆叠模块分割成独立封装。S70. Divide the plastic-encapsulated stacked modules into independent packages.7.根据权利要求6所述的多层堆叠存储器制作方法，其特征在于，在步骤S40中，所述硅胶隔板(10)的上表面高度低于顶层的存储芯片(2)的上表面。7. The method for manufacturing a multi-layer stacked memory according to claim 6, characterized in that, in step S40, the height of the upper surface of the silicone separator (10) is lower than the upper surface of the memory chip (2) on the top layer.8.根据权利要求6所述的多层堆叠存储器制作方法，其特征在于，在步骤S40中，所述硅胶隔板(10)与堆叠模块(20)的存储芯片(2)之间的距离为0.3-0.5毫米。8 . The method for manufacturing a multi-layer stacked memory according to claim 6 , wherein, in step S40 , the distance between the silica gel separator ( 10 ) and the memory chip ( 2 ) of the stacked module ( 20 ) is 8 . 0.3-0.5mm.9.根据权利要求6所述的多层堆叠存储器制作方法，其特征在于，在所述步骤S40中，在所述硅胶隔板(10)上放置压板(12)；在所述步骤S60中，在去除硅胶隔板(10)的同时或在去除硅胶隔板(10)的之前将压板(12)去除。9. The method for manufacturing a multi-layer stacked memory according to claim 6, characterized in that, in the step S40, a pressing plate (12) is placed on the silica gel separator (10); in the step S60, The pressing plate (12) is removed at the same time as the silica gel separator (10) is removed or before the silica gel separator (10) is removed.10.根据权利要求9所述的多层堆叠存储器制作方法，其特征在于，所述压板(12)为不锈钢板。10. The method for manufacturing a multi-layer stacked memory according to claim 9, wherein the pressing plate (12) is a stainless steel plate.11.根据权利要求6所述的多层堆叠存储器制作方法，其特征在于，在所述步骤S60中，对所述堆叠模块(20)进行塑封后，研磨塑封料(5)，使得所述堆叠模块(20)的最上层存储芯片(2)的上表面从塑封中露出。11 . The method for manufacturing a multi-layer stacked memory according to claim 6 , wherein in the step S60 , after the stacked module ( 20 ) is plastic-sealed, the plastic sealing compound ( 5 ) is ground to make the stack The upper surface of the uppermost memory chip (2) of the module (20) is exposed from the plastic package.12.根据权利要求6所述的多层堆叠存储器制作方法，其特征在于，12. The method for fabricating a multi-layer stacked memory according to claim 6, wherein,在所述步骤S10中，当所述基板(1)的下表面具有焊球(7)时，首先将所述基板(1)通过临时键合胶(8)粘贴在临时载板(9)上，然后再将存储芯片(2)堆叠在基板(1)上；并且在所述步骤S70中，首先将临时键合胶和临时载板去除，然后再将塑封后的堆叠模块分割成独立封装；In the step S10, when the lower surface of the substrate (1) has solder balls (7), firstly, the substrate (1) is pasted on the temporary carrier board (9) by a temporary bonding glue (8). , and then stack the memory chip (2) on the substrate (1); and in the step S70, first remove the temporary bonding glue and the temporary carrier plate, and then divide the plastic-encapsulated stacking module into independent packages;在所述步骤S10中，当所述基板(1)的下表面没有焊球(7)时，在所述步骤S70中，首先在基板(1)的下表面贴装焊球(7)，然后再将塑封后的堆叠模块分割成独立封装。In the step S10, when there are no solder balls (7) on the lower surface of the substrate (1), in the step S70, the solder balls (7) are firstly mounted on the lower surface of the substrate (1), and then the solder balls (7) are mounted on the lower surface of the substrate (1). The plastic-encapsulated stacked modules are then divided into individual packages.13.一种多层堆叠存储器，包括塑封料(5)和位于塑封料(5)中的堆叠模块(20)，所述堆叠模块(20)包括基板(1)和位于基板(1)上的存储芯片(2)，所述存储芯片(2)通过热压键合的方式堆叠在基板(1)上，当存储芯片(2)具有多层时，上层的存储芯片(2)通过热压键合的方式堆叠在下层的存储芯片(2)上，其特征在于，所述基板(1)与存储芯片(2)之间、以及上下相邻的存储芯片(2)之间均填充有底充胶(11)或塑封料(5)。13. A multi-layer stacked memory, comprising a molding compound (5) and a stacking module (20) located in the molding compound (5), the stacking module (20) comprising a substrate (1) and a stacking module (20) located on the substrate (1) memory chips (2), the memory chips (2) are stacked on the substrate (1) by thermocompression bonding, and when the memory chips (2) have multiple layers, the memory chips (2) on the upper layer are bonded by thermocompression bonding are stacked on the lower memory chip (2) in an integrated manner, characterized in that a bottom charge is filled between the substrate (1) and the memory chip (2), and between the upper and lower adjacent memory chips (2). glue (11) or molding compound (5).

Images