Disclosure of Invention
The invention aims to provide a method for improving scribing edge breakage, which is to carry out doping procedures on functional areas of chips and simultaneously carry out doping procedures on scribing channel areas, so that doping areas can be designed for the scribing channel when photoetching patterns are designed, namely, the doping procedures for the scribing channel are not added independently and the product cost is not increased.
The technical problems solved by the invention are as follows:
How to reduce the influence of the edge breakage phenomenon of wafer cutting, thereby improving the yield of chips.
The aim of the invention can be achieved by the following technical scheme:
a method of improving scribe line chipping, comprising the steps of:
Step one, wafer preparation
Selecting an MCZ silicon single crystal wafer, wherein the 5 inch crystal orientation is <111>, the resistivity is 5.0-6.5 omega/cm, and the thickness is 220 mu m +/-10%;
Step two, doping the scribing channel
Carrying out phosphorus liquid source deposition under the working conditions of the furnace temperature of 1120 ℃ and oxygen of 2L/min, nitrogen of 3L/min and nitrogen carrying source of 1.2L/min;
After deposition, the phosphorus source is propelled under the working conditions of the furnace temperature of 1140 ℃ and oxygen of 2.5L/min and nitrogen of 4L/min;
Four probes were used to test the diffusion sheet resistance at 0.6Ω±10% and the junction depth at 12 μm±10%.
As a further scheme of the invention, the scribing channel doping in the second step adopts phosphorus doping.
As a further scheme of the invention, the deposition time of the phosphorus liquid source in the second step is 25min.
As a further scheme of the invention, the phosphorus source propulsion time in the second step is 150min.
The invention has the beneficial effects that:
(1) In the invention, the high-concentration impurity doping procedure is carried out on the scribing channel region, so that the scribing channel becomes loose, thereby reducing the severity of scribing broken edges and lattice damage caused by the scribing broken edges and improving the scribing quality of the wafer;
(2) The invention performs doping process on the chip functional region and simultaneously performs doping process on the scribing channel region, so that the doping region is designed on the scribing channel when the photoetching pattern is designed, the doping process on the scribing channel is not added independently and newly, and the product cost is not increased.
Drawings
The invention is further described below with reference to the accompanying drawings.
FIG. 1 is a schematic view of a conventional dicing street in the prior art;
FIG. 2 is a schematic diagram of a wafer edge breakage in the prior art;
FIG. 3 is a schematic illustration of the structure of scribe lane doping according to the present invention;
FIG. 4 is a schematic view of the structure of a scribe lane according to the present invention;
FIG. 5 is a perspective view of the bi-directional cutting station of the present invention;
fig. 6 is a front view of the bi-directional cutting table of the present invention.
Fig. 7 is a schematic view showing the internal structure of the driving chamber of the present invention.
The device comprises a 1-direction cutting table, a 101-direction wafer cutting table, 102, a Y-direction screw rod, 103, a movable base, 2, a portal frame, 201, a transverse guide block, 202, an X-direction screw rod, 203, a driving cavity, 204, a Z-direction screw rod, 205, a longitudinal guide block, 206, a cutting mounting plate and 207, and a cutting motor.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 3, the present invention is a method for improving scribe line breakage, comprising the following steps:
Step one, wafer preparation
Selecting an MCZ silicon single crystal wafer, wherein the 5 inch crystal orientation is <111>, the resistivity is 5.0-6.5 omega/cm, and the thickness is 220 mu m +/-10%;
Step two, doping the scribing channel
The method comprises the steps of adopting phosphorus doping, carrying out phosphorus liquid source deposition under the working conditions of 1120 ℃ of furnace temperature, 3L/min of nitrogen and 1.2L/min of nitrogen carrying source, wherein the time for the phosphorus liquid source deposition is 25min, carrying out phosphorus source propulsion under the working conditions of 1140 ℃ of oxygen, 2.5L/min of oxygen and 4L/min of nitrogen, wherein the time for the phosphorus source propulsion is 150min, and using four probes to test the diffusion square resistance of 0.6Ω+/-10% and the junction depth of 12 mu m+/-10%.
The wafer can be oxidized before the scribing channel is doped, the oxidation condition is that a field oxygen masking layer is manufactured under the working conditions of the furnace temperature of 1100 ℃, the oxygen gas of 4L/min and the hydrogen gas of 5L/min, and the thickness of the oxidation layer is 1.5 mu m +/-10%.
The base of the scheme is that when the monocrystalline silicon is doped without impurities, the crystal lattice structure is perfect, the hardness is highest, the brittleness is also highest, impurity defects can be formed along with the doping of impurity atoms, the impurity defects can reduce the brittleness of the monocrystalline silicon material and become termination points when lattice damage expands, so that the high-concentration impurity doping can enable scribing channels to become loose, and the severity of scribing edge breakage and lattice damage caused by the scribing edge breakage can be reduced.
Referring to fig. 5-7, step one, a wafer is ready to be cut in two directions by a two-way cutting table 1, the two-way cutting table 1 is in a U-shaped structure, so that a block-shaped supporting plate is convenient to install, the side plates on two sides of the U-shaped structure of the two-way cutting table 1 are vertically provided with block-shaped supporting plates, and the top parts of the supporting plates on two sides are fixedly provided with a wafer cutting table 101 for placing wafer raw materials;
The width of the block-shaped supporting plate is consistent with the width of the side plate of the bidirectional cutting table 1, so that the whole structure is more attractive.
Y-direction screw rods 102 are arranged between side plates at two sides of the inside of the bidirectional cutting table 1, guide sliding rods are arranged at two sides of the Y-direction screw rods 102, a movable base 103 in the bidirectional cutting table 1 is connected to the Y-direction screw rods 102 in a threaded manner, the movable base 103 is arranged on the guide sliding rods in a sliding manner, and a portal frame 2 is fixedly arranged on the movable base 103;
The guide slide bars on two sides of the Y-direction screw rod 102 are symmetrical about the center line of the Y-direction screw rod 102, through holes matched with the guide slide bars are formed in two sides of the threaded holes of the movable base 103, the movable base 103 is slidably connected to the guide slide bars through the through holes on two sides, the movable base 103 slides in the bidirectional cutting table 1 more stably, and the cutting precision of the cutting mechanism on wafer materials is improved.
The wafer cutting table 101 penetrates through the portal frame 2, cutting mechanisms are respectively arranged on two sides of the wafer cutting table 101 in the portal frame 2, the two cutting mechanisms are symmetrical in the vertical direction about the central line of the wafer cutting table 101 in the horizontal direction, synchronous cutting of wafer materials is achieved by the two cutting mechanisms, and cutting stability is improved;
The cutting mechanism comprises a transverse guide block 201 fixedly arranged in the portal frame 2, a penetrating strip-shaped notch is formed in the transverse guide block 201 in the vertical direction, a driving cavity 203 is connected to the strip-shaped notch of the transverse guide block 201 in a sliding manner, the driving cavity 203 is of a cuboid cavity structure with a certain wall thickness, the wall thickness is matched with the width of the strip-shaped notch, and the driving cavity 203 can slide in the strip-shaped notch conveniently;
The inside of the driving cavity 203 is provided with a rectangular notch which penetrates through the driving cavity 203 in the horizontal direction, the driving cavity 203 is arranged in a cross superposition sliding way through the rectangular notch and the strip notch of the transverse guide block 201, and stable sliding of the driving cavity 203 on the transverse guide block 201 is realized through mutual locking of the rectangular notch and the strip notch;
The X-direction screw rod 202 is arranged in the strip-shaped notch, a threaded hole matched with the X-direction screw rod 202 is formed in the part, located in the strip-shaped notch, of the driving cavity 203, and the driving cavity 203 is connected to the X-direction screw rod 202 through the threaded hole in a threaded mode;
The inside of the driving cavity 203 is vertically provided with a Z-direction screw rod 204, the Z-direction screw rod 204 is connected with a longitudinal guide block 205 in a threaded manner, two sides of the front face of the longitudinal guide block 205 are provided with connecting plates, the connecting plates on the two sides penetrate through a chute on the front face of the driving cavity 203 and are connected with a cutting mounting plate 206, and the cutting mounting plate 206 is provided with a cutting motor 207.
When the wafer is cut, the cutting mechanisms on the upper side and the lower side of the portal frame 2 are synchronously adjusted, and the cutting scissors of the two cutting mechanisms are collinear in the vertical direction, so that the cutting of the wafer material is realized;
The specific adjustment is that the motor on the X direction drives the X-direction screw rod 202 to rotate, so that the X-direction screw rod 202 drives the driving cavity 203 to move in the X direction, and the motor on the Z direction drives the Z-direction screw rod 204 to rotate, so that the Z-direction screw rod 204 drives the longitudinal guide block 205 to move in the Z direction, and the adjustment on the position of the cutting motor 207 is realized, after the adjustment of the cutting mechanisms on the two sides of the portal frame 2 is finished, the motor on the Y direction drives the Y-direction screw rod 102 to rotate, so that the Y-direction screw rod 102 drives the portal frame 2 to move in the Y direction, and the two cutting structures synchronously cut the top surface and the bottom surface of the wafer material, so that the cutting stability of the wafer material can be improved, and the edge breakage during cutting is effectively avoided.
Wherein, a cutting notch for cutting the eutectic round material is arranged on the wafer cutting table 101.
Referring to fig. 4, in combination with the edge smoothness of undoped scribe lanes and doped scribe lanes, the uniformity of the scribe lane smoothness in the phosphorus doping process is better than that of undoped scribe lanes, and it can be concluded that the present invention optimizes the morphology quality of the scribe lanes and improves the influence of scribe chipping.
The method is specifically characterized in two aspects:
a1, the brittleness of the scribing channel can be reduced, so that the breakage phenomenon is not easy to occur during scribing, and the yield of the scribing process is improved;
A2, the stress transmission in the dicing process can be restrained, so that the damage layer is not easy to transmit to the active region of the chip, and the damage of the active region is one of the main reasons for the reliability failure of the chip.
On the premise of not increasing the manufacturing cost and not needing to add additional working procedures, the chip manufacturing process is greatly improved and the performance of the chip is improved by optimizing the chip design.
When the doped scribing channel is adopted for scribing, the feeding speeds of 60mm/s, 80mm/s and 100mm/s are respectively tested, wherein the scribing channel morphology meeting the quality requirement can be obtained under the process condition of 80mm/s, so that the invention can adapt to the higher feeding speed so as to improve the production efficiency of the scribing process.
The foregoing describes one embodiment of the present invention in detail, but the description is only a preferred embodiment of the present invention and should not be construed as limiting the scope of the invention. All equivalent changes and modifications within the scope of the present invention are intended to be covered by the present invention.