CN114121117A

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Info

Publication number: CN114121117A
Application number: CN202111447239.XA
Authority: CN
Inventors: 张丽丽; 陈任佳; 李苑锋; 林劲涛
Original assignee: Shenzhen Jiahejingwei Electronic Technology Ltd
Current assignee: Shenzhen Jiahejingwei Electronic Technology Ltd
Priority date: 2021-11-30
Filing date: 2021-11-30
Publication date: 2022-03-01
Anticipated expiration: 2041-11-30
Also published as: CN114121117B

Abstract

Translated fromChinese

本申请提供了一种单晶内存修补单晶内存的方法和装置，包括：依据不良IC的类型和不良区域，对所述不良IC进行分组；从所述A组、B组、C组、D组和E组中选择其中两组不良IC，以及从选中的其中一组选择至少2个不良IC，从选中的另一组选择至少1个不良IC，并依据所述不良IC的分组和预设规则，划分所述不良IC中地址线位的IC位区；依据所述IC位区和所述不良IC的类型，调整×16IC单晶封装的PCB板的布局。通过上述方法可对不良品的SDP类型封装的内存进行修补，利用出厂的内存IC存在不良产品，通过修补使其变为合格产品，有效的利用了不良产品，节省资源，同时也在一定程度上有利于环境的保护。

The present application provides a method and device for repairing a single crystal memory with a single crystal memory, including: grouping the defective ICs according to the type and defective area of the defective IC; Two groups of bad ICs are selected from group E and group E, and at least 2 bad ICs are selected from one of the selected groups, and at least 1 bad IC is selected from the other selected group, and the grouping and preset of said bad ICs According to the rules, divide the IC bit area of the address line bits in the defective IC; according to the IC bit area and the type of the defective IC, adjust the layout of the PCB board of the ×16IC single crystal package. Through the above method, the defective SDP type packaged memory can be repaired. There are defective products in the factory-made memory IC, and they can be changed into qualified products through repairing. The defective products are effectively used, resources are saved, and at the same time, to a certain extent Conducive to the protection of the environment.

Description

Method, device and equipment for repairing single crystal memory by using single crystal memory

Technical Field

The present application relates to the field of memory chip technology, and in particular, to a method, an apparatus, and a device for repairing a single crystal memory with a single crystal memory.

Background

The Memory, also called Random Access Memory (RAM), is an internal Memory that exchanges data directly with the CPU. It can be read and written at any time (except for refreshing), and has high speed, and is usually used as a temporary data storage medium of an operating system or other programs in operation. The RAM can write (store) or read (take out) information from any one of designated addresses at any time when it is operated. The biggest difference with the ROM is the volatility of data, i.e. the stored data will be lost as soon as power is turned off. RAM is used in computers and digital systems to temporarily store programs, data, and intermediate results.

However, memory manufacturers cannot achieve 100% good products in the wafer production and IC package manufacturing processes.

At present, defective products generated by memory manufacturers are about 10-15%, so that a large amount of resources are wasted, and due to the fact that precious metals are used in the processes of memory IC and packaging, if the defective products are destroyed, further resources are wasted; at present, precious metals are extracted in a chemical mode, so that environmental pollution is caused to a certain extent.

Disclosure of Invention

In view of the above, the present application is proposed to provide a method, apparatus and device for repairing a single crystal memory, which overcomes or at least partially solves the above problems, and comprises:

a method of repairing a single crystal memory bank for a reconstituted package of a defective IC packaged ina x 16 single crystal, the method comprising:

grouping the bad ICs according to the types and bad areas of the bad ICs; wherein the grouping comprises group A, group B, group C, group D and group E; the bad area type is an address line bit area; wherein, the group A area is 0-3 bits, the group B area is 4-7 bits, the group C area is 8-11 bits, the group D area is 12-15 bits, and the group E area is 8-15 bits;

selecting two groups of bad ICs from the groups A, B, C, D and E, selecting at least 2 bad ICs from one selected group, selecting at least 1 bad IC from the other selected group, and dividing an IC bit area of an address line position in the bad ICs according to the grouping of the bad ICs and a preset rule;

and adjusting the layout of the PCB of the X16 IC single crystal package according to the IC position area and the type of the bad IC.

Optionally, the grouping according to the type of the bad IC and the bad area includes a step before the group a, the group B, the group C, the group D, and the group E, including:

determining a normal diode value and an error threshold value of the address line bit according to a normal address line bit of a normal IC corresponding to the bad IC;

detecting a diode of each address line bit of the bad IC, comparing the diode with the normal diode value and the error value, and determining the address line bit as the bad address line bit if the abnormal value appears;

determining the bad region of the bad IC as a function of bad address line bits.

Optionally, the step of grouping the bad ICs according to the types of the bad ICs and the bad areas includes:

detecting address line bits of a bad IC according to the type of the bad IC, and determining a bad area of the address line bits in the bad IC;

dividing the bad ICs into 5 groups according to the bad area of the address line bits; the address line group comprises an A group with a defective area of only 0-3 bits, a B group with a defective area of only 4-7 bits, a C group with a defective area of only 8-11 bits, a D group with a defective area of only 12-15 bits and an E group with a defective area of only 8-15 bits.

Optionally, the step of dividing the IC bit regions of the address line bits in the bad IC according to the grouping of the bad ICs and a preset rule includes:

determining address line bits available in the bad IC from the grouping of the bad ICs;

and combining the available address line bits in the bad IC into the IC bit area according to the preset rule.

Optionally, the step of combining the address line bits available in the bad IC into the IC bit region according to the preset rule includes:

when the MDQ digit sequence of the PCB board is 64 bits, determining the IC bit area according to the available address line bits in the bad IC and the types of the available address line bits; wherein the number of the IC bit regions is 8, and the IC bit regions comprise 8 available address line bits.

when the MDQ digit order of the PCB board is 32 bits, determining the IC bit area according to available address line bits and types of the available address line bits in the bad IC; wherein the number of the IC bit regions is 4, and the IC bit regions comprise 8 available address line bits.

Preferably, the step of adjusting the layout of the PCB board of the x 16IC single crystal package according to the type of the IC site area and the defective IC includes:

determining the arrangement sequence of the bad ICs according to the IC bit regions;

adjusting the layout of the PCB according to the type of the bad ICs and the arrangement sequence of the bad ICs;

wherein, the layout adjustment of the PCB board includes:

setting resistors R26, R29, R31, R34, R72, R73, R76, R77, R80, R83, R118 and R119 on the memory PCB board to be 0 ohm;

setting a pin T7 of the memory PCB to be empty;

and shorting the 1 st pin and the 2 nd pin of the memory PCB boards Y1-Y6 respectively.

Optionally, after the step of adjusting the layout of the PCB board of the × 16IC single crystal package according to the IC site area and the type of the bad IC, the method includes:

determining the packaging position of the bad IC according to the IC position area, the type of the bad IC and the laid PCB;

and packaging the bad IC to the arranged PCB according to the packaging position.

An apparatus for repairing a single crystal memory bank by a single crystal memory bank, applied to a restructuring package of a defective IC ofa x 16 single crystal package, the apparatus comprising:

the grouping module is used for grouping the bad ICs according to the types and the bad areas of the bad ICs; wherein the grouping comprises group A, group B, group C, group D and group E; the bad area type is an address line bit area; wherein, the group A area is 0-3 bits, the group B area is 4-7 bits, the group C area is 8-11 bits, the group D area is 12-15 bits, and the group E area is 8-15 bits;

the selection module is used for selecting two groups of bad ICs from the groups A, B, C, D and E, selecting at least 2 bad ICs from one selected group, selecting at least 1 bad IC from the other selected group, and dividing an IC bit area of an address line bit in the bad ICs according to the grouping and preset rules of the bad ICs;

and the adjusting module is used for adjusting the layout of the PCB of the X16 IC single crystal package according to the IC bit region and the type of the bad IC.

An apparatus comprising a processor, a memory, and a computer program stored on the memory and capable of running on the processor, the computer program when executed by the processor implementing the steps of the method of single crystal memory repair of single crystal memory as described above.

A computer readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method for repairing a monocrystalline memory as described above.

The application has the following advantages:

in the embodiment of the application, the grouping is performed according to the type and the bad area of the bad memory IC, and the grouping comprises a group A, a group B, a group C, a group D and a group E; selecting two groups of poor memory ICs and determining a matching scheme of the two groups of poor memory ICs; determining the layout of a PCB of a multiplied by 16IC single crystal package according to the type of a bad memory IC and a matching scheme between the bad memory ICs; and packaging the two groups of bad memory ICs to the arranged memory PCB according to the matching scheme of the two groups of bad memory ICs. The method can repair the memory packaged by SDP type of defective products, and the defective products of the memory IC from factory are utilized to be changed into qualified products through repair, thereby effectively utilizing the defective products, saving resources and being beneficial to environmental protection to a certain extent.

Drawings

In order to more clearly illustrate the technical solutions of the present application, the drawings needed to be used in the description of the present application will be briefly introduced below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive labor.

Fig. 1 is a flowchart illustrating steps of a method for repairing a single-crystal memory by using a single-crystal memory according to an embodiment of the present disclosure;

fig. 2 is a block diagram illustrating an apparatus for repairing a single-crystal memory by using a single-crystal memory according to an embodiment of the present disclosure;

fig. 3 is a schematic diagram of a Layout structure of a PCB corresponding to a memory IC according to an embodiment of the present disclosure

Fig. 4 is a schematic structural diagram of a computer device according to an embodiment of the present invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present application more comprehensible, the present application is described in further detail with reference to the accompanying drawings and the detailed description. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that, in any embodiment of the present invention, the SDP Package of the memory is a Package including a Die (here, a memory granule, i.e., a memory IC), that is, an SDP (signal-Die Package), and the capacity of the Package is also the capacity size of the memory granule. DDP is a Package containing 2 Dies, namely a DDP (Dual-Dial Package) packaging mode, and the capacity is the capacity of 2 memory granules; of course, the DDP packaging method can also be understood as connecting two memory granules in parallel to extend the bit width, for example, two × 8 memory granules, and by using the DDP packaging method, the whole memory granule can be regarded as a × 16 memory granule. An IC Chip (Integrated Circuit Chip) is a Chip formed by placing an Integrated Circuit formed by a large number of microelectronic components (transistors) on a plastic substrate; package, a term for circuit integration, is a process of assembling an integrated circuit into a chip end product, in short, an integrated circuit Die (Die) produced by a foundry is placed on a substrate for carrying, pins are led out, and then fixed and packaged into a whole.

Referring to fig. 1, a method for repairing a single crystal memory provided in an embodiment of the present application is illustrated, and is applied to a restructured package of a defective IC of a × 16 single crystal package, that is, the method is used for repairing an SDP memory of a package type × 16IC, and the method includes:

s110, grouping the bad ICs according to the types and the bad areas of the bad ICs; wherein the grouping comprises group A, group B, group C, group D and group E; the bad area type is an address line bit area; wherein, the group A area is 0-3 bits, the group B area is 4-7 bits, the group C area is 8-11 bits, the group D area is 12-15 bits, and the group E area is 8-15 bits;

s120, selecting two groups of bad ICs from the groups A, B, C, D and E, selecting at least 2 bad ICs from one selected group, selecting at least 1 bad IC from the other selected group, and dividing an IC bit area of an address line bit in the bad ICs according to the grouping and preset rules of the bad ICs;

s130, adjusting the layout of the PCB of the X16 IC single crystal package according to the IC position area and the type of the bad IC.

In the embodiment of the present application, the bad ICs are grouped by the type of the bad IC and the bad area; selecting two groups of bad ICs from the groups A, B, C, D and E, selecting at least 2 bad ICs from one selected group, selecting at least 1 bad IC from the other selected group, and dividing an IC bit area of an address line position in the bad ICs according to the grouping of the bad ICs and a preset rule; and adjusting the layout of the PCB of the X16 IC single crystal package according to the IC position area and the type of the bad IC. The method can repair the SDP type packaged X16 IC memory of the defective product, and the defective product existing in the memory IC from factory is utilized to be changed into a qualified product through repair, thereby effectively utilizing the defective product, saving resources and being beneficial to environmental protection to a certain extent.

Next, a method for repairing the single crystal memory by the single crystal memory according to the exemplary embodiment will be further described.

In an embodiment of the present application, the step of grouping according to the type of the bad IC and the bad area as described in step S110, and including the groups before the group a, the group B, the group C, the group D, and the group E, includes:

In an embodiment of the present invention, the detecting an address line of a defective memory IC according to a type of the defective memory IC to obtain an address bit detection result including a defective area includes: determining the address line bit of a corresponding normal memory IC according to the type of the bad memory IC;

and detecting an address line of a bad memory IC according to the address line position of the normal memory IC, and determining the address line position of a bad area of the bad memory IC.

As one and more examples, for example, the splitting classification can be performed by simulating a test fixture for a "memory bank" application and testing bad bits in "address lines" or "address lines" in a chip by general memory chip testing software (e.g., memtest/RST/self-development software); the memory IC can be detected through a simulation memory model to obtain a bad area of an address line bit in the bad memory IC, for example, if the bad area is located in 0-3 bits of the address line bit, the bad memory IC is divided into A groups, if the detected bad area is located in 4-7 bits of the address line bit, the bad memory IC is divided into B groups, the groups are sequentially classified into C groups and D groups, if the detected bad area is located in 8-11 bits and 12-15 bits of the address line bit, the bad memory IC is divided into E groups, and the bad memory IC is maximally reused by being grouped into different groups for different combinations.

As described in step S110, the bad ICs are grouped according to the types of the bad ICs and the bad areas.

In an embodiment of the present invention, a specific process of "grouping the bad ICs according to the types and bad areas of the bad ICs" in step S110 may be further described with reference to the following description.

Detecting address line bits of a defective IC according to the type of the defective IC, and determining a defective area of the address line bits in the defective IC;

In the above embodiment, the bad memory ICs are grouped, for example, the bad memory ICs are divided into different groups a, B, C, D and E, and an optimized combination manner is obtained through combination and matching of different manners, so as to obtain a group matching repair scheme, which can optimize the combination manner of the bad memory ICs, improve the utilization rate of the bad memory ICs, and further avoid waste caused by direct discarding or destroying of the bad memory ICs.

It should be noted that the memory IC is a kind of IC, and due to its high precision, a certain defective product is generated during the production of the Package (Package), and the defective product cannot be used directly, according to the working principle of the CPU and the memory, the data transmission between the CPU and the memory is one-time transmission of multiple bits (the specific bit number is determined according to the data bit width matched between the CPU and the memory), at present, the mainstream PC is generally 8 bits, that is, 8bit address lines of the memory IC are required to receive data at the same time, otherwise, data transmission cannot be completed, and therefore, if there are bad address line bits in the memory IC, the whole memory can not be used, and the defective products of the manufacturers of the memory ICs are also directly used for memory production, so that the defective memory ICs can be reused, the waste is reduced, meanwhile, the defective rate in the memory production is reduced, and the high cost caused by defective products is greatly reduced.

As described in step S120, two groups of bad ICs are selected from the groups a, B, C, D and E, at least 2 bad ICs are selected from one selected group, at least 1 bad IC is selected from the other selected group, and the IC bit regions of the address line bits in the bad ICs are divided according to the grouping of the bad ICs and a preset rule.

In an embodiment of the present invention, a specific process of "selecting two bad ICs from the groups a, B, C, D and E, and selecting at least 2 bad ICs from the selected one group, selecting at least 1 bad IC from the selected another group, and dividing the IC bit regions of the address line bits in the bad ICs according to the grouping of the bad ICs and a preset rule" in step S120 may be further described in conjunction with the following description.

Determining address line bits available in the bad ICs from the grouping of the bad ICs as described in the following steps;

and combining the available address line bits in the bad IC into the IC bit area according to the preset rule as follows.

In an embodiment of the present invention, the step of combining the address line bits available in the bad IC into the IC bit region according to the predetermined rule includes: when the MDQ digit sequence of the PCB board is 64 bits, determining the IC bit area according to the available address line bits in the bad IC and the types of the available address line bits; specifically, the arrangement sequence of the address line bits of the good area in the bad memory IC is determined according to the MDQ digit sequence and the address line bit type; wherein the MDQ digit order comprises bits 0-63; selecting 4 first bad memory ICs from one group of the selected groups, selecting 2 second bad memory ICs from the other group, and fully arranging the address line bits of the good area in 8 groups according to the arrangement sequence; wherein the number of the IC bit regions is 8, and the IC bit regions comprise 8 available address line bits.

In the above embodiments, the MDQ digit sequence is used to combine the bad memory ICs into 64Bit memory banks, which are currently used in mainstream computers, such as DDR4 type memory.

In an embodiment of the present invention, when the MDQ bit order of the PCB board is 32 bits, the IC bit area is determined according to the available address line bits and the type of the available address line bits in the bad IC; specifically, the arrangement sequence of the address line bits of the good area in the bad memory IC is determined according to the MDQ digit sequence and the address line bit type; wherein the MDQ digit order comprises bits 0-31; when the MDQ digit sequence is 0-31 bits, selecting 2 first bad memory ICs from one group of the selected groups, selecting 1 second bad memory ICs from the other group, and fully arranging the address line bits of the good area into 4 groups according to the arrangement sequence; the number of the IC bit regions is 4, and the IC bit regions include 8 available address line bits.

In the above embodiments, the 32-Bit memory with the same line mode is also the same, and can also be used in the main control IC-based product application of the "ARM" architecture and the "DSP" architecture.

In an embodiment of the present invention, determining an arrangement order of address line bits of a good area in the bad memory IC according to the MDQ bit order and the address line bit type includes: according to the MDQ digit sequence, combining every 8-bit address line bits, shielding the address line bits of the bad area, and determining the arrangement sequence of the address line bits of the good area in the bad memory IC; the high bit is an 8-bit UDQS address line, and the low bit is an 8-bit LDQS address line.

It should be noted that, if the MDQ bits are 0-127, the MDQ bits can also be used as a patch for a 128-bit wide memory; as the 128-bit wide memory belongs to the special memory, the method can be used for repairing the 128-bit wide memory.

In an example, two bad memory ICs are selected from the group a, the group B, the group C, the group D, and the group E, and a matching scheme of the two bad memory ICs is determined, for better clarity, the scheme of the group B and the group E will be taken as an example, but the present application is not limited to the combination of the scheme of the group B and the group E;

as shown in the following table:

as in the above table, the 4 first bad memory ICs of the a group and the 2 second bad memory ICs of the E group are selected for scheme matching; specifically, because the bad bits of the address line of the A group are 0-3 bits, the E group is 8-15 bits, the corresponding good address line bits of the A group are 4-7 bits and 8-15 bits, and the good address line bits of the IC of the E group are 0-7 bits; using 8-15 bits in a1 st first bad memory IC as a first group IC (U1), dividing 8-15 bits in a second first bad memory IC into a third group IC (U3), combining two groups of 4-7 bits in the 1 st and 2 nd first bad memory ICs into 8 bits to form a second group IC (U1+ U2), wherein the second group IC is not a separate memory IC and is composed of a main body or partial address line bits of the first group IC and the third group IC, so that the second group IC is arranged to 0-23 bits of MDQ bits, then arranging the 1 st second bad memory IC to 24-31 bits of the MDQ bits as a fourth group IC (U3), which is arranged in the first half, and arranging the first half in a mirror image mode by the other half and the arrangement combination, thereby completing scheme matching;

in addition, when the bad memory ICs are matched, the high bit address lines (8-15 bits of UDQS address lines) of the first bad memory IC of the group A are completely good, so that the high bit address lines of the first bad memory IC of the group A correspond to and repair the UDQS corresponding to the 0-7 bits in the MDQ, the 0-3 bits of the 1 st first bad memory IC and the 2 nd first bad memory IC correspond to and repair the LDQS corresponding to the 8-15 bits in the MDQ, the 8-15 bits of the 2 nd first bad memory IC repair the UDQS corresponding to the 16-23 bits in the MDQ, and the 1 st second bad memory IC corresponds to and repair the LDQS corresponding to the 24-31 bits in the MDQ.

It should be noted that, there are address lines and address lines in the complete memory, and the basic component unit of the memory is the memory IC, and the address lines and address lines of the memory are provided by the memory IC, wherein, as shown in fig. 3, the address lines of the memory IC are DQS0-DQS 7; the address line is a0-An of the IC, where the number of address line bits (i.e., the size of n) of the memory IC determines the capacity size of the memory IC, for example, when n is 11, the memory IC capacity is 128Mbit (i.e., 16MB), when n is 12, the memory IC capacity is 256Mbit (32MB), when n is 13, the memory IC capacity is 512Mbit (64MB), when n is 14, the memory IC capacity is 1024Mbit (128MB), when n is 15, the memory IC capacity is 2048Mbit (256MB), and when n is 16, the memory IC capacity is 4096Mbit (512 MB); the address lines further include BA0, BA1, and BG 0.

In step S130, the layout of the PCB board of the × 16IC single crystal package is adjusted according to the IC bit region and the type of the bad IC.

Referring to fig. 3, in an embodiment of the present invention, a specific process of "adjusting the layout of the PCB board of the × 16IC single crystal package according to the IC bit region and the type of the bad IC" in step S130 can be further described with reference to the following description.

The step of adjusting the layout of the PCB board of the x 16IC single crystal package according to the type of the bad IC and the IC bit region comprises the following steps:

determining the arrangement sequence of the bad ICs according to the IC bit regions; adjusting the layout of the PCB according to the type of the bad ICs and the arrangement sequence of the bad ICs; wherein, the layout adjustment of the PCB board includes: setting resistors R26, R29, R31, R34, R72, R73, R76, R77, R80, R83, R118 and R119 on the memory PCB board to be 0 ohm; setting a pin T7 of the memory PCB to be empty; and shorting the 1 st pin and the 2 nd pin of the memory PCB boards Y1-Y6 respectively.

It should be noted that, as shown in fig. 3, the signal pin of E9 of U1 on the memory PCB is connected through a resistor R26, and the connection of the signal lines of E9 at other IC positions with resistors R29, R31, R34, R72, R73, R76, R77, R80, R83, R118, and R119 is the same as that of the resistor R26, so that, not shown in fig. 3, the same jumper connection method of Y2-Y6 can refer to the jumper of Y1 in fig. 3.

In the above embodiment, according to the set memory PCB and the bad memory IC matching the address line, the address bus, the data bus, and the control bus connecting the bad memory IC and the memory PCB are used to perform memory repair, specifically, the LDQS of the bad memory IC correspondingly repairs the LDQS position of the memory PCB; the UDQS of the bad memory IC correspondingly repairs the UDQS of the memory PCB, wherein the LDQS comprises LDQS _ t + LDQS _ c, and the control address bit is 0-7 bit; the uDQS comprises UDQS _ t + UDQS _ c, and the control address bits are 8-15 bits.

In step S130, according to the matching scheme of the two bad memory ICs, the step after the two bad memory ICs are packaged to the set memory PCB is performed:

determining the packaging position of the bad memory IC according to the matching scheme between the bad memory ICs and the laid PCB board;

and packaging the bad memory IC to the arranged PCB according to the packaging position.

In this application, x 8IC means an IC having a grain bit width of 8 bits, and x 16 means an IC having a grain bit width of 16 bits.

In the above embodiment, the memory PCB board is configured according to JEDEC (solid state technology association is a leading standard organization of the microelectronics industry) specifications; the PCB for dividing and classifying bad bits in bad memory IC chips and re-designing circuits uses JEDEC standard as the principle of application design to avoid the occurrence of related compatibility and electrical problems.

For the device embodiment, since it is basically similar to the method embodiment, the description is simple, and for the relevant points, refer to the partial description of the method embodiment.

Referring to fig. 2, a device for repairing a single crystal memory by a single crystal memory according to an embodiment of the present application is shown, which is applied to a restructuring package of a defective IC packaged by x 16 single crystal;

the method specifically comprises the following steps:

agrouping module 210, configured to group bad ICs according to types and bad areas of the bad ICs; wherein the grouping comprises group A, group B, group C, group D and group E; the bad area type is an address line bit area; wherein, the group A area is 0-3 bits, the group B area is 4-7 bits, the group C area is 8-11 bits, the group D area is 12-15 bits, and the group E area is 8-15 bits;

a selectingmodule 220, configured to select two groups of bad ICs from the groups a, B, C, D, and E, select at least 2 bad ICs from the selected group, select at least 1 bad IC from the selected other group, and divide an IC bit area of an address line bit in the bad ICs according to the grouping of the bad ICs and a preset rule;

and anadjusting module 230 for adjusting the layout of the PCB board of the × 16IC single crystal package according to the IC bit region and the type of the bad IC.

Referring to fig. 4, a computer device for illustrating a method for repairing a single crystal memory by using a single crystal memory according to the present invention may specifically include the following:

thecomputer device 12 described above is embodied in the form of a general purpose computing device, and the components of thecomputer device 12 may include, but are not limited to: one or more processors orprocessing units 16, asystem memory 28, and abus 18 that couples various system components including thesystem memory 28 and theprocessing unit 16.

Bus 18 represents one or more of any of several types ofbus 18 structures, including amemory bus 18 or memory controller, aperipheral bus 18, an accelerated graphics port, and a processor orlocal bus 18 using any of a variety ofbus 18 architectures. By way of example, such architectures include, but are not limited to, Industry Standard Architecture (ISA)bus 18, micro-channel architecture (MAC)bus 18,enhanced ISA bus 18, audio Video Electronics Standards Association (VESA)local bus 18, and Peripheral Component Interconnect (PCI)bus 18.

Computer device 12 typically includes a variety of computer system readable media. Such media may be any available media that is accessible bycomputer device 12 and includes both volatile and nonvolatile media, removable and non-removable media.

Thesystem memory 28 may include computer system readable media in the form of volatile memory, such as Random Access Memory (RAM)30 and/orcache memory 32.Computer device 12 may further include other removable/non-removable, volatile/nonvolatile computer system storage media. By way of example only,storage system 34 may be used to read from and write to non-removable, nonvolatile magnetic media (commonly referred to as "hard drives"). Although not shown in FIG. 4, a magnetic disk drive for reading from and writing to a removable, nonvolatile magnetic disk (e.g., a "floppy disk") and an optical disk drive for reading from or writing to a removable, nonvolatile optical disk (e.g., a CD-ROM, DVD-ROM, or other optical media) may be provided. In these cases, each drive may be connected tobus 18 by one or more data media interfaces. The memory may include at least one program product having a set (e.g., at least one) of program modules 42, with the program modules 42 configured to carry out the functions of embodiments of the invention.

A program/utility 40 having a set (at least one) of program modules 42 may be stored, for example, in memory, such program modules 42 including, but not limited to, an operating system, one or more application programs, other program modules 42, and program data, each of which examples or some combination thereof may comprise an implementation of a network environment. Program modules 42 generally carry out the functions and/or methodologies of the described embodiments of the invention.

Computer device 12 may also communicate with one or more external devices 14 (e.g., keyboard, pointing device,display 24, camera, etc.), with one or more devices that enable a healthcare worker to interact withcomputer device 12, and/or with any devices (e.g., network card, modem, etc.) that enablecomputer device 12 to communicate with one or more other computing devices. Such communication may be through an input/output (I/O)interface 22. Also,computer device 12 may communicate with one or more networks (e.g., a Local Area Network (LAN)), a Wide Area Network (WAN), and/or a public network (e.g., the Internet) vianetwork adapter 20. As shown, thenetwork adapter 20 communicates with the other modules of thecomputer device 12 via thebus 18. It should be appreciated that although not shown in FIG. 4, other hardware and/or software modules may be used in conjunction withcomputer device 12, including but not limited to: microcode, device drivers,redundant processing units 16, external disk drive arrays, RAID systems, tape drives, and databackup storage systems 34, etc.

Theprocessing unit 16 executes programs stored in thesystem memory 28 to perform various functional applications and data processing, such as implementing the method for repairing the single crystal memory provided by the embodiments of the present invention.

That is, theprocessing unit 16 implements, when executing the program,: grouping the bad ICs according to the types and bad areas of the bad ICs; selecting two groups of bad ICs from the groups A, B, C, D and E, selecting at least 2 bad ICs from one selected group, selecting at least 1 bad IC from the other selected group, and dividing an IC bit area of an address line position in the bad ICs according to the grouping of the bad ICs and a preset rule; and adjusting the layout of the PCB of the X16 IC single crystal package according to the IC position area and the type of the bad IC.

In an embodiment of the present invention, the present invention further provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the method for repairing a single crystal memory by using a single crystal memory as provided in all embodiments of the present application:

that is, the program when executed by the processor implements: grouping the bad ICs according to the types and bad areas of the bad ICs; selecting two groups of bad ICs from the groups A, B, C, D and E, selecting at least 2 bad ICs from one selected group, selecting at least 1 bad IC from the other selected group, and dividing an IC bit area of an address line position in the bad ICs according to the grouping of the bad ICs and a preset rule; and adjusting the layout of the PCB of the X16 IC single crystal package according to the IC position area and the type of the bad IC.

Any combination of one or more computer-readable media may be employed. The computer readable medium may be a computer-readable storage medium or a computer-readable signal medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPOM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

Computer program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the healthcare worker computer, partly on the healthcare worker computer, as a stand-alone software package, partly on the healthcare worker computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the healthcare worker's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider). The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.

While preferred embodiments of the present application have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the true scope of the embodiments of the application.

Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.

The method, the apparatus, and the device for repairing a single crystal memory provided by the present application are introduced in detail, and a specific example is applied in the present application to explain the principle and the implementation manner of the present application, and the description of the above embodiment is only used to help understand the method and the core idea of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.