Detailed Description
As can be seen from the background art, the semiconductor structure formed at present has the problem of poor performance.
According to analysis, in a traditional radio frequency LDMOS structure in a FINFET technology, a well region and a drift region are both composed of fin structures, because of the three-dimensional characteristic of the fin structures of the drift region, a silicon/oxide interface region (3D structure) of the drift region is much higher than that of a planar radio frequency LDMOS structure, hot carriers are generated due to impact ionization under the action of high-pressure stress due to the fact that the silicon/oxide interface is larger, the probability of being trapped in defects of interface states is increased, drain current is reduced, and HCI fault problems often exist in the LDMOS structure, so that the reliability performance of an LDMOS device is reduced.
In order to improve the reliability of the LDMOS device, the doping concentration of the drift region can be reduced to reduce the electric field, so that hot carriers generated during high-voltage stress are reduced, the drain current is reduced, and the device can pass an HCI test. But at the same time, the drift region resistance increases, resulting in reduced conductivity and reduced Radio Frequency (RF) performance.
In order to improve the reliability of an LDMOS device and not affect the RF performance, the embodiment of the invention provides an LDMOS device and a forming method thereof, wherein the forming method comprises the following steps:
providing a base, wherein adjacent well regions and drift regions are formed in the base, the well regions comprise a first substrate and first fin portions protruding out of the first substrate, the drift regions comprise a second substrate, and the top surfaces of the second substrate are flush with the top surfaces of the first fin portions;
and forming an oxide layer on the first substrate exposed by the first fin portion, wherein the height of the oxide layer is lower than that of the first fin portion.
According to the method for forming the LDMOS device, the first fin portion protruding out of the first substrate is formed in the well region, the second substrate flush with the top surface of the first fin portion is formed in the drift region, when the oxide layer used for isolating the device is formed between the first fin portions, the contact surface of the substrate and the oxide layer is the silicon/oxide interface, and the second substrate is not provided with the fin portion, so that the oxide layer used for isolating the device is not required to be formed on the second substrate.
In order to make the above objects, features and advantages of the embodiments of the present invention more comprehensible, a detailed description of specific embodiments of the present invention is provided below with reference to the accompanying drawings.
Fig. 1 to 11 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention. The following describes a semiconductor structure provided by an embodiment of the present invention in detail with reference to the accompanying drawings.
Referring to fig. 1 and 2, wherein fig. 1 is a schematic view of fig. 2 along the AA' direction;
referring to fig. 1 and 2, a base 10 is provided, in which a well region 101 and a drift region 102 are formed, the well region 101 includes a first substrate 100 and a first fin 201 protruding from the first substrate 100, and the drift region 102 includes a second substrate 200, and a top surface of the second substrate 200 is flush with a top surface of the first fin 201;
the substrate 10 is used to provide a process platform for the subsequent formation of semiconductor structures.
In this embodiment, the substrate 10 is made of silicon. In other embodiments, the substrate may be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may be made of other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates. The material of the substrate may be a material suitable for process requirements or easy integration.
A well region 101 and a drift region 102 are formed in the substrate, wherein the drift region 102 has first type ions therein, and the well region 101 has second type ions therein, and the first type ions and the second type ions have different conductive types.
The well region 101 and the drift region 102 are in contact, the well region 101 acts as a lateral diffusion region to form a channel having a concentration gradient, and the drift region 102 is used to withstand a large partial pressure.
Specifically, in this embodiment, when the semiconductor structure is used to form an NLDMOS, the first type ion is an N type ion, the N type ion includes one or more of a phosphorus ion, an arsenic ion, and an antimony ion, the second type ion is a P type ion, and the P type ion includes one or more of a boron ion, a gallium ion, and an indium ion.
When the semiconductor structure is used for forming PLDMOS, the first type ion is a P type ion, the P type ion comprises one or more of boron ion, gallium ion and indium ion, the second type ion is an N type ion, and the N type ion comprises one or more of phosphorus ion, arsenic ion and antimony ion.
In this embodiment, the substrate 10 is a unitary structure, which is beneficial to simplifying the process flow.
The base 10 of the well region is patterned to form a first substrate 100 and a first fin protruding from the first substrate 100. Meanwhile, the base of the drift region that is not etched serves as the second substrate 200.
Specifically, the forming step of the first fin 201 includes:
forming a fin mask layer (not shown) on the substrate 10;
forming a shielding layer, wherein the shielding layer covers the fin mask layer corresponding to the drift region;
and patterning the substrate corresponding to the well region exposed by the shielding layer by taking the fin mask layer and the shielding layer as masks, so as to form a first substrate 100 and a discrete first fin 201 protruding out of the first substrate 100.
In this embodiment, the shielding layer covers the fin mask layer corresponding to the drift region, so that when the substrate 100 of the well region is etched in a subsequent process to form a first substrate and a discrete first fin 201 protruding above the first substrate, etching of the substrate material of the drift region is avoided to form a second substrate 200 flush with the top surface of the first fin 201.
In this embodiment, the fin mask layer is made of silicon nitride, and may be formed by CVD (Chemical Vapor Deposition ) process. In other embodiments, the fin mask layer may be made of one or more of silicon oxide, silicon carbide, silicon carbonitride, silicon oxycarbonitride, and silicon oxynitride.
In this embodiment, the material of the shielding layer is different from the material of the fin mask layer, and the material of the shielding layer is amorphous carbon, and in other embodiments, the material of the shielding layer may also be an ODL material or a DARC material.
The first fin 201 is used to provide a channel of a fin field effect transistor subsequently.
In this embodiment, the material of the first fin 201 is silicon, and since the first fin 201 and the first substrate 100 are obtained by etching an integrated substrate, the material of the first substrate 100 is also a silicon substrate. In other embodiments, the material of the first substrate may be germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or other materials, and the first substrate may be a silicon-on-insulator substrate or another type of substrate such as a germanium-on-insulator substrate.
It should be noted that, because the first substrate of the well region, the first fin portion and the second substrate of the drift region are implemented in one patterning process, the base of the drift region is not etched due to the shielding by the shielding layer, and therefore, the top surface of the first fin portion formed in this step is flush with the top surface of the second substrate.
That is, in this step, the first substrate 100 and the discrete first fin 201 protruding from the first substrate 100 are formed by etching the integrated base, and the unetched region serves as the second substrate.
In this embodiment, the substrate 10 is patterned by Self-aligned double patterning (Self-Aligned Double Patterning, SADP) or Self-aligned quad patterning (Self-Aligned Quadruple Patterning, SADP), so as to facilitate improving the pattern density and precision of the first fin 201, and realizing smaller-period pattern imaging.
Of course, the surface layer of the base may include at least one semiconductor material layer, and the first fin 201 and the first substrate 100 are obtained by etching the same semiconductor material layer. The first fin 201 is made of the same material as the first substrate 100, and in this embodiment, the material of the first fin 201 is silicon. The top surface of the unetched semiconductor material layer serves as the top surface of the second substrate. In other embodiments, the material of the base may be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the base may also be a silicon substrate on an insulator or other types of base such as a germanium substrate on an insulator, and the semiconductor material layer may be a silicon substrate on an insulator or a germanium substrate.
Specifically, the substrate may further include a first semiconductor material layer and a second semiconductor material layer located on the first semiconductor material layer, where the first semiconductor material layer is used to provide a process basis for subsequently forming the first substrate, and the second semiconductor material layer is used to provide a process basis for subsequently forming the first fin portion, so as to achieve the purpose of precisely controlling the formation height of the subsequently formed first fin portion.
The second semiconductor material layer may be silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, or a stack of a plurality of the above materials. The material of the first semiconductor material layer is silicon, germanium, silicon carbide, gallium arsenide, gallium indium arsenide or other materials, and the first semiconductor material layer can also be a silicon substrate on an insulator or a germanium substrate on an insulator or other types of substrates, in some specific implementations, the first semiconductor material layer can be the same material as the second semiconductor material layer, and those skilled in the art can choose according to actual needs.
Specifically, the forming of the first fin may include:
forming a fin mask layer on the substrate;
Forming a shielding layer, wherein the shielding layer covers the fin mask layer corresponding to the drift region;
and patterning the second semiconductor material layer corresponding to the well region exposed by the shielding layer by taking the fin mask layer and the shielding layer as masks to form a first fin, and taking the first semiconductor material layer under the first fin as a first substrate. The top surface of the unetched second semiconductor material layer serves as the top surface of the second substrate.
The first fin 201 is made of the same material as the first substrate 100, and in this embodiment, the material of the first fin 201 is silicon.
Next, referring to fig. 3, fig. 3 is a schematic view of fig. 2 in the DD' direction. An oxide layer 109 is formed on the first substrate 100 where the first fin 201 is exposed, and the height of the oxide layer 109 is lower than the height of the first fin 201.
After the plurality of parallel first fin portions are formed, an oxide layer is further formed on the top surface of the first substrate exposed by the first fin portions, so that the first substrate and the device structure on the first substrate are isolated. The material of the oxide layer 109 is silicon dioxide.
The method for forming the LDMOS device does not need to form an oxide layer for isolating the device because the fin parts are not formed on the second substrate, and the second substrate of the drift region is set to be a planar structure, so that the oxide layer for isolating the fin structure is not formed on the second substrate.
Next, referring to fig. 4 and 5, fig. 4 is a schematic diagram of the view of fig. 3, and fig. 5 is a cross-sectional view of the view of fig. 1, a gate structure is formed on the substrate at the junction of the well region and the drift region, the gate structure spans the first fin, and the gate structure covers a portion of the first fin and a portion of the drift region and the oxide layer along the extending direction of the first fin.
And in the extending direction along the first fin part, the gate structure covers part of the first fin part and part of the drift region, and as the coverage area of the gate structure on the drift region is increased, the maximum electric field between the drift region and the channel is reduced, the number of carriers is reduced, and the stability of the device is improved. On the other hand, as the gate structure increases in area coverage of the drift region, the capacitance between the gate structure and the drain increases, and the RF performance of the device decreases. Therefore, in order to balance the stability and RF performance of the device, the gate structure and the drift region may overlap in the extending direction along the first fin portion, and the overlapping size of the gate structure and the drift region may depend on the specific process and performance requirements.
Specifically, as shown in fig. 5, in the present embodiment, the step of forming the gate structure 103 includes:
First, a gate dielectric material layer (not shown) is formed on the first and second substrates 100 and 200, the gate dielectric material layer covering the first and second substrates 100 and 200;
depositing a gate material layer on the gate dielectric material layer, wherein the gate material layer covers the gate dielectric material layer;
the gate material layer and the gate dielectric material layer are patterned to form a gate dielectric layer 1031 and a gate layer 1032 on the gate dielectric layer, where the gate dielectric layer 1031 and the gate layer 1032 form the gate structure 103.
In this embodiment, the process of patterning the gate material layer and the gate dielectric material layer is a dry etching process. The dry etching process has anisotropic etching characteristics and good etching profile control, and is beneficial to enabling the morphology of the gate structure 103 to meet process requirements.
In this embodiment, the gate dielectric layer 1031 is silicon oxide, and the gate layer 1032 is polysilicon. In other embodiments of the present invention, the gate dielectric layer may also be silicon nitride, silicon oxynitride, silicon oxycarbide, or a high-k gate dielectric material. The gate layer may be a metal gate material such as Al, cu, ag, au, pt, ni, ti, co or W.
With continued reference to fig. 5, in this embodiment, the step of forming the gate structure 103 further includes: and forming a side wall 110 covering the gate dielectric layer and the side wall of the gate electrode layer. The sidewalls 110 are respectively located on two opposite sidewalls of the gate dielectric layer and the gate electrode layer. In the process of forming the semiconductor structure, the side wall 110 protects the side walls of the gate dielectric layer and the gate layer, and the side wall 110 is also used for defining a forming region of the source region.
The process steps for forming the side wall 110 include: and forming a side wall material layer (not shown in the figure) which conformally covers the substrate, the gate layer and the gate dielectric layer, and removing the side wall material layer at the top of the gate layer and the top of the substrate by adopting an etching process to form a side wall 110.
In this embodiment, the material of the sidewall 110 is silicon oxide. In other embodiments of the present invention, the material of the sidewall may be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride oxide, silicon oxynitride, boron nitride and boron carbonitride.
Of course, in other embodiments, the gate structure may be formed by forming a dummy gate structure, forming a sidewall, removing the dummy gate structure, and depositing the conductive gate.
In the process of forming the first fin portion, when the first fin portion is transited to the planar second substrate from the three-dimensional first fin portion, in order to facilitate process control, the reliable connection of the junction of the first fin portion of the well region and the second substrate of the drift region is improved, meanwhile, in order to enhance the control of the grid structure on the channel, in the process of forming the first fin portion, the second fin portion can be formed in the drift region at the same time, so that the grid structure spans the first fin portion and the second fin portion, the grid structure can control ultrathin bodies (fin portions) from at least two sides, and compared with a planar MOSFET, the grid structure has stronger control capability on the channel and can well inhibit short channel effect.
Therefore, referring to fig. 6, in a specific embodiment, the drift region further includes a third substrate and a second fin protruding from the third substrate, the second fin is connected to the first fin, a top surface of the second fin is flush with a top surface of the first fin, an extension direction of the second fin is the same as an extension direction of the first fin, the third substrate is located between the first substrate and the second substrate, and the second fin is located between the first fin and the second substrate.
It should be noted that, to simplify the process, the substrate is a unitary structure. And forming a first substrate, a first fin part protruding out of the first substrate, a second substrate, a third substrate and a second fin part protruding out of the third substrate by etching the base.
The second fin portion is connected with the first fin portion, namely the first fin portion and the second fin portion are in contact and extend in the same direction, and the drift region close to one side of the well region is etched while the substrate of the well region is etched, so that the first fin portion and the second fin portion are formed simultaneously.
As shown in fig. 6, a region I indicates a region where the well region is located, a region ii indicates a region where the drift region is located, and the drift region includes the second substrate 200, the third substrate 300, and the second fin 202 protruding from the third substrate 300.
Specifically, to simplify the process and ensure the connection between the first fin 201 and the second fin 202, the first fin 201 and the second fin 202 may be formed simultaneously, and the steps of forming the first fin 201 and the second fin 202 include:
forming a fin mask layer (not shown) on the substrate;
forming a shielding layer (not shown), wherein the shielding layer covers part of the fin mask layer corresponding to the drift region, and the shielding layer is positioned on a substrate at one side of the drift region away from the well region;
And patterning the well region exposed by the shielding layer and the substrate corresponding to the drift region by taking the fin mask layer and the shielding layer as masks to form a first substrate 100, a discrete first fin 201 protruding from the first substrate 100, a discrete third substrate 300 and a discrete second fin 202 protruding from the third substrate 300.
In another embodiment, the substrate may further include a first semiconductor material layer and a second semiconductor material layer located on the first semiconductor material layer, so as to achieve the purpose of precisely controlling the heights of the subsequent first fin portion and the second fin portion.
Forming a fin mask layer (not shown) on the substrate;
forming a shielding layer (not shown), wherein the shielding layer covers part of the fin mask layer corresponding to the drift region, and the shielding layer is positioned on a substrate at one side of the drift region away from the well region;
and patterning the well region exposed by the shielding layer and the second semiconductor material layer corresponding to the drift region by taking the fin mask layer and the shielding layer as masks to form a first fin portion positioned in the well region and a second fin portion positioned in the drift region, wherein the first semiconductor material layer under the first fin portion is used as a first substrate, and the first semiconductor material layer under the second fin portion is used as a third substrate.
Of course, when the drift region further includes a third substrate and a second fin portion protruding from the third substrate, an oxide layer is formed on the first substrate exposed by the first fin portion, and at the same time, an oxide layer is also formed on the third substrate exposed by the second fin portion.
Referring to fig. 7 in conjunction with fig. 6, fig. 7 is a cross-sectional view taken along the direction BB' in fig. 6. When the drift region includes the second fin 202 and the second substrate 200 that is flush with the second fin 202, the gate structure 103 spans the first fin 201 and the second fin 202, and in a direction extending along the first fin 201, the gate structure 103 covers a portion of a sidewall and a top surface of the first fin 201 and at least a portion of a sidewall and a top surface of the second fin 202, and the oxide layer.
The gate structure covers at least part of the side wall and the top surface of the second fin portion, which means that the gate structure in the drift region may cover part of the second fin portion or may completely cover the second fin portion in the extending direction along the first fin portion.
In this embodiment, in order to facilitate processing, in the step of forming the first fin portion and the second fin portion, the gate structure in the drift region covers a portion of the second fin portion, that is, the gate structure spans the first fin portion and the second fin portion. Therefore, the gate structure completely spans the first fin portion and the second fin portion, the control capability of the gate structure on a channel is improved, and short channel effect can be well restrained. L in fig. 5 indicates the dimension of the second fin along the extension direction of the first fin. It can be seen that the gate structure covers part of the second fin. By forming the second fin part, part of which is not covered by the grid electrode structure, in the drift region, the process control can be facilitated, and the connection reliability of the joint of the second fin part and the second substrate can be improved.
Referring to fig. 8, after forming the gate structure 103, the method further includes:
a drain region 105 is formed on a side of the drift region 102 remote from the gate structure 103.
A source region 104 may be formed in the well region 101 at the same time as the drain region 105 is formed. Of course, in other embodiments, the source and drain regions may also be formed prior to forming the gate structure. The source region 104 and the drain region 105 provide stress to the channel during operation of the semiconductor structure, increasing the mobility of carriers in the channel.
In this embodiment, the source region 104 is formed in the well region 101 of the preset region and the drain region 105 is formed in the drift region 102 of the preset region through a mask, so as to avoid doping ions into other regions of the first substrate 100 and other regions of the second substrate 200.
Specifically, the source region 104 is located in the well region 101 at one side of the gate structure 103, and the source region 104 is doped with first type ions; the drain region 105 is located in the drift region 102 at the other side of the gate structure 103, and the drain region 105 is doped with first type ions; the doping ion type in the drain region 105 and the source region 104 is the same as the doping ion type in the drift region 102.
In this embodiment, the semiconductor structure is an NLDMOS, and the first type ions in the source region 104 and the drain region 105 are N type ions. In other embodiments, when the semiconductor structure is a PLDMOS, the first type ions in the source and drain regions are P-type ions, respectively.
With continued reference to fig. 8, in this embodiment, the method for forming a semiconductor structure further includes: and doping second type ions into the top end of the well region exposed by the gate structure 103 by adopting an ion implantation mode to form a doped region 106, wherein the doped region 106 is positioned on one side of the source region 104 away from the gate structure 103. The ion implantation has the characteristics of simple operation, low process cost and the like.
The order in which the source region 104, the drain region 105, and the doped region 106 are formed is not limited.
Referring to fig. 9 to 11, after forming the gate structure 103, the method further includes:
forming an isolation layer between the gate structure and the drain region, wherein the isolation layer covers part of the gate structure and the substrate of the drift region;
the isolation layer 107 is used to avoid subsequent conductive structures 108 from directly contacting the gate structure 103.
The spacer layer conformally covers the gate structure 103 and the substrate between the gate structure 103 and the conductive structure. In this way, during the subsequent filling of the conductive structure 108, a short circuit caused by the direct contact between the conductive structure 108 and the gate structure 103 can be avoided.
The step of forming the isolation layer 107 includes:
forming an isolation material layer (not shown) on the substrate, the isolation material layer covering the substrate and the gate structure, respectively;
And removing part of the isolation material layer, and forming the isolation layer between the gate structure and the drain region.
In this embodiment, the isolation layer is a metal silicide blocking layer, so that the metal silicide is prevented from being formed in a partial region by utilizing the characteristic that the metal silicide blocking layer does not react with metals such as titanium or cobalt. In this embodiment, the material of the isolation layer is silicon oxide.
A conductive structure 108 (shown in fig. 11) is formed on the isolation layer on a side remote from the drain region 105, the conductive structure 108 covering a portion of the gate structure 103 in a direction along which the first fin extends (i.e., in the X direction in fig. 11).
When the semiconductor device is powered on, the conductive structure 108 (shown in fig. 11) forms a longitudinal electric field (Y direction in fig. 11) with the drift region 102, which can reduce the carrier concentration of the drift region, so that the width of the depletion region increases, the maximum electric field of the drift region decreases, and the stability of the device is further improved.
Before forming the conductive structure 108 after the forming of the isolation layer 107, further includes:
an interlayer dielectric layer 130 is formed on the substrate, and the interlayer dielectric layer 130 covers the substrate and the isolation layer 107.
The interlayer dielectric layer 130 is used for providing a process platform for the subsequent formation of the conductive structure, and the conductive structure is electrically isolated from other electrical connection structures through the interlayer dielectric layer 130. Therefore, the material of the interlayer dielectric layer 130 is a dielectric material.
In this embodiment, the material of the interlayer dielectric layer 130 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer may be another dielectric material such as silicon nitride or silicon oxynitride.
As shown in fig. 9, the step of forming the interlayer dielectric layer 130 includes: forming a layer of dielectric material (not shown) over the substrate and gate structure 103; and carrying out planarization treatment on the dielectric material layer to form an interlayer dielectric layer 130.
Referring to fig. 10 and 11, the step of forming the conductive structure includes:
etching the interlayer dielectric layer to form a first groove 121 exposing the interlayer dielectric layer;
and filling conductive materials in the first grooves 121 to form the conductive structures.
The conductive structure is made of a metal material or metal silicide.
A conductive structure 108 is formed in the interlayer dielectric layer 130, and a bottom end of the conductive structure 108 is in contact with the isolation layer 107.
The material of the conductive structure is a metallic material. In this embodiment, the material of the conductive structure 108 is tungsten (W). In other embodiments, the material of the conductive structure may also be a conductive material such as Al, cu, ag, or Au.
In this embodiment, the conductive material is filled using an electrochemical plating process. The electrochemical plating process has the advantages of simple operation, high deposition speed, low cost and the like.
In this embodiment, the first trench 121 is formed by etching the interlayer dielectric layer 130 by a dry etching process. The dry etching process has anisotropic etching characteristics and good etching profile control, is favorable for enabling the morphology of the first trench 121 to meet the process requirements, and is also favorable for improving the removal efficiency of the interlayer dielectric layer 130. The top of the isolation layer can be an etching stop position in the dry etching process, so that the damage to other film structures is reduced.
Of course, while forming the first trench 121 exposing the isolation layer, a first via 122 may be formed by etching the interlayer dielectric layer 130, where the first via 122 exposes the doped region 106, the source region 104, the drain region 105, or the gate structure 103, respectively;
The first through hole 122 is filled with a conductive material to form contact plugs 120, and each contact plug 120 is a source electrode electrically connected to the source region, a drain electrode electrically connected to the drain region, a gate electrode electrically connected to the gate structure, and a ground electrode electrically connected to the doped region.
Correspondingly, the embodiment of the invention also provides an LDMOS device, and referring to FIG. 11, a schematic cross-sectional structure of the semiconductor structure of the embodiment is shown. Fig. 12 is a top view of an LDMOS device; fig. 11 is a sectional view of fig. 12 along the direction CC'.
As shown in fig. 11 and 12, the LDMOS device provided in the embodiment of the invention includes:
a base 10, in which an adjacent well region 101 and a drift region 102 are disposed, where the well region includes a first substrate 100 and a first fin 201 protruding from the first substrate 100, and the drift region 102 includes a second substrate 200, and a top surface of the second substrate 200 is flush with a top surface of the first fin 201;
and an oxide layer disposed on the first substrate 100 exposed by the first fin 201, wherein the height of the oxide layer is lower than the height of the first fin 201.
In this embodiment, the substrate 10 is made of silicon. In other embodiments, the substrate may be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may be made of other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates. The material of the substrate may be a material suitable for process requirements or easy integration.
Of course, the surface layer of the base may include at least one semiconductor material layer, and the first fin 201 and the first substrate 100 are obtained by etching the same semiconductor material layer. The first fin 201 is made of the same material as the first substrate 100, and in this embodiment, the material of the first fin 201 is silicon. The top surface of the unetched semiconductor material layer serves as the top surface of the second substrate. In other embodiments, the material of the base may be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the base may also be a silicon substrate on an insulator or other types of base such as a germanium substrate on an insulator, and the semiconductor material layer may be a silicon substrate on an insulator or a germanium substrate.
Specifically, the substrate may further include a first semiconductor material layer and a second semiconductor material layer located on the first semiconductor material layer, where the first semiconductor material layer is used to provide a process basis for subsequently forming the first substrate, and the second semiconductor material layer is used to provide a process basis for subsequently forming the first fin portion, so as to achieve the purpose of precisely controlling the formation height of the subsequently formed first fin portion.
The second semiconductor material layer may be silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, or a stack of a plurality of the above materials. The material of the first semiconductor material layer is silicon, germanium, silicon carbide, gallium arsenide, gallium indium arsenide or other materials, and the first semiconductor material layer can also be a silicon substrate on an insulator or a germanium substrate on an insulator or other types of substrates, in some specific implementations, the first semiconductor material layer can be the same material as the second semiconductor material layer, and those skilled in the art can choose according to actual needs.
A well region 101 and a drift region 102 are formed in the substrate, wherein the drift region 102 has first type ions therein, and the well region 101 has second type ions therein, and the first type ions and the second type ions have different conductive types.
The well region 101 and the drift region 102 are in contact, the well region 101 acts as a lateral diffusion region to form a channel having a concentration gradient, and the drift region 102 is used to withstand a large partial pressure.
Specifically, in this embodiment, when the semiconductor structure is an NLDMOS, the first type ion is an N type ion, where the N type ion includes one or more of a phosphorus ion, an arsenic ion, and an antimony ion, and the second type ion is a P type ion, and the P type ion includes one or more of a boron ion, a gallium ion, and an indium ion.
When the semiconductor structure is PLDMOS, the first type ion is a P type ion, the P type ion comprises one or more of boron ion, gallium ion and indium ion, the second type ion is an N type ion, and the N type ion comprises one or more of phosphorus ion, arsenic ion and antimony ion.
In this embodiment, the substrate 10 is a unitary structure, which is beneficial to simplifying the process flow. In other embodiments, the substrate may further include a semiconductor material layer and a second semiconductor material layer located on the first semiconductor material layer, so as to achieve the purpose of precisely controlling the height of the subsequent first fin portion.
The first fin 201 is used to provide a channel of a fin field effect transistor. The first fin 201 and the first substrate 100 are obtained by etching the same semiconductor material layer. The first fin 201 is made of the same material as the first substrate 100, and in this embodiment, the material of the first fin 201 is silicon. The top surface of the unetched fin material layer serves as the top surface of the second substrate.
In this embodiment, the first substrate 100 and the second substrate 200 are silicon substrates. In other embodiments, the first substrate and the second substrate may also be substrates of other materials, such as a germanium substrate, a silicon carbide substrate, a gallium arsenide substrate, or an indium gallium arsenide substrate, and may also be substrates of other types, such as a silicon on insulator substrate or a germanium on insulator substrate.
According to the LDMOS device provided by the embodiment of the invention, the first fin part protruding out of the first substrate is arranged in the well region, the second substrate flush with the top surface of the first fin part is arranged in the drift region, the oxide layer used for isolating the device is formed between the first fin parts, the contact surface of the substrate and the oxide layer is the silicon/oxide interface, and the second substrate is not provided with the fin part, so that the oxide layer of the fin part is not required to be formed, and the second substrate is not provided with the oxide layer used for isolating the fin structure.
And the gate structure 103 is positioned on the substrate at the junction of the well region 101 and the drift region 102, the gate structure 103 spans across the first fin 201, and in the extending direction along the first fin, the gate structure covers part of the first fin and part of the drift region.
The drift region 102 may further include a third substrate 300 and a second fin 202 protruding from the third substrate 300, where the second fin 202 is connected to the first fin 201, a top surface of the second fin 202 is flush with a top surface of the first fin 201, and an extension direction of the second fin 202 and the first fin 201 (extending along an X direction in fig. 9) is the same, the third substrate 300 is located between the first substrate 100 and the second substrate 200, and the second fin 202 is located between the first fin 201 and the second substrate 200;
when the drift region 102 may further include a third substrate 300 and a second fin 202 protruding from the third substrate 300, the oxide layer is further disposed on the third substrate 300 where the second fin 202 is exposed.
As shown in fig. 12, a region i indicates a well region, a region ii indicates a drift region, and the drift region includes the second substrate 200, the third substrate 300, and the second fin 202 protruding from the third substrate 300.
When the drift region further comprises a third substrate and a second fin portion protruding out of the third substrate, the gate structure covers part of the side wall and the top surface of the first fin portion and part of the side wall and the top surface of the second fin portion in the extending direction along the first fin portion.
The gate structure covers at least part of the second fin portion, which means that the gate structure in the drift region may cover part of the sidewall and the top surface of the second fin portion in the extending direction along the first fin portion, or may be that the gate structure in the drift region completely covers the sidewall and the top surface of the second fin portion.
In this embodiment, for convenience in processing, the gate structure in the drift region covers a portion of the sidewall and the top surface of the second fin, that is, the gate structure spans the first fin and the second fin. L in fig. 10 indicates the dimension of the second fin along the extension direction of the first fin. It can be seen that the gate structure covers part of the sidewalls and top surface of the second fin.
The gate structure includes a gate dielectric layer 1031, a gate layer 1032 over the gate dielectric layer, and a sidewall spacer 110 covering sidewalls of the gate dielectric layer and the gate layer.
The sidewalls 110 are respectively located on two opposite sidewalls of the gate dielectric layer and the gate electrode layer. The side wall 110 protects the side walls of the gate dielectric layer and the gate layer, and the side wall 110 is also used for defining a formation region of the source region.
In this embodiment, the gate dielectric layer 1031 is silicon oxide, and the gate layer 1032 is polysilicon. In other embodiments of the present invention, the gate dielectric layer may also be silicon nitride, silicon oxynitride, silicon oxycarbide, or a high-k gate dielectric material. The gate layer may be a metal gate material such as Al, cu, ag, au, pt, ni, ti, co or W.
In this embodiment, the sidewall 110 is silicon oxide. In other embodiments of the present invention, the sidewall may be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.
A source region 104 is located in the well region 101 at one side of the gate structure 103, and first type ions are doped in the source region 104; the drain region 105 is positioned in the drift region 102 at one side far away from the gate structure, and the drain region 105 is doped with first type ions; the doping ion type in the drain region 105 and the source region 104 is the same as the doping ion type in the drift region 102. Doped region 106 is located on a side of the source region 104 remote from the gate structure 103. The source region 104 and the drain region 105 provide stress to the channel during operation of the semiconductor structure, increasing the mobility of carriers in the channel.
In this embodiment, the semiconductor structure is an NLDMOS, and the first type ions in the source region 104 and the drain region 105 are N type ions. In other embodiments, when the semiconductor structure is a PLDMOS, the first type ions in the source and drain regions are P-type ions, respectively.
A conductive structure 108 located in the drift region on a side remote from the drain region 105, the conductive structure 108 covering a portion of the gate structure.
The material of the conductive structure is a metallic material. In this embodiment, the material of the conductive structure 108 is tungsten (W). In other embodiments, the material of the conductive structure may also be a conductive material such as Al, cu, ag, or Au.
When the semiconductor device is powered on, the conductive structure 108 (shown in fig. 11) forms a longitudinal electric field (Y direction in fig. 11) with the drift region 102, which can reduce the carrier concentration of the drift region, so that the width of the depletion region increases, the maximum electric field of the drift region decreases, and the stability of the device is further improved.
An isolation layer 107 is located between the gate structure and the conductive structure to avoid direct contact of the conductive structure 108 with the gate structure 103.
The isolation layer 107 conformally covers the gate structure 103 and the substrate between the gate structure 103 and the conductive structure, so as to avoid a short circuit caused by direct contact between the conductive structure 108 and the gate structure 103.
In this embodiment, the isolation layer 107 is a metal silicide blocking layer, so as to prevent the formation of metal silicide in a partial region by utilizing the characteristic that the metal silicide blocking layer does not react with metals such as titanium or cobalt. In this embodiment, the material of the isolation layer is silicon oxide.
The interlayer dielectric layer 130 is used for providing a process platform for the subsequent formation of the conductive structure, and the conductive structure is electrically isolated from other electrical connection structures by the interlayer dielectric layer 130. Therefore, the material of the interlayer dielectric layer 130 is a dielectric material.
In this embodiment, the material of the interlayer dielectric layer 130 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer may be another dielectric material such as silicon nitride or silicon oxynitride.
The contact plugs 120 formed in the interlayer dielectric layer 130, each contact plug 120 is a source electrode electrically connected to the source region, a drain electrode electrically connected to the drain region, a gate electrode electrically connected to the gate structure, and a ground electrode electrically connected to the doped region.
Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the embodiments of the invention, and the scope of the embodiments of the invention should be pointed out in the appended claims.