CN114036889A

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Info

Publication number: CN114036889A
Application number: CN202111268380.3A
Authority: CN
Inventors: 张凯
Original assignee: Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Current assignee: Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Priority date: 2021-10-29
Filing date: 2021-10-29
Publication date: 2022-02-11
Anticipated expiration: 2041-10-29
Also published as: CN114036889B

Abstract

The invention discloses a layout design method of an edge unit of a standard cell library, which comprises the following steps: determining basic parameters of edge units according to the basic parameters of a corresponding standard unit library and a minimum design rule in a design rule file provided by a tape-out manufacturer; designing the edge unit according to the basic parameters and layout design rules of the edge unit, wherein the edge unit specifically comprises six edge units, namely a first edge unit, a second edge unit, a third edge unit, a fourth edge unit, a fifth edge unit and a sixth edge unit; and thirdly, when the layout of the edge unit is designed at the digital back end, reasonably inserting the edge unit into the outer edge of the IP module, thereby realizing P-well isolation. The invention optimizes the design and development process of the standard cell library, can realize the horizontal splicing of the standard cells of different device types, and improves the rear-end design efficiency of the digital circuit.

Description

Layout design method for edge unit of standard cell library

Technical Field

The invention relates to the field of semiconductor manufacturing, in particular to a layout design method of an edge unit of a standard cell library.

Background

In the FDSOI (Fully Depleted-Silicon-On-Insulator) process, a Silicon, insulating layer and Silicon substrate structure mode is adopted in the manufacturing process of an integrated circuit, so that the parasitic capacitance of a device is greatly reduced, and the performance of the device is improved. Under the FDSOI process, the adjustment of the device performance can be realized by changing the potential of the P/N well. In order to isolate the P-Well (P-Well) and adjust the potential of the P-Well to avoid its failure due to conduction with the substrate, an N-Well (N-Well) Guard Ring (Guard-Ring)102 needs to be added at the periphery of theIP block 101, as shown in fig. 1. Since the protection ring size is related to the IP block size, it is necessary to customize the corresponding protection ring for different IP blocks.

Disclosure of Invention

In view of the above situation, in order to overcome the defects of the prior art, the present invention provides a layout design method for edge cells of a standard cell library.

The invention solves the technical problems through the following technical scheme: a layout design method for an edge unit of a standard cell library is characterized by comprising the following steps:

determining basic parameters of edge units according to the basic parameters of a corresponding standard unit library and a minimum design rule in a design rule file provided by a tape-out manufacturer;

designing the edge unit according to the basic parameters and layout design rules of the edge unit, wherein the edge unit specifically comprises six edge units, namely a first edge unit, a second edge unit, a third edge unit, a fourth edge unit, a fifth edge unit and a sixth edge unit;

and thirdly, when the layout of the edge unit is designed at the digital back end, reasonably inserting the edge unit into the outer edge of the IP module, thereby realizing P-well isolation.

Preferably, the basic parameters of the standard cell library include: a first cell height, a first power bus width, a first ground bus width, a first Poly horizontal wiring pitch, a first P/N region boundary, a first N-well edge; the basic parameters of the edge unit include: a second cell height, a second power bus width, a second ground bus width, a second Poly horizontal wiring pitch, a second P/N region boundary, and a second N-well edge.

Preferably, the second cell height is the same as the relative height of all standard cells within the corresponding library of standard cells.

Preferably, the second power bus width is the same as the first power bus width for all of the standard cells within the corresponding standard cell library, and the second ground bus width is the same as the first ground bus width for all of the cells within the corresponding standard cell library.

Preferably, the second Poly horizontal wiring pitch is a centerline distance of two adjacent Poly, which is determined by a design rule of a process platform.

Preferably, the second P/N region boundary is a boundary position of the PMOS region and the NMOS region of the edge cell, and the position of the second P/N region boundary is the same as a relative position of all standard cells in the corresponding standard cell library, the relative position being a position with respect to the origin.

Preferably, the second N-well borderline is a centerline distance between two adjacent N-well borderlines.

The positive progress effects of the invention are as follows: the invention optimizes the design and development process of the standard cell library, can realize the horizontal splicing of the standard cells of different device types, and improves the rear-end design efficiency of the digital circuit.

Drawings

Fig. 1 is a schematic structural diagram of a prior art N-well protection ring added on the periphery of an IP block.

Fig. 2A to fig. 2F are schematic structural diagrams of six edge units according to the present invention.

FIG. 3 is a schematic layout diagram of an edge cell according to the present invention.

FIG. 4 is a layout diagram of a first edge cell according to the present invention.

FIG. 5 is a layout diagram of a second edge cell according to the present invention.

FIG. 6 is a layout diagram of a third edge cell according to the present invention.

FIG. 7 is a layout diagram of a fourth edge cell according to the present invention.

Fig. 8 is a schematic layout diagram of a fifth edge cell in the present invention.

FIG. 9 is a schematic layout diagram of a sixth edge cell according to the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.

The layout design method of the standard cell library edge cell comprises the following steps:

step two, designing the edge unit according to the basic parameters and layout design rules of the edge unit, specifically, six edge units, as shown in fig. 2A to fig. 2F, namely afirst edge unit 1, asecond edge unit 2, athird edge unit 3, afourth edge unit 4, afifth edge unit 5 and asixth edge unit 6;

and thirdly, when the layout of the edge unit is designed at the digital back end, reasonably inserting the edge unit into the outer edge of theIP module 101, thereby realizing P-well isolation, as shown in FIG. 3.

Wherein, the basic parameters of the standard cell library comprise: a first cell height, a first power bus width, a first ground bus width, a first Poly horizontal wiring pitch, a first P/N region boundary, a first N-well edge; the basic parameters of the edge unit include: the second unit height, the second power bus width, the second ground bus width, the second Poly horizontal wiring pitch, the second P/N region boundary, and the second N-well border are convenient to correspond.

The second cell height is the same as the relative height of all standard cells in the corresponding library of standard cells, which is the height relative to the origin.

The width of the second power bus is the same as that of the first power bus of all the standard units in the corresponding standard unit library, and the width of the second ground bus is the same as that of the first ground bus of all the units in the corresponding standard unit library, so that the matching use is convenient.

The second Poly horizontal wiring pitch is the centerline distance of two adjacent Poly (polysilicon) lines, and is determined by the design rule of the process platform.

The second P/N region boundary is a boundary position of the PMOS region and the NMOS region of the edge cell, and the position of the second P/N region boundary is the same as a relative position of all standard cells in the corresponding standard cell library, the relative position being a position with respect to the origin.

The second N-well borderline is a centerline distance between two adjacent N-well borderlines, and is determined by a design rule (design rule) of the process platform.

As shown in FIG. 4, it can be seen from FIG. 4 that in the layout of the first edge cell in the embodiment of the present invention, Deep N-Well covers the entire edge cell, the PMOS region is covered by the N-Well layer, and the NMOS region is covered by the P-Well layer. The design rule limitation shown in the figure is to ensure that the unit layout can be checked through the design rule after automatic splicing according to the minimum design rule and the half minimum rule (collectively referred to as a general rule D) provided by the wafer foundry. The embodiment is suitable for the upper edge and the lower edge of the IP module, and the inner side of the IP module can be spliced with the NMOS of the P substrate in the vertical direction.

As shown in FIG. 5, it can be seen from FIG. 5 that in the layout of the second edge cell in the embodiment of the present invention, Deep N-Well covers the entire edge cell, the NMOS region is covered by the N-Well layer, and the PMOS region is covered by the P-Well layer. The design rule limitation shown in the figure is to ensure that the unit layouts can be checked through the design rules after automatic splicing according to the minimum design rules and half of the minimum rules provided by the wafer foundry. The embodiment is suitable for the upper edge and the lower edge of the IP module, and the inner side of the IP module can be vertically spliced with the PMOS of the P substrate.

As shown in FIG. 6, it can be seen from FIG. 6 that in the layout of the third edge cell in the embodiment of the present invention, Deep N-Well covers the whole edge cell, the left half of the PMOS region and the NMOS region are covered by the N-Well layer, and the right half of the NMOS region is P-Well. The design rule limitation shown in the figure is to ensure that the unit layouts can be checked through the design rules after automatic splicing according to the minimum design rules and half of the minimum rules provided by the wafer foundry. The embodiment is suitable for the left edge and the right edge of an IP module, and the inner side of the IP module can be spliced with standard units of a P substrate NMOS and an N substrate PMOS in the horizontal direction; corner Boundary cells (Corner Boundary cells) are also possible.

As shown in FIG. 7, it can be seen from FIG. 7 that in the layout of the fourth edge cell in the embodiment of the present invention, Deep N-Well covers the whole edge cell, the left half of the NMOS region and the PMOS region are covered by the N-Well layer, and the right half of the PMOS region is P-Well. The design rule limitation shown in the figure is to ensure that the unit layouts can be checked through the design rules after automatic splicing according to the minimum design rules and half of the minimum rules provided by the wafer foundry. The embodiment is suitable for the left edge and the right edge of an IP module, and the inner side of the IP module can be spliced with standard units of an N substrate NMOS and a P substrate PMOS in the horizontal direction; may also be used as corner edge elements.

As shown in FIG. 8, it can be seen from FIG. 8 that in the layout of the fifth edge cell in the embodiment of the present invention, Deep N-Well covers the entire edge cell, and both the PMOS region and the NMOS region are covered by the N-Well layer. The design rule limitation shown in the figure is to ensure that the unit layouts can be checked through the design rules after automatic splicing according to the minimum design rules and half of the minimum rules provided by the wafer foundry. The embodiment is suitable for the upper edge and the lower edge of a module, and can be spliced with NMOS of an N substrate or PMOS of the N substrate in the vertical direction; the embodiment is simultaneously suitable for the left edge and the right edge of the IP module, and can be spliced with standard units of an N substrate NMOS and an N substrate PMOS in the horizontal direction; may also be used as corner edge elements.

As shown in fig. 9, it can be seen from fig. 9 that, in the layout of the sixth edge cell in the embodiment of the present invention, Deep N-Well covers the entire edge cell, the left half of the PMOS region and the left half of the NMOS region are covered by the N-Well layer, and the right half of the PMOS region and the right half of the NMOS region are P-Well. The design rule limitation shown in the figure is to ensure that the unit layouts can be checked through the design rules after automatic splicing according to the minimum design rules and half of the minimum rules provided by the wafer foundry. The embodiment is suitable for the left edge and the right edge of the IP module, and the inner side of the IP module can be spliced with standard cells of a P substrate NMOS and a P substrate PMOS in the horizontal direction.

By the edge unit layout design method provided by the above embodiment, the layout height of the edge unit is consistent with the height of the corresponding standard unit. Through horizontal and vertical mirror image, the inner sides of the edge units can be normally adjacent to the corresponding standard units, P-well isolation in the whole module is realized, the design and development process of a standard unit library is optimized, and the rear-end design efficiency of the digital circuit is improved.

The above-mentioned embodiments are preferred embodiments of the present invention, and the present invention is not limited thereto, and any other modifications or equivalent substitutions that do not depart from the technical spirit of the present invention are included in the scope of the present invention.

Claims

1. A layout design method for an edge unit of a standard cell library is characterized by comprising the following steps:

2. The layout design method of the edge cell of the standard cell library as claimed in claim 1, wherein the basic parameters of the standard cell library include: a first cell height, a first power bus width, a first ground bus width, a first Poly horizontal wiring pitch, a first P/N region boundary, a first N-well edge; the basic parameters of the edge unit include: a second cell height, a second power bus width, a second ground bus width, a second Poly horizontal wiring pitch, a second P/N region boundary, and a second N-well edge.

3. The method of claim 2, wherein the second cell height is the same as the relative height of all standard cells in the corresponding standard cell library.

4. The method of claim 2, wherein the second power bus width is the same as the first power bus width of all standard cells in the corresponding standard cell library, and the second ground bus width is the same as the first ground bus width of all cells in the corresponding standard cell library.

5. The layout design method of an edge cell of a standard cell library as claimed in claim 2, wherein the second Poly horizontal wiring distance is a centerline distance of two adjacent Poly, determined by design rules of a process platform.

6. The layout design method of an edge cell of a standard cell library as claimed in claim 2, wherein the second P/N region boundary is a boundary position of a PMOS region and an NMOS region of the edge cell, and the position of the second P/N region boundary is the same as a relative position of all standard cells in the corresponding standard cell library, the relative position being a position with respect to an origin.

7. The layout design method of a standard cell library edge cell according to claim 2, wherein the second N-well borderline is a centerline distance between two adjacent N-well borderlines.