Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Accordingly, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims (the claims) and their equivalents.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
The embodiments provided by the embodiments of the present invention may be combined with each other without contradiction.
Fig. 1 is a schematic diagram of a display panel according to an embodiment of the present invention, where, as shown in fig. 1, the display panel includes a display area AA, the display area AA includes an optical component setting area AA1, and the display area AA includes a plurality of light emitting devices, and the optical component setting area AA1 includes a first light emitting device (not labeled in fig. 1). When the display device is assembled, the optical member is disposed at a position corresponding to the optical member disposition area AA 1. In use, ambient light can penetrate the optic-set area AA1 to be received by the optic. The shape, position, and number of the optical member placement areas AA1 in fig. 1 are shown only schematically, and are not intended to limit the present invention.
The display panel includes a plurality of pixel circuits for driving the light emitting devices in the display area AA to emit light. Fig. 2 is a schematic diagram of a film structure of a display panel according to an embodiment of the present invention, and as shown in fig. 2, the display panel includes a substrate 10, and a first metal layer 11 and a second metal layer 12 disposed on the same side of the substrate 10. The pixel circuit 2 may include a first type transistor 1T and a second type transistor 2T, among others. In the embodiment of the invention, the pixel circuit 2 comprises two types of transistors, and the transistors are divided according to different film layers of the grid electrode of the transistors. The first gate 1g of the first type transistor 1T is located in the first metal layer 11 and the second gate 2g of the second type transistor 2T is located in the second metal layer 12.
It should be noted that, in fig. 2, only the first metal layer 11 is illustrated on the side of the second metal layer 12 away from the substrate 10, and in some embodiments, the first metal layer 11 may be located on the side of the second metal layer 12 close to the substrate 10. In addition, in fig. 2, the first type transistor 1T and the second type transistor 2T are shown as top gate structures, and the type of each transistor in the pixel circuit is not limited in the embodiment of the present invention, and each transistor may be a bottom gate structure, or a portion of each transistor may be a top gate structure, or a portion of each transistor may be a bottom gate structure.
The display panel further comprises a first semiconductor layer 13 and a second semiconductor layer 14 located above the substrate 10. Wherein the active layer of the first type transistor 1T is located in the first semiconductor layer 13 and the active layer of the second type transistor 2T is located in the second semiconductor layer 14. The active layer of the first type transistor 1T and the active layer of the second type transistor 2T are located at different layers. In one embodiment, the first type transistor 1T further includes a third gate electrode 3g, and the first gate electrode 1g and the third gate electrode 3g are located on both sides of the first semiconductor layer 13, respectively.
Also illustrated in fig. 2 is a light emitting device 1, the light emitting device 1 comprising a first electrode a, a light emitting layer b and a second electrode c arranged in a stack. The light emitting device 1 is electrically connected to the pixel circuit 2 through the connection electrode 31.
In the embodiment of the present invention, the pixel circuit 2 includes a first pixel circuit. The first pixel circuit comprises a transistor 1T of the first type and a transistor 2T of the second type described above. The first pixel circuit is electrically connected to the first light emitting device in the optical member setting area AA1, that is, the first pixel circuit is for driving the first light emitting device to emit light. The display panel further includes a functional metal located in the first metal layer 11, the functional metal being insulated from the first gate electrode 1g of the first pixel circuit.
In the display panel provided by the embodiment of the invention, the first light emitting device is arranged in the optical component setting area, and the first pixel circuit is electrically connected with the first light emitting device, so that the optical component setting area can display image information, and the integrity of the image displayed by the display panel is ensured. The transistors of the pixel circuit comprise two types, the grid electrodes of the two types of transistors are positioned on different metal layers, and the types of the transistors can be designed differently according to the functions of the transistors in the pixel circuit so as to improve the driving performance of the pixel circuit. The functional metal and the first grid electrode of the first type transistor are arranged on the first metal layer, the functional metal and the first grid electrode are mutually insulated, the functional metal and the first grid electrode are manufactured in the same process, the utilization of the first metal layer is realized, and the integration level of the display panel is increased. In some embodiments, the functional metal is connected to the transistor in the first pixel circuit, and the voltage drop of the transmission voltage signal is reduced by using the functional metal, so that the brightness difference between the brightness of the optical component setting area and other display areas is improved, and the overall display uniformity of the display panel is improved. In other embodiments, the functional metal is connected to a transistor in the first pixel circuit, and the functional metal is used as a part of signal lines in the display panel, so that circuit wiring in the first pixel circuit can be more tightly distributed, the first pixel circuit is arranged in the optical component arrangement region, the light transmittance of the optical component arrangement region can be increased, and the first pixel circuit is arranged in the transition region, so that the area of the transition region can be reduced, and the ratio of the transition region to the optical component arrangement region in the whole display region can be reduced.
In some embodiments, the first semiconductor layer 13 is a first metal oxide semiconductor layer, i.e., the first semiconductor layer 13 comprises a metal oxide semiconductor, such as indium gallium zinc oxide, and the second semiconductor layer 14 is a second silicon semiconductor layer, i.e., the second semiconductor layer 14 comprises silicon, such as low temperature polysilicon.
Fig. 3 is a schematic diagram of a pixel circuit in a display panel according to an embodiment of the invention, where, as shown in fig. 3, the pixel circuit includes a driving transistor Tm, a data writing transistor T1, a threshold compensation transistor T2, a gate reset transistor T3, an electrode reset transistor T4, a first light emitting control transistor T5, a second light emitting control transistor T6, and a storage capacitor Cst. Fig. 3 also illustrates the first scan signal C1, the second scan signal C2, the third scan signal C3, the light emission control signal E, the power supply voltage signal P, the first reset signal Ref1, the second reset signal Ref2, and the Data signal Data.
Wherein the gate of the driving transistor Tm is connected to the first node N1, the first pole of the driving transistor Tm is connected to the second node N2, the second pole of the driving transistor Tm is connected to the third node N3, and the driving transistor Tm is configured to generate a driving current under the control of the gate voltage thereof. A gate of the gate reset transistor T3 may receive the second scan signal C2, a first pole of the gate reset transistor T3 may receive the second reset signal Ref2 to be electrically connected, a second pole of the gate reset transistor T3 may be connected to the first node N1, and the gate reset transistor T3 may be used to reset a gate of the driving transistor Tm. A gate of the Data writing transistor T1 may receive the first scan signal C1, a first pole thereof may receive the Data signal Data, and a second pole thereof may be connected to the second node N2. The gate of the threshold compensation transistor T2 may receive the third scan signal C3, a first pole thereof may be connected to the third node N3, and a second pole thereof may be connected to the first node N1. The data writing transistor T1 may be used to write a data signal to the gate of the driving transistor Tm, and the threshold compensation transistor T2 may be used to self-check and compensate the threshold voltage of the driving transistor Tm. The gate of the first light emission control transistor T5 and the gate of the second light emission control transistor T6 may each receive the light emission control signal E, a first pole of the first light emission control transistor T5 may be connected to the power supply voltage signal P, a second pole of the first light emission control transistor T5 may be connected to the second node N2, a first pole of the second light emission control transistor T6 may be connected to the third node N3, and a second pole of the second light emission control transistor T6 may be connected to the fourth node N4. A gate of the electrode reset transistor T4 may receive the first scan signal C1, a first electrode of the electrode reset transistor T4 may be connected to the first reset signal Ref1, a second electrode of the electrode reset transistor T4 may be connected to the fourth node N4, a first electrode of the light emitting device 1 may be connected to the fourth node N4, and a second electrode of the light emitting device 1 may receive a second power signal (not shown in fig. 3).
In one embodiment, the threshold compensation transistor T2 and the gate reset transistor T3 are both the first type transistor 1T, and the remaining transistors are both the second type transistor 2T. The active layers of the threshold value compensation transistor T2 and the gate reset transistor T3 comprise metal oxide semiconductors, so that the drain currents of the threshold value compensation transistor T2 and the gate reset transistor T3 in the off state are relatively small, when the pixel circuit works in the light-emitting stage, the drain currents of the threshold value compensation transistor T2 and the gate reset transistor T3 to the grid electrode of the driving transistor Tm can be reduced, the potential of the grid electrode of the driving transistor can be stabilized, the problem of flicker of a display panel picture is solved, and the display effect is improved.
In another embodiment, the threshold compensation transistor T2 is a first type transistor 1T, and the remaining transistors in the pixel circuit are all second type transistors 2T.
In another embodiment, the gate reset transistor T3 is a first type transistor 1T, and the remaining transistors in the pixel circuit are all second type transistors 2T.
In addition, a first pole of the electrode reset transistor T4 is connected to the first reset signal Ref1, and a first pole of the gate reset transistor T3 is connected to the second reset signal Ref2. Optionally, the first reset signal Ref1 and the second reset signal Ref2 reset the first electrode of the light emitting device 1 and the gate of the driving transistor Tm, respectively, and the voltage of the first reset signal Ref1 is set to be smaller than the voltage of the second reset signal Ref2. By providing a higher reset voltage to the gate of the driving transistor Tm, the faster the threshold of the gate of the driving transistor Tm is grasped, the shorter the time of grasping the gate threshold of the driving transistor Tm when applied to high-frequency display or low-brightness (or gray-scale) display, and the faster the threshold of the gate of the driving transistor Tm is grasped, the more accurate the threshold grasping, so that display unevenness can be reduced, and simultaneously, the lower reset voltage is provided to the first electrode of the light emitting device 1, so that the lighting of the light emitting device 1 can be reduced, and the low-gray-scale display effect can be improved.
In some embodiments, the first pixel circuit is located in the optical component placement area. Fig. 4 is a schematic diagram of a portion of an optical component arrangement area of a display panel according to an embodiment of the invention, and as shown in fig. 4, a first pixel circuit 201 is located in the optical component arrangement area AA1. The first light emitting device includes a first red light emitting device 101r, a first green light emitting device 101g, and a first blue light emitting device 101b. The first light emitting devices of the three colors are arranged into one pixel unit, and the first pixel circuits 201 respectively connected with the first light emitting devices of the three colors are correspondingly arranged below the pixel unit. The arrangement of the first light emitting device 101 in fig. 4 is only schematically shown and is not a limitation of the present invention.
In some embodiments, fig. 5 is a schematic partial view of another display panel according to an embodiment of the present invention, as shown in fig. 5, the display panel further includes a transition area AA2 and a conventional display area AA3, where the transition area AA2 is adjacent to the optical component arrangement area AA1, and the transition area AA2 is located between the optical component arrangement area AA1 and the conventional display area AA 3. The first pixel circuit 201 is located in the transition area AA2. A second light emitting device 102 and a second pixel circuit 202 are disposed in the transition area AA2, and the second pixel circuit 202 is electrically connected to the second light emitting device 102. The third light emitting device 103 is disposed in the conventional display area AA3, and a pixel circuit (not shown in fig. 5) for driving the third light emitting device 103 is also disposed in the conventional display area AA 3. In one embodiment, the arrangement density of the second light emitting devices 102 in the transition area AA2 is the same as the arrangement density of the first light emitting devices 101 in the optical member arrangement area AA 1. In another embodiment, the arrangement density of the second light emitting devices 102 in the transition area AA2 is greater than the arrangement density of the first light emitting devices 101 in the optical member arrangement area AA 1. In one embodiment, the arrangement density of the third light emitting device 103 in the conventional display area AA3 is the same as the arrangement density of the first light emitting device 101 in the optical member arrangement area AA1, wherein the light emitting area of the first light emitting device 101 may be smaller than the light emitting area of the third light emitting device 103 for the same color. In one embodiment, the arrangement density of the third light emitting devices 103 in the conventional display area AA3 is greater than the arrangement density of the first light emitting devices 101 in the optical member arrangement area AA 1.
In some embodiments, the second type of transistor 2T in the first pixel circuit comprises a first functional transistor, a first pole of the first functional transistor receiving a constant voltage signal during an operational phase of the first pixel circuit, wherein the functional metal is electrically connected to the first pole of the first functional transistor. In one embodiment, the functional metal and the original signal line for transmitting the constant voltage signal are connected to the first pole of the first functional transistor, for example, in parallel, so that the voltage drop for transmitting the constant voltage signal can be reduced. In another embodiment, the functional metal replaces the original signal line for transmitting the constant voltage signal to be electrically connected with the first electrode of the first functional transistor, so that the circuit wiring in the first pixel circuit can be compactly distributed.
In an embodiment, fig. 6 is a schematic diagram of a first pixel circuit in a display panel according to an embodiment of the invention. FIG. 7 is a schematic cross-sectional view taken at the location of line A-A' in FIG. 6. As shown in fig. 6, the first functional transistor G1 is an electrode reset transistor T4, that is, the first functional transistor G1 is used for resetting a first electrode of a first light emitting device (not labeled in fig. 6), and a second electrode of the first functional transistor G1 is connected to the first electrode of the first light emitting device.
The display panel comprises a first reset signal line Vref1, wherein the first reset signal line Vref1 is used for providing a first reset signal Ref1, the first reset signal Ref1 is a constant voltage signal, and a first pole of the first functional transistor G1 is electrically connected with the first reset signal line Vref 1. The first reset signal line Vref1 and the functional metal M0 are located at different layers, and the functional metal M0 is electrically connected to the first reset signal line Vref 1. The functional metal M0 illustrated in fig. 6 is electrically connected to the first reset signal line Vref1 through the first connection line L1.
In fig. 6 and the following drawings, structures located on the same film layer are filled with the same pattern.
The embodiment provides that the functional metal M0 is electrically connected to the first reset signal line Vref1, i.e., the functional metal M0 is electrically connected to the first electrode of the electrode reset transistor T4 in the first pixel circuit. The functional metal M0 can reduce the voltage drop for transmitting the first reset signal, and improve the brightness difference between the brightness of the optical component setting area and other display areas, so that the overall display uniformity of the display panel is improved.
Fig. 6 also illustrates a data line Vdata, a first scan line S1, a light emission control line Emit, and a power supply voltage signal line PV1 of the display panel. The data line Vdata is used for providing a data signal, the first scan line S1 is used for providing a first scan signal C1, the emission control line Emit is used for providing an emission control signal E, and the power supply voltage signal line PV1 is used for providing a power supply voltage signal P. Also illustrated in FIG. 6 are second scan lines S2-1 and S2-2, and third scan lines S3-1 and S3-2. The second scan line is used for providing a second scan signal C2, and the third scan line is used for providing a third scan signal C3. Wherein the second scan line S2-1 and the second scan line S2-2 are located at different layers, and the third scan line S3-1 and the third scan line S3-2 are located at different layers. Alternatively, the second scan line S2-1 and the third scan line S3-1 are located on the same layer, and the second scan line S2-2 and the third scan line S3-2 are located on the same layer. The arrangement of the second scan line S2-1 and the second scan line S2-2 causes the threshold compensation transistor T2 to form a structure of upper and lower double gates. Similarly, the gate reset transistor T3 has a structure of upper and lower double gates.
With continued reference to fig. 6, the first reset signal line Vref1 extends in the first direction X, and the display panel further includes a first gate line X1 extending in the first direction X, the first gate line X1 is located on the first metal layer 11, and a part of line segments in the first gate line X1 are multiplexed into the first gate 1g. In the embodiment of the invention, the second scan line S2-1 and the third scan line S3-1 are both the first gate line X1, a part of the line segments in the second scan line S2-1 are multiplexed to the first gate 1g of the gate reset transistor T3, and a part of the line segments in the third scan line S3-1 are multiplexed to the first gate 1g of the threshold compensation transistor T2. As shown in fig. 7, the threshold compensation transistor T2 further includes a third gate 3g, a portion of the line segment of the third scan line S3-2 is multiplexed into the third gate 3g of the threshold compensation transistor T2, the first gate 1g and the third gate 3g are respectively located at two sides of the first semiconductor layer 13, and the threshold compensation transistor T2 forms a structure with upper and lower double gates. As can be seen from fig. 6 and 7, the gate reset transistor T3 also includes a first gate 1g and a third gate 3g, and the gate reset transistor T3 has a structure of upper and lower double gates.
As can be seen from fig. 6, two functional metals M0 adjacent in the second direction y are connected by a first connection line L1, the second direction y crosses the first direction X, and the first connection line L1 crosses the first gate line X1 in an insulating manner. Through setting up first connecting wire L1 so that two adjacent functional metal M0 in second direction y can transmit the same signal to realize that functional metal M0 and first grid line X1 are mutual insulating, then functional metal M0 and first grid 1g all are located first metal layer 11, and functional metal and first grid make in same technology process, realize the utilization to first metal layer, increase display panel integrated level.
In addition, the second light-emitting control transistor T6 is a second type transistor 2T, and as can be seen from fig. 7, the second light-emitting control transistor T6 includes a second gate electrode 2g, and the second gate electrode 2g is located in the second metal layer 12.
As shown in fig. 6, the display panel further includes a second reset signal line Vref2 extending in the first direction x, the second reset signal line Vref2 being for providing a second reset signal Ref2, the second reset signal Ref2 being a constant voltage signal. In the first pixel circuit, the second functional transistor G2 is used to reset the gate of the driving transistor Tm, that is, the second functional transistor G2 is the gate reset transistor T3. The first pole of the second functional transistor G2 is electrically connected to the second reset signal line Vref2, and the second pole of the second functional transistor G2 is electrically connected to the gate of the driving transistor Tm. This embodiment sets the first reset signal line Vref1 and the second reset signal line Vref2 in the circuit wiring that drives the first light emitting device in the optical component setting region AA1 to emit light. The first reset signal line Vref1 supplies the first reset signal Ref1, the second reset signal line Vref2 supplies the first reset signal Ref2, the first pole of the electrode reset transistor T4 is connected to the first reset signal line Vref1, and the first pole of the gate reset transistor T3 is connected to the second reset signal line Vref2. In the first pixel circuit operation phase, the first electrode of the first light emitting device is reset by the first reset signal Ref1, and the gate of the driving transistor Tm is reset by the second reset signal Ref2. By providing a higher reset voltage to the gate of the driving transistor Tm, the faster the threshold of the gate of the driving transistor Tm is grasped, the shorter the time of grasping the gate threshold of the driving transistor Tm when applied to high-frequency display or low-brightness (or gray-scale) display, and the faster the threshold of the gate of the driving transistor Tm is grasped, the more accurate the threshold grasping, so that display unevenness can be reduced, and simultaneously, a lower reset voltage is provided to the first electrode of the light emitting device 1, the lighting of the light emitting device can be reduced, and the low-gray-scale display effect can be improved. This embodiment can improve the display effect of the optical member installation area AA 1.
As seen in fig. 6 and 7, the display panel further includes a third metal layer 15, a fourth metal layer 16 and a fifth metal layer 17, wherein the third metal layer 15 is located on a side of the fourth metal layer 16 close to the substrate 10, and the fifth metal layer 17 is located on a side of the fourth metal layer 16 remote from the substrate 10. The first connection line L1 and the first reset signal line Vref1 are connected to each other and are both located at the fourth metal layer 16, and the second reset signal line Vref2 is located at the third metal layer 15. Wherein the data line Vdata and the power voltage signal line PV1 are located in the fifth metal layer 17. In this embodiment, the first reset signal line Vref1 and the second reset signal line Vref2 that are disposed in the same extension direction are located in different layers, so that the total number of signal lines disposed in the same metal layer can be reduced, which is beneficial to reducing the space occupied by the whole first pixel circuit. In the case where the first pixel circuit is located in the optical member setting area AA1, the area of the light transmitting area of the optical member setting area AA1 can be increased. In the case where the first pixel circuit is located in the transition region, it can be advantageous to reduce the area of the transition region, thereby reducing the duty ratio of the transition region and the optical member setting region in the entire display region.
In another embodiment, fig. 8 is a schematic diagram of a first pixel circuit in a display panel according to an embodiment of the invention. FIG. 9 is a schematic cross-sectional view taken at the line B-B' of FIG. 8.
As shown in fig. 8, the functional metal M0 is electrically connected to a first pole of a first functional transistor G1, and the first functional transistor G1 is connected in series with a driving transistor Tm for supplying a power supply voltage signal to the first pole of the driving transistor Tm, that is, the first functional transistor G1 is a first light emitting control transistor T5. A first pole of the first functional transistor G1 is electrically connected to the power supply voltage signal line PV 1.
As can be seen from fig. 8 and 9, the power voltage signal line PV1 and the functional metal M0 are located in different layers, wherein the power voltage signal line PV1 is located in the fifth metal layer 17, the functional metal M0 is located in the first metal layer 11, and the functional metal M0 and the power voltage signal line PV1 are electrically connected through the via hole of the insulating layer. Also illustrated in fig. 9 is the storage capacitor Cst having a first plate located on the second metal layer 12 and a second plate located on the third metal layer 15. The display panel is further provided with a fourth connection line L4 located on the fourth metal layer 16, the second pole of the threshold compensation transistor T2 is connected to the first pole plate of the storage capacitor through the fourth connection line L4, and the first pole plate located on the second metal layer 12 is multiplexed to be the gate of the driving transistor Tm.
In this embodiment, the functional metal M0 is electrically connected to the power supply voltage signal line PV1, and the functional metal M0 is electrically connected to the first electrode of the first light emitting control transistor T5. The functional metal M0 can reduce the voltage drop of the transmission power supply voltage signal, and improve the brightness difference between the brightness of the optical component setting area and other display areas, thereby improving the overall display uniformity of the display panel.
In another embodiment, fig. 10 is a schematic diagram of a first pixel circuit in a display panel according to an embodiment of the invention. In fig. 10, two first pixel circuits are shown, and as shown in fig. 10, the storage capacitor Cst of the first pixel circuit includes a first electrode plate B1 and a second electrode plate B2, the first electrode plate B1 is multiplexed as a gate electrode of the driving transistor Tm, adjacent second electrode plates B2 in the first direction x are electrically connected to each other, and adjacent second electrode plates B2 are electrically connected to each other to form a power supply voltage signal line PV1 extending in the first direction x. The display panel further comprises a second connecting line L2 and a third connecting line L3, wherein the functional metal M0 is electrically connected with the second electrode plate B2 through the second connecting line L2, and the functional metal M0 is electrically connected with the first electrode of the first functional transistor G1 through the third connecting line L3. In one embodiment, the second connection line L2 and the third connection line L3 are located at the same layer and are connected to each other. In this embodiment, the second plates B2 adjacent to each other in the first direction x are electrically connected to each other to form a power supply voltage signal line PV1 extending in the first direction x, and the functional metal M0 is provided to be electrically connected to the first electrode of the first functional transistor G1. According to the embodiment, the original power supply voltage signal line extending in the second direction y can be removed, and the adjacent second plates B2 are connected with each other to transmit the power supply voltage signal, so that the whole transmission of the power supply voltage signal is ensured. The functional metal M0 for transmitting the power supply voltage signal is arranged on the first metal layer, so that the utilization of the first metal layer is realized, the power supply voltage signal line extending in the second direction y is reduced, the occupied width of the first pixel circuit in the first direction x can be compressed to a certain extent, and the occupied panel of the first pixel circuit is reduced. In the case where the first pixel circuit is located in the optical member setting area AA1, the area of the light transmitting area of the optical member setting area AA1 can be increased. In the case where the first pixel circuit is located in the transition region, it can be advantageous to reduce the area of the transition region, thereby reducing the duty ratio of the transition region and the optical member setting region in the entire display region.
In one embodiment, the second connection line L2 and the third connection line L3 are located at the same layer as the fourth connection line L4. In connection with the above description of the metal layers in the display panel in fig. 7 and 9, the display panel further comprises a third metal layer 15 and a fourth metal layer 16, the third metal layer 15 being located on a side of the fourth metal layer 16 close to the substrate 10. The first electrode plate B1 is located on the second metal layer 12, the second electrode plate B2 is located on the third metal layer 15, and the second connection line L2 and the third connection line L3 are located on the fourth metal layer 16.
In another embodiment, fig. 11 is a schematic partial view of an optical component arrangement area of another display panel according to an embodiment of the present invention, and fig. 11 is a schematic top view, in which the top view is the same as the direction perpendicular to the substrate 10. As can be seen from fig. 11, the functional metal M0 overlaps with at least part of the wiring lines in the first pixel circuit 21 in the direction perpendicular to the substrate. The routing gap refers to a gap between two adjacent wires, wherein the two adjacent wires can be routing wires in different film layers or routing wires in the same film layer. In this embodiment, the functional metal M0 may be used as a light shielding layer, and in the under-screen optical component scheme, the light is received by the optical component after penetrating through the optical component setting area AA1, and the light diffraction is caused by the routing gap in the pixel circuit to affect the performance of the optical component. The functional metal M0 and the first gate electrode 1g are both located in the first metal layer 11, and the light shielding layer made of the functional metal M0 is used to shield at least part of the wiring lines in the first pixel circuit 21, so that in the scheme that the first pixel circuit 21 is located in the optical component installation area AA1, when light penetrates through the optical component installation area AA1, diffraction can be reduced, and optical performance of the optical component can be improved. In addition, the functional metal M0 is manufactured by utilizing the original film layer in the display panel, the functional metal M0 can be manufactured in the same process with the first grid electrode 1g, the simplified process is realized, and the etching process of the shading layer is not required to be additionally added.
In fig. 11, the shape of the functional metal M0 is schematically shown, and the present invention is not limited thereto. In one embodiment the edges of the functional metal M0 are curved.
In one embodiment, the display panel includes a second semiconductor layer 14, a second metal layer 12, a third metal layer 15, a first semiconductor layer 13, a first metal layer 11, a fourth metal layer 16, and a fifth metal layer 17 stacked in this order over a substrate 10, as in the display panel film structure illustrated in fig. 7. In the embodiment of the present invention, the functional metal M0 is located in the first metal layer 11, and when the functional metal layer M0 is fabricated as a light shielding layer, the functional metal M0 needs to be patterned to avoid part of the via hole in the first pixel circuit 21, such as the connection via hole V1 between the fourth metal layer 16 and the second semiconductor layer 14 illustrated in fig. 11.
Fig. 12 is a schematic diagram of a display device according to an embodiment of the present invention, and as shown in fig. 12, the display device includes a display panel 100 according to any embodiment of the present invention. The structure of the display panel 100 is already described in the above display panel embodiments, and will not be described here again. The display device in the embodiment of the invention can be any device with a display function, such as a mobile phone, a tablet computer, a notebook computer, an electronic paper book, a television, a smart watch and the like.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather to enable any modification, equivalent replacement, improvement or the like to be made within the spirit and principles of the invention.
It should be noted that the above embodiments are merely for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the above embodiments, it should be understood by those skilled in the art that the technical solution described in the above embodiments may be modified or some or all of the technical features may be equivalently replaced, and these modifications or substitutions do not deviate the essence of the corresponding technical solution from the scope of the technical solution of the embodiments of the present invention.