CN113971920A - Image display and its driving circuit - Google Patents

Abstract

An image display and a driving circuit thereof, the image display includes: a display panel; and a driving circuit coupled to the display panel, wherein the driving circuit updates an active area of the display panel in a normal mode, and alternately updates the active area and at least one inactive area of the display panel in an ultra-wide mode.

Description

Image display and driving circuit thereof

Technical Field

The invention relates to an image display and a driving circuit thereof.

Background

Image displays, such as liquid crystal displays, have the advantages of low radiation and low power consumption, and thus become the mainstream of the market.

By utilizing the GOA technology (Gate on Array), the Gate drive ICs on the left side and the right side of the panel are designed and manufactured on the glass substrate, so that the use number of the panel drive ICs can be greatly reduced, and the ultra-narrow frame design is achieved.

In addition, in the currently used operation mode, it has been proposed that the image display has a mode switch, which is switchable between a normal mode and a super-wide mode.

In the normal mode, the whole display screen is an active area (active area), and in the super-wide mode, the display screen is divided into an active area and an inactive area (also called a black area).

However, the current technical problem is how to reduce the leakage current to maintain the black frame in the inactive region; and how scanning from the active area can be conveniently achieved, rather than starting from the uppermost or lowermost portion of the entire screen.

In addition, it is also an effort in the industry to increase the frequency to match different resolutions according to the requirements of different operation modes. Therefore, it is one of the efforts in the industry to switch the operation mode, resolution and operation frequency without increasing the circuit cost.

Disclosure of Invention

According to an example of the present disclosure, there is provided an image display including: a display panel; and a driving circuit coupled to the display panel, wherein the driving circuit updates an active area of the display panel in a normal mode, and alternately updates the active area and at least one inactive area of the display panel in an ultra-wide mode.

According to another example of the present disclosure, there is provided a driving circuit of an image display, including: the driving units comprise a pull-up control circuit, a pull-up circuit, a pull-down control circuit and a pull-down circuit, wherein the pull-up control circuit is coupled to the pull-up circuit so as to control the pull-up circuit to pull up a current-stage output signal; the pull-down control circuit is coupled to the pull-down circuit to control the pull-down of the pull-down circuit to the output signal of the current stage, wherein the pull-up control circuit comprises a first transistor and a second transistor, and the first transistor receives a start trigger signal or a preceding stage start signal; the second transistor is coupled to a current stage start signal.

In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments is made with reference to the accompanying drawings:

drawings

Fig. 1A shows a functional block diagram of an image display according to a first embodiment of the present disclosure, fig. 1B shows a functional block diagram of a driving circuit of an image display according to a first embodiment of the present disclosure, and fig. 1C shows a circuit diagram of a driving circuit of an image display according to a first embodiment of the present disclosure.

Fig. 2A shows a circuit diagram of a pull-up control circuit according to a first embodiment of the disclosure. Fig. 2B shows another circuit diagram of the pull-down sub-circuit according to the first embodiment of the disclosure.

Fig. 3A-3C show several exemplary operations and signal waveforms according to a first embodiment of the present disclosure.

Fig. 4A to 4C show other update modes according to the first embodiment of the disclosure.

Fig. 5 shows a functional block diagram of a driving unit of a driving circuit of an image display according to a second embodiment of the present disclosure.

Fig. 6A to 6D show circuit architecture diagrams of an auxiliary pull-down control circuit, an auxiliary pull-down circuit and an auxiliary pull-up circuit according to a second embodiment of the disclosure.

FIG. 7 is a schematic diagram of a display panel according to a second embodiment of the disclosure.

Fig. 8A to 8E are signal waveform diagrams illustrating a scan start signal, a scan end signal and a turn-on signal for various operation modes according to a second embodiment of the disclosure.

Fig. 9A to 9E are signal waveform diagrams illustrating a scan start signal, a scan end signal and a turn-on signal for various operation modes according to a second embodiment of the disclosure.

Fig. 10A to 10E are signal waveform diagrams illustrating a scan start signal, a scan end signal and a turn-on signal used in various operation modes according to a second embodiment of the present disclosure.

Description of reference numerals:

10: image display

50: display panel

60: driving circuit

100: drive unit

110: pull-up control circuit

120: pull-up circuit

130: pull-down control circuit

140: pull-down circuit

130_1, 103_ 2: pull-down control sub-circuit

140_1 to 140_ 3: pull-down sub-circuit

C: capacitor with a capacitor element

T11-T12, T11-1, T11-2, T21, T32-T33, T41-T44, T51-T54, T61-T64: transistor with a metal gate electrode

G1, G256, G541, G1081, G1621, G1906, GM: drive unit

500: drive unit

510: pull-up control circuit

520: pull-up circuit

530: pull-down control circuit

540: pull-down circuit

550: auxiliary pull-down control circuit

560: auxiliary pull-down circuit

570: auxiliary pull-up circuit

T57, T58, T67, T68, T45, Txon, Txa, Txb: transistor with a metal gate electrode

B1-B6: display sub-region

Detailed Description

The technical terms in the specification refer to the common terms in the technical field, and if the specification explains or defines a part of the terms, the explanation of the part of the terms is based on the explanation or definition in the specification. Various embodiments of the present disclosure each have one or more technical features. One skilled in the art may selectively implement some or all of the features of any of the embodiments, or selectively combine some or all of the features of the embodiments, as may be implemented.

First embodiment

Fig. 1A shows a functional block diagram of an image display according to a first embodiment of the present disclosure, fig. 1B shows a functional block diagram of a driving circuit of an image display according to a first embodiment of the present disclosure, and fig. 1C shows a circuit diagram of a driving circuit of an image display according to a first embodiment of the present disclosure. Theimage display 10 includes adisplay panel 50 and a driving circuit 60 coupled to thedisplay panel 50. For example, but not limited thereto, thedisplay panel 50 may be a liquid crystal display panel (LCD panel), and the drivingcircuit 100 may be a Gate circuit (Gate circuit), for example, but not limited thereto, a GOA technology (Gate on Array). The driving circuit 60 includes a plurality of drivingunits 100, such as, but not limited to, gate driving units.

The drivingunit 100 includes: a pull-upcontrol circuit 110, a pull-upcircuit 120, a pull-down control circuit 130, and a pull-down circuit 140.

The pull-upcontrol circuit 110 is coupled to the pull-upcircuit 120 to control the pull-up of the pull-upcircuit 120 on the output signal g (n) of the present stage.

The pull-down control circuit 130 is coupled to the pull-down circuit 140 to control the pull-down of the pull-down circuit 140 to the output signal g (n) of the current stage.

As shown in fig. 1C, the pull-upcontrol circuit 110 includes: transistors T11-T12, and a capacitor C. The pull-upcircuit 120 includes: and a transistor T21.

The pull-down control circuit 130 includes: the pull-down control sub-circuits 130_1 and 103_ 2.

The pull-down control sub-circuit 130_1 includes: transistors T51-T54. The pull-down control sub-circuit 103_2 includes: transistors T61-T64.

The pull-down circuit 140 includes: the pull-down sub-circuits 140_1 to 140_ 3.

The pull-down sub-circuit 140_1 includes: and a transistor T41.

The pull-down sub-circuit 140_2 includes: transistors T32 and T42.

The pull-down sub-circuit 140_3 includes: transistors T33 and T43.

In FIG. 1C, Q (n), K (n), and P (n) are internal nodes. LC1 and LC2 are low frequency signals.

Fig. 2A shows a circuit diagram of the pull-upcontrol circuit 110 according to a first embodiment of the disclosure. Fig. 2B shows another circuit diagram of the pull-down sub-circuit 140_1 according to the first embodiment of the disclosure.

As shown in fig. 2A, the pull-upcontrol circuit 110 includes: the first transistor T11-1, the second transistor T12, and the third transistor T11-2, wherein the third transistor T11-2 is a selective device for reducing leakage current.

The first transistor T11-1 has three terminals respectively coupled to the operating voltage VGHD, the start trigger signal ST _ T or the previous stage start signal ST (n-8), and the internal node q (n). The third terminal of the second transistor T12 is coupled to the internal node hc (n), the internal node q (n) and the current stage start signal st (n), respectively. The third transistor T11-2 has three terminals respectively coupled to the operating voltage VGHD, the ground voltage VSS or the start trigger signal ST _ T, and the internal node q (n).

In more detail, taking the example that thedisplay panel 50 has a resolution 3840 (horizontal) × 2160 (vertical) as an example, for now, the display panel has 5 operation modes, as shown in table 1 below.

TABLE 1

Regarding the gate coupling relationship between the first transistor T11-1 and the third transistor T11-2, in the embodiment of the disclosure, in the 1 ST stage driving unit, the gate of the first transistor T11-1 is coupled to the start trigger signal ST _ T, and the gate of the third transistor T11-2 is coupled to the ground voltage VSS; in the 256 th, 541 ST, 1081 ST, 1621 th and 1906 th stage driving units, the gate of the first transistor T11-1 is coupled to the previous stage start signal ST (n-8), and the gate of the third transistor T11-2 is coupled to the start trigger signal ST _ T; in other stage driving units, the gate of the first transistor T11-1 is coupled to the previous stage start signal ST (n-8), and the gate of the third transistor T11-2 is coupled to the ground voltage VSS.

Unlike fig. 1C, as shown in fig. 2B, in another possible embodiment of the present disclosure, the pull-down sub-circuit 140_1 includes: a fourth transistor T41 and a fifth transistor T44.

The third terminal of the fourth transistor T41 is coupled to the post-stage start signal ST (n +8), the ground voltage VSS and the internal node q (n), respectively.

The third terminal of the fifth transistor T44 is coupled to the internal node q (n), the start reset signal ST _ R and the ground voltage VSS respectively.

In the embodiment of the present disclosure, for the 255 th, 540 th, 1080 th, 1620 th, 1905 th and 2160 th level driving units, (a) in theoperation mode 1, the pull-down is performed by the fourth transistor T41, and after the 2160 th level driving unit is activated, the fifth transistor T44 is reset; (B) in the other four operation modes, the fifth transistor T44 is responsible for pull-down, and after the last stage of the driving unit in the active or inactive region is activated, the fifth transistor T44 is reset, and the fourth transistor T41 is turned off. For the other stages of the driver cell, (A) in theoperation mode 1, the fourth transistor T41 is responsible for pull-down, and after the action of the 2160 stage of the driver cell, the fifth transistor T44 is reset; (B) in the other four operation modes, the fourth transistor T41 is responsible for pull-down, and the fifth transistor T44 is reset after the last stage of the driving unit in the active or inactive region is activated.

Fig. 3A-3C show several exemplary operations and signal waveforms according to a first embodiment of the present disclosure. FIG. 3A is applicable to the case of operation mode 1 (normal mode, active area: 1-2160, no inactive area). Fig. 3B and 3C are applicable to the case of operation modes 2-5 (ultra wide mode). In fig. 3A to 3C, G1 represents a 1 st-stage driving unit, G256 represents a 256 th-stage driving unit, and the like, GM represents an M-th-stage driving unit (M is a positive integer), and D represents display data. Taking all 2160 levels as an example, M is between 1 and 2160, but M ≠ 1, 256, 541, 1081, 1621, 1906.

As shown in fig. 3A, in thestage 1 driving unit G1, the start trigger signal ST _ T (L/S) from the shift register is pulled high, the start trigger signal ST _ T (L/S) is transmitted to thestage 1 driving unit G1 but not to other driving units, and the start trigger signal ST _ T (1) coupled to the gate of the first transistor T11-1 is triggered. The other start trigger signals ST _ T (2) to ST _ T (6) are held at a low level. The start reset signal ST _ R is activated after the 2160 th stage driving unit is finished.

Referring to FIG. 3B, the operation mode 2 (ultra wide mode, active area: 256-.

In the driving units G1, G256, and G1906, the start trigger signal ST _ T (L/S) from the shift register is pulled high. The start trigger signals ST _ T (L/S) are individually transmitted as start trigger signals ST _ T (1), ST _ T (2), and ST _ T (6), while the start trigger signals ST _ T (3) to ST _ T (5) are kept at a low level. The start reset signal ST _ R is activated after the driving units G255, G1905 and 2160 are finished.

In FIG. 3B, in thesuper-wide mode 2, during the update, the levels 1-255 of the inactive region are updated, then thelevels 1905 and 1906 of the active region are updated, and then thelevels 2160 and 1906 of the inactive region are updated. That is, in one frame, both the active area and the inactive area can be scanned and updated.

Fig. 3B can be applied to theoperation modes 3 to 5 of the ultra-wide mode as well, and the details thereof are not repeated here.

Referring to FIG. 3C, the operation mode 2 (ultra wide mode, active area: 256-.

In the driving units G1, G256, and G1906, the start trigger signal ST _ T (L/S) from the shift register is pulled high. The start trigger signals ST _ T (L/S) are individually transmitted as start trigger signals ST _ T (1), ST _ T (2), and ST _ T (6), while the start trigger signals ST _ T (3) to ST _ T (5) are kept at a low level. The start reset signal ST _ R is activated after the driving units G255, G1905 and 2160 are finished.

In FIG. 3C, in thesuper-wide mode 2, during the update, the levels 1-255 of the inactive region and thelevels 1906 and 2160 of the inactive region are updated simultaneously, and then thelevels 256 and 1905 of the active region are updated.

Fig. 3C can be applied to theoperation modes 3 to 5 of the ultra-wide mode as well, and the details thereof are not repeated here.

The refresh method of fig. 3B and 3C can also be referred to as alternately refreshing the active region and the inactive region.

Fig. 4A to 4C show other update modes according to the first embodiment of the disclosure.

In FIG. 4A, in thesuper-wide mode 2, when performing the update in every 6 frames (144Hz), the update sequence is the non-active area 1-255(1440Hz) (update 1 time), the active area (150Hz) (update 6 times) and thenon-active area 1906 and 2160(1440Hz) (update 1 time). In FIG. 4A, in the super-wide mode ofoperation mode 2, or in every 6 frames (144Hz), the update sequence is that the active area (150Hz) (update 6 times) and the inactive area (720Hz) (update 1 time), and the inactive areas 1-255 and 1906 + 2160 are updated synchronously.

Fig. 4A is equally applicable to theoperation mode 4 of the ultra-wide mode, the details of which are not repeated here.

In fig. 4B, in the super-widemode operation mode 3 and the super-widemode operation mode 5, the updating sequence is the inactive area (720Hz) and the active area (360Hz) when updating is performed in each 1 frame.

In each 6 frames (240Hz), the updating sequence is active area (360Hz) (updating 6 times) and inactive area (120Hz) (updating 1 time).

In the first embodiment of the present disclosure, by doing so, the conventional leakage problem that the inactive region cannot be maintained can be solved, and the scanning can be started in the middle section of the display panel.

Second embodiment

Fig. 5 shows a functional block diagram of adriving unit 500 of a driving circuit of an image display according to a second embodiment of the present disclosure. The driving circuit may be a gate circuit, such as but not limited to GOA. The driving circuit includes a plurality of drivingunits 500.

The drivingunit 500 includes: pull-up control circuit 510, pull-upcircuit 520, pull-down control circuit 530, pull-down circuit 540, auxiliary pull-down control circuit 550, auxiliary pull-down circuit 560, and auxiliary pull-upcircuit 570. The pull-up control circuit 510, pull-upcircuit 520, pull-down control circuit 530, and pull-down circuit 540 may be the same as or similar to the pull-upcontrol circuit 110, pull-upcircuit 120, pull-down control circuit 130, and pull-down circuit 140 of fig. 1, and therefore, the details thereof will not be repeated here.

The auxiliary pull-down circuit 560 is coupled to the pull-down circuit 540 for pulling down the internal node. The auxiliary pull-down control circuit 550 is coupled to the pull-down control circuit 530 for controlling the pull-down of the internal node.

The auxiliary pull-upcircuit 570 is used to control the pull-up of the stage output signal G (n).

Fig. 6A to 6D show circuit architecture diagrams of an auxiliary pull-down control circuit 550, an auxiliary pull-down circuit 560 and an auxiliary pull-upcircuit 570 according to a second embodiment of the disclosure.

As shown in fig. 6A, the auxiliary pull-down control circuit 550 includes: transistors T57, T58, T67, and T68. The gates of the transistors T57, T58, T67 and T68 all receive one of the turn-on signals Xon 1-6. One end of each of the transistors T57, T58, T67 and T68 is coupled to the internal nodes A (n), P (n), B (n) and K (n), respectively. The other terminals of the transistors T57, T58, T67 and T68 are coupled to the ground voltage VSS.

As shown in fig. 6B, the auxiliary pull-down circuit 560 includes: and a transistor T45. Three terminals of the transistor T45 are coupled to the internal node Q (n), one of the start signals ST 7-ST 12, and the ground voltage VSS, respectively.

As shown in fig. 6C, the auxiliary pull-upcircuit 570 includes: a transistor Txon. Three terminals of the transistor Txon are respectively coupled to the current stage output signal G (n) and one of the turn-on signals Xon 1-6.

As shown in fig. 6D, the auxiliary pull-upcircuit 570 includes: transistor Txa and transistor Txb. Three terminals of the transistor Txa are respectively coupled to the output signal g (n), one terminal of the transistor Txb and one of the turn-on signals Xon 1-6. The three terminals of the transistor Txb are respectively coupled to one terminal of the transistor Txa and one of the turn-on signals Xon 1-6.

FIG. 7 is a schematic diagram of a display panel according to a second embodiment of the disclosure. In the second embodiment of the present disclosure, the display panel is virtually partitioned into a plurality of display sub-regions, for example, taking the display panel having 2160 scan lines in the vertical direction as an example, the displayable panel is virtually partitioned into 6 display sub-regions B1-B6, wherein the display sub-regions B1-B6 are respectively driven by the driving units G1-G255, G256-G540, G541-G1080, G1081-G1620, G1621-G1905, and G1906-G2160. In fig. 7, #1 to #5 representoperation mode 1 tooperation mode 5, respectively. Taking theoperation mode 2 as an example, in theoperation mode 2, the sub-regions B1 and B6 are displayed to show the inactive region, the sub-regions B2 to B5 are displayed to show the active region, and so on.

Taking the display sub-area B1 as an example, in the driving units G1 to G255, the scanning start signal (ST _ on) ST1 is received when scanning is started, and the scanning end signal (ST _ off) ST7 is received when scanning is ended; the gate of its transistor Txon receives the turn-onsignal Xon 1. The rest can be analogized.

Table 2 below shows the scan start signal, the scan end signal and the turn-on signal used in various operation modes in the second embodiment of the present disclosure.

TABLE 2

Fig. 8A to 8E are signal waveform diagrams illustrating a scan start signal, a scan end signal and a turn-on signal for various operation modes according to a second embodiment of the disclosure.

As can be seen from fig. 8A to 8E, in the second embodiment of the present disclosure, different display sub-regions are controlled by matching different timings, wherein the scan start signal, the scan end signal and the turn-on signal are independently and separately controlled by different signals.

In the second embodiment of the present disclosure, some scan start signals may be the same as the scan end signals, and some turn-on signals may be the same.

Table 3 below shows another scan start signal, another scan end signal and another turn-on signal used in various operation modes in the second embodiment of the present disclosure.

TABLE 3

Fig. 9A to 9E are signal waveform diagrams illustrating another scan start signal, scan end signal and turn-on signal used in various operation modes according to the second embodiment of the present disclosure.

As can be seen from fig. 9A to 9E, in the second embodiment of the present disclosure, different display sub-regions are controlled by matching different timings, wherein the scan start signal, the scan end signal and the turn-on signal can be shared to reduce the number of signals required to be provided by the system.

Table 4 below shows still another scan start signal, scan end signal and turn-on signal used in various operation modes in the second embodiment of the present disclosure.

TABLE 4

Fig. 10A to 10E are signal waveform diagrams illustrating still another scan start signal, scan end signal and turn-on signal used in various operation modes according to the second embodiment of the present disclosure.

As can be seen from fig. 10A to 10E, in the second embodiment of the present disclosure, different display sub-regions are controlled by matching different timings, wherein the scan start signal, the scan end signal and the turn-on signal are independently and separately controlled by different signals.

In the second embodiment of the present disclosure, under 5 different operation modes, the driving units are divided into a plurality of display sub-regions, which are respectively controlled by different driving units, and are matched with different scanning start signals (ST 1-6) and different scanning end signals (ST 7-12) to control the on and off of the driving units of different display sub-regions. In addition, in different operation modes, for the inactive area, the auxiliary pull-upcircuit 570, the conducting signals (Xon 1-6) and the auxiliary pull-down control circuit are used to write the black frame into the inactive area to maintain the inactive area.

In the embodiment of the present disclosure, G1, G256, G541, G1081, G1621, and G1906 are referred to as candidate scan start stages because in different modes, the stages may be selected as the scan start stages; and G255, G540, G1080, G1620, G1905 and G2160 are referred to as candidate scan end levels because the levels may be selected as scan end levels in different modes.

In the embodiments of the present disclosure, the scan/update sequence of the active area and the inactive area is switched in different operation modes to maintain the black frame of the inactive area.

As can be seen from the above embodiments, in the embodiments of the present disclosure, the display screen is virtually divided into a plurality of display sub-areas, and under different operation modes, an appropriate candidate scan start level can be selected as the scan start level, so that the convenience of operation can be increased.

Furthermore, in the embodiment of the present disclosure, the leakage current problem can be improved by adding the leakage current balancing transistor (the transistor T11-2) in the pull-up control circuit of the driving unit.

While the present invention has been described with reference to the above embodiments, it is not intended to be limited thereto. It will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention is subject to the claims.

Claims (12)

Translated fromChinese

1.一种影像显示器，包括：1. An image display, comprising:一显示面板；以及，a display panel; and,一驱动电路，耦接至该显示面板，a driving circuit coupled to the display panel,其中，in,当处于一正常模式，该驱动电路更新该显示面板的一主动区，以及when in a normal mode, the driver circuit updates an active area of the display panel, and当处于一超宽模式，该驱动电路交错更新该显示面板的该主动区与至少一非主动区。When in an ultra-wide mode, the driving circuit alternately updates the active area and at least one inactive area of the display panel.2.如权利要求1所述的影像显示器，其中，当处于该超宽模式下，在一画框内，该驱动电路按序更新该显示面板的一第一非主动区、该主动区与一第二非主动区。2 . The image display of claim 1 , wherein when in the ultra-wide mode, within a picture frame, the driving circuit sequentially updates a first inactive area, the active area and a The second inactive zone.3.如权利要求1所述的影像显示器，其中，当处于该超宽模式下，在一画框内，该驱动电路同步更新该显示面板的一第一非主动区与一第二非主动区，之后，该驱动电路更新该显示面板的该主动区。3 . The image display of claim 1 , wherein, when in the ultra-wide mode, within a frame, the driving circuit synchronously updates a first inactive area and a second inactive area of the display panel 3 . , and then, the driving circuit updates the active area of the display panel.4.如权利要求1所述的影像显示器，其中，当处于该超宽模式下，4. The image display of claim 1, wherein, when in the ultra-wide mode,在多个画框内，该驱动电路多次更新该显示面板的该主动区，之后，该驱动电路更新该显示面板的该至少一非主动区；或者In a plurality of picture frames, the driving circuit updates the active area of the display panel multiple times, and then the driving circuit updates the at least one inactive area of the display panel; or在多个画框内，该驱动电路更新该显示面板的一第一非主动区、该驱动电路多次更新该显示面板的该主动区，以及，该驱动电路更新该显示面板的一第二非主动区。In a plurality of frames, the driving circuit updates a first non-active area of the display panel, the driving circuit updates the active area of the display panel multiple times, and the driving circuit updates a second non-active area of the display panel Active zone.5.一种影像显示器的驱动电路，包括：5. A drive circuit for an image display, comprising:多个驱动单元，各该些驱动单元包括一上拉控制电路、一上拉电路、一下拉控制电路与一下拉电路，a plurality of driving units, each of the driving units includes a pull-up control circuit, a pull-up circuit, a pull-down control circuit and a pull-down circuit,该上拉控制电路耦接至该上拉电路，以控制该上拉电路对一本级输出信号的上拉；The pull-up control circuit is coupled to the pull-up circuit to control the pull-up of the first-stage output signal by the pull-up circuit;该下拉控制电路耦接至该下拉电路，以控制该下拉电路对该本级输出信号的下拉，The pull-down control circuit is coupled to the pull-down circuit for controlling the pull-down of the output signal of the current stage by the pull-down circuit,其中，该上拉控制电路包括一第一晶体管与一第二晶体管，Wherein, the pull-up control circuit includes a first transistor and a second transistor,该第一晶体管接收一起始触发信号或一前级起始信号；the first transistor receives a start trigger signal or a previous stage start signal;该第二晶体管耦接至一本级起始信号。The second transistor is coupled to a primary start signal.6.如权利要求5所述的驱动电路，其中，该上拉控制电路还包括一第三晶体管，该第三晶体管接收一接地电压或该起始触发信号。6 . The driving circuit of claim 5 , wherein the pull-up control circuit further comprises a third transistor, and the third transistor receives a ground voltage or the start trigger signal. 7 .7.如权利要求6所述的驱动电路，其中，7. The drive circuit of claim 6, wherein,于该些驱动单元的一第一级驱动单元中，该第一晶体管接收该起始触发信号，该第三晶体管接收该接地电压；In a first-level driving unit of the driving units, the first transistor receives the start trigger signal, and the third transistor receives the ground voltage;于该些驱动单元的至少一候选扫描起始驱动单元中，该第一晶体管接收该前级起始信号，该第三晶体管接收该起始触发信号；以及In at least one candidate scan start driving unit of the driving units, the first transistor receives the pre-stage start signal, and the third transistor receives the start trigger signal; and于其他级驱动单元中，该第一晶体管栅极接收该前级起始信号，该第三晶体管接收该接地电压。In other stage driving units, the gate of the first transistor receives the pre-stage start signal, and the third transistor receives the ground voltage.8.如权利要求5所述的驱动电路，其中该下拉电路包括：一第四晶体管与一第五晶体管，8. The driving circuit of claim 5, wherein the pull-down circuit comprises: a fourth transistor and a fifth transistor,该第四晶体管耦接至该后级起始信号、该接地电压与一内部节点，The fourth transistor is coupled to the post-stage start signal, the ground voltage and an internal node,该第五晶体管分别耦接至该内部节点、一起始重置信号与该接地电压，The fifth transistor is coupled to the internal node, an initial reset signal and the ground voltage, respectively,其中，对于该些驱动单元的至少一候选扫描结束驱动单元中，由该第四晶体管下拉一本级内部节点，该第五晶体管进行重置，或者，该第五晶体管下拉该本级内部节点且进行重置，该第四晶体管被关闭，Wherein, for at least one candidate scanning end driving unit of the driving units, the fourth transistor pulls down the internal node of the first stage, the fifth transistor is reset, or the fifth transistor pulls down the internal node of the current stage and A reset is performed, the fourth transistor is turned off,对于该些驱动单元的其他级驱动单元，由该第四晶体管下拉该本级内部节点，该第五晶体管进行重置，或者，该第四晶体管下拉该本级内部节点，该第五晶体管进行重置。For other driving units of the driving units, the fourth transistor pulls down the internal node of the current stage, and the fifth transistor resets, or, the fourth transistor pulls down the internal node of the current stage, and the fifth transistor resets set.9.如权利要求5所述的驱动电路，其中各该些驱动单元还包括一辅助下拉控制电路、一辅助下拉电路与一辅助上拉电路，9. The driving circuit of claim 5, wherein each of the driving units further comprises an auxiliary pull-down control circuit, an auxiliary pull-down circuit and an auxiliary pull-up circuit,该辅助下拉电路耦接至该下拉电路，将一内部节点下拉，The auxiliary pull-down circuit is coupled to the pull-down circuit and pulls down an internal node,该辅助下拉控制电路耦接至该下拉控制电路，控制该内部节点的下拉，以及The auxiliary pull-down control circuit, coupled to the pull-down control circuit, controls the pull-down of the internal node, and该辅助上拉电路控制将该本级输出信号上拉。The auxiliary pull-up circuit controls the pull-up of the output signal of this stage.10.如权利要求9所述的驱动电路，其中，10. The drive circuit of claim 9, wherein,该辅助下拉控制电路包括：多个第六晶体管，该些第六晶体管接收一导通信号，分别耦接至多个内部节点，且耦接至一接地电压；以及The auxiliary pull-down control circuit includes: a plurality of sixth transistors, the sixth transistors receive a turn-on signal, are respectively coupled to a plurality of internal nodes, and are coupled to a ground voltage; and该辅助下拉电路包括：一第七晶体管，耦接至该些内部节点之一且接收一起始信号。The auxiliary pull-down circuit includes: a seventh transistor coupled to one of the internal nodes and receiving a start signal.11.如权利要求10所述的驱动电路，其中，该辅助上拉电路包括：一第八晶体管，该第八晶体管耦接至该本级输出信号与该导通信号。11. The driving circuit of claim 10, wherein the auxiliary pull-up circuit comprises: an eighth transistor, and the eighth transistor is coupled to the output signal of the current stage and the turn-on signal.12.如权利要求10所述的驱动电路，其中，该辅助上拉电路包括：一第九晶体管与一第十晶体管，该第九晶体管耦接至该本级输出信号、该第十晶体管与该导通信号，该第十晶体管耦接至该第九晶体管与该导通信号。12. The driving circuit of claim 10, wherein the auxiliary pull-up circuit comprises: a ninth transistor and a tenth transistor, the ninth transistor is coupled to the output signal of the current stage, the tenth transistor and the tenth transistor A turn-on signal, the tenth transistor is coupled to the ninth transistor and the turn-on signal.

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