Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the invention may be practiced without one or more of these details. In other instances, well-known features have not been described in detail in order to avoid obscuring the invention.
It should be understood that the present invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size of layers and regions, as well as the relative sizes, may be exaggerated for clarity. Like numbers refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In order to provide a thorough understanding of the present invention, detailed steps and detailed structures will be presented in the following description in order to explain the technical solution presented by the present invention. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments in addition to these detailed descriptions.
For a better understanding of the present invention, the reasons for passing and failing chips of a wafer are first further analyzed in connection with FIG. 1A.
In Back End of Line (BEOL) semiconductor, al/Cu (0.5%) alloys are often used as materials for leads of integrated circuits, and are mainly characterized by low resistance, good conductivity, easy processing, capability of meeting design requirements of chips of different structures, and capability of increasing electromigration resistance by adding an appropriate amount of Cu to Al. Because the melting point of aluminum metal is relatively low, in the process of depositing FSG by HDPCVD, the HDP process has strong Bias Power for enabling charged ions to bombard the surface of a wafer (wafer) so as to improve filling capability, the ion bombardment can raise the temperature of the surface of the wafer, and when the reaction temperature of the wafer is too high, deformation or even melting of Al wires can be caused, so that the reliability of the wafer is affected.
Therefore, flowing helium (He) is introduced into the back of the wafer while the HDP process is applied to prevent aluminum melting caused by the excessive temperature of the wafer. The helium back gas is mainly introduced by two circles of dense holes on a wafer tray (E-Chuck), wherein the Outer circle (Outer) helium back holes are about 7mm from the wafer edge, and the Inner circle (Inner) helium back holes are about 15mm from the wafer edge. As the flow of the helium gas removes heat from the wafer, the region of the lowest temperature of the entire wafer will be the outer ring helium back region. Because the F in the FSG mainly has two forms, namely Si-F bonds and free F ions are formed by combining with Si dangling bonds, a large amount of free F ions are easy to appear when the reaction temperature is too low, F precipitation can be generated when the excessive free F ions are gathered, the F is expressed on a wafer as bubble-shaped defects appear on the surface of the FSG film, and short circuit risks can be caused in the subsequent process.
Specifically, the failed chip located in the edge area of the wafer shown in fig. 1A belongs to a short circuit, that is, the wires are interconnected at a certain position, for the failed chip, the section of the failed chip is analyzed by using an electron scanning microscope (SEM), and bubbles appear in the short circuit area, as shown in fig. 1B, so that the failure mechanism of the failed chip may be that bubbles may appear in the lower layer of an inter-metal dielectric layer (IMD), the through holes are communicated with the bubbles after the subsequent etching to form the through holes (Via), and then W is poured in during the tungsten (W) deposition process, so as to cause a short circuit.
Further, fig. 1C and 1D show the results of wafer testing including pass chips and fail chips before and after forming the fluorine-doped silicon glass by high density plasma chemical vapor deposition, respectively, and it can be seen that the number of fail chips is significantly increased in the step of forming the fluorine-doped silicon glass by high density plasma chemical vapor deposition, and for the fail chips, the cross section of the fail chips is analyzed by using an electron scanning microscope (SEM), and typical edge egg roll-shaped bubbles (as shown in fig. 1E) after the high density plasma chemical vapor deposition and typical edge bubble-shaped bubbles (as shown in fig. 1F) after the high density plasma chemical vapor deposition are observed.
In view of the above problems, the present invention provides a method for manufacturing a semiconductor device, as shown in fig. 2 and 3, including:
Step S310, providing a wafer 200, wherein a metal layer 210 is formed on the wafer 200;
Step 320, forming a first inter-metal dielectric layer 221 on the wafer 200;
step S330, heating the first inter-metal dielectric layer 221;
Step S340, performing an oxidation treatment on the first intermetal dielectric layer 221;
step S350, forming a second inter-metal dielectric layer 222 on the first inter-metal dielectric layer 221.
First, step S310 is performed to provide a wafer 200, and a metal layer 210 is formed on the wafer 200.
Illustratively, the wafer 200 includes a silicon substrate, which may be at least one of single crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), germanium-on-insulator (GeOI), and the like. In one embodiment, the silicon substrate may be a P-type or N-type impurity ion implanted silicon substrate, and the specific doping concentration thereof is not limited by the present embodiment.
Illustratively, the wafer 200 further includes an isolation structure, which is a Shallow Trench Isolation (STI) structure or a local silicon oxide (LOCOS) isolation structure, that divides the silicon substrate into different active regions in which various semiconductor devices, such as NMOS and PMOS, may be formed. Various well (well) structures are also formed in the silicon substrate, and are omitted from the drawings for simplicity.
Illustratively, a metal interconnect structure is also formed over the active region, including a multi-layered inter-metal dielectric structure and a multi-layered interconnect metal layer located within the inter-metal dielectric structure, the interconnect metal structure generally including trenches and vias that form connection vias from bottom to top to connect electrodes of the semiconductor device of the active region to pads located at the very top of the metal interconnect structure. In this embodiment, the metal layer 210 is any one of a plurality of interconnection metal layers in a metal interconnection structure.
Illustratively, the metal layer 210 includes an aluminum copper alloy containing about 0.5% copper. Al/Cu (0.5%) alloy is often used as material for the leads of integrated circuits, and is mainly characterized by low resistance, good conductivity, easy processing, capability of meeting the design requirements of chips with different structures, capability of increasing the electromigration resistance by adding proper amount of Cu into Al, and the like.
Illustratively, the metal layer 210 may be formed by one of Low Pressure Chemical Vapor Deposition (LPCVD), laser Ablation Deposition (LAD), and Selective Epitaxial Growth (SEG) formed by a Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or the like. Physical Vapor Deposition (PVD) is preferred in this embodiment.
Further, the metal layer 210 is etched to form an interconnect via. The method for etching the metal layer 210 may be dry etching or wet etching. Illustratively, the dry etching process includes, but is not limited to, reactive Ion Etching (RIE), ion beam etching, plasma etching, laser ablation, or any combination of these methods. A single etching method may be used, or more than one etching method may be used. The source gases for the dry etch may include HBr and/or CF4 gases.
Next, a step of forming a first diffusion barrier layer 231 on the metal layer 210 is performed.
Illustratively, the first diffusion barrier 231 includes a silicon-rich oxide (silicon rich oxide, SRO) layer.
Illustratively, the SRO layer is prepared substantially the same as conventional silicon oxide by a Chemical Vapor Deposition (CVD) method, using a gas mixture containing silane (SiH4), oxygen (O2), and a rare gas such as argon (Ar) as a preparation gas. Wherein, since the silicon content of the SRO is greater than that of the conventional silicon oxide, the ratio of SiH4 to O2 is set to be higher than that used to form the conventional silicon oxide. In addition, another silane gas such as disilane (Si2H6) gas and Tetraethoxysilane (TEOS) gas may be used instead of the monosilane gas. Instead of oxygen, an oxygen-containing gas such as nitrous oxide (N2 O) gas or ozone (O3) may also be used. As an example, when CVD is used to form the SRO layer, the power is 180W-220W, the pressure in the chamber is 2.6Torr-3.0Torr, the flow rate of SiH4 gas is 140sccm-160sccm, the flow rate of N2 O gas is 2400sccm, the deposition time lasts for 4s-5s, and the thickness of the deposited film is equal to or greater than that of the substrate
The use of a silicon-rich oxide as the first diffusion barrier 231 may trap F ions to prevent the F ions in the subsequently formed first inter-metal dielectric layer 221 from diffusing toward the metal layer 210.
Next, step S320 is performed to form a first inter-metal dielectric layer 221 on the wafer 200.
Illustratively, an inter-metal dielectric structure is formed between adjacent interconnect metal layers, the inter-metal dielectric structure being a stacked structure, in this embodiment, the inter-metal dielectric structure includes at least a first inter-metal dielectric layer 221 and a second inter-metal dielectric layer 222, further, the inter-metal dielectric structure further includes a first diffusion barrier layer 231 between the first inter-metal dielectric layer 221 and the interconnect metal layer (i.e., metal layer 210), and a second diffusion barrier layer 232 between the second inter-metal dielectric layer 222 and the interconnect metal layer.
Illustratively, a first inter-metal dielectric layer 221 comprising fluorine doped silicon glass (FSG) is formed on the first diffusion barrier layer 231. Further, the content of F in the FSG is about 4%.
Illustratively, the first inter-metal dielectric layer 221 is formed using High Density Plasma Chemical Vapor Deposition (HDPCVD).
Illustratively, forming the fluorine-doped silica glass is performed in a Chemical Vapor Deposition (CVD) process chamber using a silicon tetrafluoride (SiF4)/silane (SiH4) gas to react with an oxidizing agent to form the fluorine-doped silica glass (FSG). Meanwhile, in the process chamber, a radio frequency power (RFPower) is applied to the reaction gas to form a high density plasma. As an example, in forming FSG using HDPCVD, the power parameters include radio frequency Bias (RF Bias) =3000W-3300W, side RF (RF Side) =3300W-3500W, top RF (RF Top) =1200W-1400W, back helium gas pressure (independenthelium control, IHC) of about 5.8Torr for the Inner ring (Inner), about 8.6Torr for the Outer ring (Outer), pressure of 4mTorr-6mTorr in the chamber, siH4 gas flow of 30sccm-34sccm, silicon tetrafluoride gas flow of 20sccm-25sccm, O2 gas flow of 65sccm-75sccm, deposited film thickness
Meanwhile, flowing He (helium) is introduced into the back surface of the wafer 200 to prevent aluminum melting caused by the excessive temperature of the wafer. The helium back gas is mainly introduced by two circles of dense holes on a wafer tray (E-Chuck), wherein the Outer circle (Outer) helium back holes are about 7mm from the wafer edge, and the Inner circle (Inner) helium back holes are about 15mm from the wafer edge.
As one example, HDPFSG deposition processes include wafer movement into the process chamber, plasma ignition, pre-heating, reactant gas entry, pre-deposition of a protective film, main deposition, bias off, wafer movement out of the process chamber, and the like. The Bias off (Bias off) mainly includes turning off the Bias Power and the reactive gases such as SiH4, and adding to the processing of the first inter-metal dielectric layer 221 after the Bias off and before the wafer is removed from the processing chamber, as described below.
Next, step S330 is performed to heat the first inter-metal dielectric layer 221.
Illustratively, the temperature range of the heat treatment is 380 ℃ to 400 ℃ and the time range of the heat treatment is 10s to 20s.
Further, the power parameters during the heating process include radio frequency Bias (RF Bias) =0w, side radio frequency (RF Side) =3500W-4000W, top radio frequency (RF Top) =2500W-3000W. The pressure during the heat treatment is in the range of 4mTorr to 6mTorr. The back helium gas pressure (IHC) range in the heating treatment process is 2.2Torr-2.4Torr in the Inner ring (Inner) and 3.6Torr-4.0Torr in the Outer ring (Outer), the gas flow rate of argon (Ar) in the heating treatment process is 100sccm-120sccm, and the gas flow rate of oxygen (O2) is 120sccm-130sccm.
By performing the heat treatment on the first inter-metal dielectric layer 221, more free F contained in the first inter-metal dielectric layer 221, especially in the helium-free low temperature ring portion, can volatilize at a higher temperature, and is prevented from being accumulated and separated out at the interface between the first inter-metal dielectric layer 221 and the lower first diffusion barrier layer 231, so that bubble defects between the first inter-metal dielectric layer 221 and the first diffusion barrier layer 231 are avoided. In addition, the heating process volatilizes only free F in the first inter-metal dielectric layer 221, and does not affect the stable F element in the first inter-metal dielectric layer 221, so that the change of the dielectric constant of the first inter-metal dielectric layer 221 is not caused.
Next, step S340 is performed to perform an oxidation process on the first inter-metal dielectric layer 221.
Illustratively, the oxidation process includes an oxygen plasma process to form a dense oxide layer on the surface of the first inter-metal dielectric layer 221.
Illustratively, the time of the oxidation treatment is in the range of 16s to 20s. The power parameters during the oxidation process include radio frequency Bias (RF Bias) =0w, side radio frequency (RF Side) =4600W-4800W, top radio frequency (RF Top) =4600W-4800W. The pressure during the oxidation process is in the range of 4mTorr to 6mTorr. The back helium gas pressure (IHC) in the oxidation treatment process ranges from 4.4Torr to 4.8Torr in the Inner ring (Inner) to 7.5Torr to 7.9Torr in the Outer ring (Outer), and the gas strength of oxygen (O2) in the heating treatment process ranges from 220sccm to 240sccm.
Because the HDP deposited fluorine-doped silica glass has the existence of fluorine, the microstructure of the FSG presents loose multi-surrounding pores, so that the FSG has stronger water vapor adsorption capacity. And a waiting time exists between the formation of the first inter-metal dielectric layer 221 and the start of the formation of the second inter-metal dielectric layer 222, so that after the water vapor in the environment enters the first inter-metal dielectric layer 221, HF is easily formed by combining with F ions, the first inter-metal dielectric layer 221 and the metal layer 210 are corroded, and bubble defects may be formed at the interface between the first diffusion barrier layer 231 and the first inter-metal dielectric layer 221 when water absorption is excessive, which affects the yield. In addition, F in the second intermetal dielectric layer 222 formed later diffuses into the first intermetal dielectric layer 221 below, and F precipitation is generated to cause defects.
Oxygen treatment dissociates O2 with a larger side source power. After the oxygen plasma treatment, the Si dangling bonds at the interface of the first inter-metal dielectric layer 221 are oxidized, so as to form a dense oxide layer. The dense oxide layer has two functions of (1) preventing the first inter-metal dielectric layer 221 from adsorbing water vapor in the environment during the process gap to cause HF corrosion, and (2) blocking the free F interdiffusion between the second inter-metal dielectric layer 222 and the first inter-metal dielectric layer 221 to cause F precipitation, especially generating bubble defects at the wafer edge.
Next, step S350 is performed to form a second inter-metal dielectric layer 222 on the first inter-metal dielectric layer 221.
Illustratively, the second intermetal dielectric layer 222 comprises fluorine doped silicon glass (FSG).
Illustratively, the second inter-metal dielectric layer 222 is formed using Plasma Enhanced Chemical Vapor Deposition (PECVD). As an example, when PECVD is used, the power is 900W-1400W, the temperature in the chamber is heated to 300-500 ℃, the SiH4 gas flow is 250-280 sccm, the SiF4 gas flow is 650-750 sccm, the N2 O gas flow is 9000-11000 sccm, the N2 gas flow is 2000-3000 sccm, and the deposited film layer is thick
Illustratively, forming the fluorine-doped silica glass is performed in a Chemical Vapor Deposition (CVD) process chamber using a silicon tetrafluoride (SiF4)/silane (SiH4) gas to react with an oxidizing agent to form the fluorine-doped silica glass (FSG).
Next, a chemical mechanical polishing is performed on the second inter-metal dielectric layer 222.
Illustratively, by chemical-mechanical polishing (CMP), a perfect surface can be obtained while ensuring material removal efficiency, resulting in a wafer with good flatness.
Next, a second diffusion barrier layer 232 is formed on the second inter-metal dielectric layer 222.
Illustratively, the second diffusion barrier 232 includes a silicon-rich oxide (silicon rich oxide, SRO) layer.
Illustratively, the SRO layer is prepared substantially the same as conventional silicon oxide by a Chemical Vapor Deposition (CVD) method, using a gas mixture of silane (SiH4), oxygen (O2), and a rare gas such as argon (Ar) as a preparation gas. Wherein, since the silicon content of the SRO is greater than that of the conventional silicon oxide, the ratio of SiH4 to O2 is set to be higher than that used to form the conventional silicon oxide. In addition, another silane gas such as disilane (Si2H6) gas and Tetraethoxysilane (TEOS) gas may be used instead of the monosilane gas. Instead of oxygen, an oxygen-containing gas such as nitrous oxide (N2 O) gas or ozone (O3) may also be used. As an example, when CVD is used to form the SRO layer, the power is 180W-220W, the pressure in the chamber is 2.6Torr-3.0Torr, the flow rate of SiH4 gas is 140sccm-160sccm, the flow rate of N2 O gas is 2400sccm, the deposition time lasts for 4s-5s, and the thickness of the deposited film is equal to or greater than that of the substrate
The use of a silicon-rich oxide as the second diffusion barrier 232 may trap F ions to prevent the F ions in the second inter-metal dielectric layer 222 from diffusing toward the upper interconnect metal layer.
Further, the embodiment further includes repeating the steps of forming the metal layer and the inter-metal dielectric structure to form the metal interconnection structure.
The present invention provides a semiconductor device, as shown in fig. 2, comprising:
a wafer 200 on which a metal layer 210 is formed;
the wafer 200 has a first inter-metal dielectric layer 221 formed thereon that is heated and oxidized;
the first inter-metal dielectric layer 221 has a second inter-metal dielectric layer 222 formed thereon.
Illustratively, the wafer 200 includes a silicon substrate, which may be at least one of single crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), germanium-on-insulator (GeOI), and the like. In one embodiment, the silicon substrate may be a P-type or N-type impurity ion implanted silicon substrate, and the specific doping concentration thereof is not limited by the present embodiment.
Illustratively, the wafer 200 further includes an isolation structure, which is a Shallow Trench Isolation (STI) structure or a local silicon oxide (LOCOS) isolation structure, that divides the silicon substrate into different active regions in which various semiconductor devices, such as NMOS and PMOS, may be formed. Various well (well) structures are also formed in the silicon substrate, and are omitted from the drawings for simplicity.
Illustratively, a metal interconnect structure is also formed over the active region, including a multi-layered inter-metal dielectric structure and a multi-layered interconnect metal layer located within the inter-metal dielectric structure, the interconnect metal structure generally including trenches and vias that form connection vias from bottom to top to connect electrodes of the semiconductor device of the active region to pads located at the very top of the metal interconnect structure. In this embodiment, the metal layer 210 is any one of a plurality of interconnection metal layers in a metal interconnection structure.
Illustratively, the metal layer 210 includes an aluminum copper alloy containing about 0.5% copper. Al/Cu (0.5%) alloy is often used as material for the leads of integrated circuits, and is mainly characterized by low resistance, good conductivity, easy processing, capability of meeting the design requirements of chips with different structures, capability of increasing the electromigration resistance by adding proper amount of Cu into Al, and the like.
Illustratively, the metal layer 210 has a first diffusion barrier 231 formed thereon.
Illustratively, the first diffusion barrier 231 includes a silicon-rich oxide (silicon rich oxide, SRO) layer.
The use of a silicon-rich oxide as the first diffusion barrier 231 may trap F ions to prevent the F ions in the subsequently formed first inter-metal dielectric layer 221 from diffusing toward the metal layer 210.
Illustratively, the wafer 200 has a first inter-metal dielectric layer 221 formed thereon.
Illustratively, an inter-metal dielectric structure is formed between adjacent interconnect metal layers, the inter-metal dielectric structure being a stacked structure, in this embodiment, the inter-metal dielectric structure includes at least a first inter-metal dielectric layer 221 and a second inter-metal dielectric layer 222, further, the inter-metal dielectric structure further includes a first diffusion barrier layer 231 between the first inter-metal dielectric layer 221 and the interconnect metal layer (i.e., metal layer 210), and a second diffusion barrier layer 232 between the second inter-metal dielectric layer 222 and the interconnect metal layer.
Illustratively, the first intermetal dielectric layer comprises fluorine doped silicon glass (FSG). Further, the content of F in the FSG is about 4%.
Illustratively, the first inter-metal dielectric layer 221 is formed using High Density Plasma Chemical Vapor Deposition (HDPCVD). The first inter-metal dielectric layer 221 is subjected to a heat treatment at a temperature ranging from 380 ℃ to 400 ℃ for a time ranging from 10s to 20s. The first inter-metal dielectric layer 221 is further subjected to an oxidation process including an oxygen plasma process to form a dense oxide layer on the surface of the first inter-metal dielectric layer 221.
Illustratively, a second inter-metal dielectric layer 222 is also formed on the first inter-metal dielectric layer 221. The second inter-metal dielectric layer 222 includes fluorine doped silicon glass (FSG).
Further, a second diffusion barrier layer 232 is formed on the second inter-metal dielectric layer 222. The second diffusion barrier 232 includes a silicon-rich oxide (silicon rich oxide, SRO) layer.
The use of a silicon-rich oxide as the second diffusion barrier 232 may trap F ions to prevent the F ions in the second inter-metal dielectric layer 222 from diffusing toward the upper interconnect metal layer.
According to the manufacturing method of the semiconductor device, the first inter-metal dielectric layer is subjected to heating treatment and oxidation treatment to form the compact oxide layer at the interface between the first inter-metal dielectric layer and the second inter-metal dielectric layer, so that water vapor erosion and diffusion and precipitation of free F ions are avoided, bubble defects at the edge of a wafer are avoided, and the yield of the wafer is improved.
The present invention has been illustrated by the above-described embodiments, but it should be understood that the above-described embodiments are for purposes of illustration and description only and are not intended to limit the invention to the embodiments described. In addition, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications are possible in light of the teachings of the invention, which variations and modifications are within the scope of the invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.