CN113946485A - Method and device for monitoring memory bandwidth - Google Patents

Abstract

The embodiment of the application discloses a method and a device for monitoring memory bandwidth, and relates to the field of computers. The method comprises the following steps: the processor core obtains the memory bandwidth size used by the process group for accessing the volatile memory in the preset period, and calculates the memory bandwidth size used by the process group for accessing the nonvolatile memory according to the memory bandwidth size and the counted memory operation after counting the memory operation executed by the process group in the preset period. The method and the device realize monitoring of the memory bandwidth of the nonvolatile memory by taking the process group as granularity, and further take the memory bandwidth of the nonvolatile memory as a basis for limiting the memory bandwidth of the nonvolatile memory.

Description

Method and device for monitoring memory bandwidth

The present application claims priority from the chinese patent application filed by the national intellectual property office on 17/07/2020, having application number 202010691597.4 entitled "a method and apparatus for monitoring memory bandwidth," which is incorporated herein by reference in its entirety.

Technical Field

The embodiment of the application relates to the field of computers, in particular to a method and a device for monitoring memory bandwidth.

Background

With the development and prosperity of cloud technology, one server can run a plurality of processes of different tenants, and the plurality of processes share various resources (such as computing resources, storage resources, memory resources and the like) of the server, so that the resource utilization rate of the server is improved. However, resource sharing may present a performance unfair problem. For example, processes of the same priority get different resources. For another example, a process with a low priority occupies a large amount of resources, and a process with a high priority cannot acquire sufficient resources, so that the service of the tenant is affected, and the user experience is reduced. In the conventional technology, a resource control group (cgroup) technology is adopted to divide a plurality of processes into different process groups, and the different process groups use different resources (such as computing resources, storage resources and memory resources). In addition, a resource allocation technology (resource direction technology) is adopted to identify a process occupying the memory bandwidth of a large amount of volatile memory and limit the process to occupy the memory bandwidth of the volatile memory, so as to ensure that other processes acquire sufficient memory resources.

Since the memory bandwidth of a non-volatile memory (NVM) is much lower than that of a volatile memory. In a multi-tenant cloud environment, the memory bandwidth competition of a nonvolatile memory is more drastic than that of a volatile memory, and service degradation and even interruption are easily caused. However, since the non-volatile memory does not provide a memory bandwidth limiting function, the resource allocation technique cannot monitor and limit the memory bandwidth of the non-volatile memory. Therefore, how to monitor the memory bandwidth of the nonvolatile memory is an urgent problem to be solved.

Disclosure of Invention

The embodiment of the application provides a method and a device for monitoring memory bandwidth, which realize monitoring of the memory bandwidth of a nonvolatile memory by taking a process group as granularity, and further take the memory bandwidth of the nonvolatile memory as a basis for limiting the memory bandwidth of the nonvolatile memory.

In a first aspect, a method for monitoring memory bandwidth is provided, which is used for monitoring memory bandwidth of a non-volatile memory. The method comprises the following steps: the processor core obtains the memory bandwidth size used by the process group for accessing the volatile memory in the preset period, counts the memory operation executed by the process group in the preset period, and further calculates the first memory bandwidth size used by the process group for accessing the nonvolatile memory according to the memory bandwidth size and the counted memory operation. The memory operations herein include non-volatile memory operations and volatile memory operations. Therefore, the processor core estimates the memory bandwidth used by the process group for accessing the volatile memory based on the nonvolatile memory operation, the volatile memory operation and the memory bandwidth used by the process group for accessing the volatile memory in the preset period, the memory bandwidth of the nonvolatile memory is monitored by taking the process group as granularity through a software method, and the memory bandwidth of the nonvolatile memory is used as a basis for limiting the memory bandwidth of the nonvolatile memory.

It should be noted that the memory operation executed by the process group in the predetermined cycle may be understood as a memory address accessed by the memory operation executed by the process group in the predetermined cycle. The memory operation is a memory read-write operation. The process group includes at least one process. In some embodiments, a process group may be a container or a virtual machine. All processes comprised by a process group may be run by one container or one virtual machine. In other embodiments, the processes included in a process group may be run by multiple containers or multiple virtual machines. That is, the processes included in one process group are processes in a plurality of containers. Alternatively, the processes included in one process group are processes in a plurality of virtual machines.

In one possible design, calculating a first memory bandwidth size used by the process group to access the non-volatile memory according to the memory bandwidth size and the counted memory operations includes: the processor core determines the ratio of the access amount of the process group to the nonvolatile memory and the access amount of the process group to the volatile memory according to the memory address accessed by the memory operation; and calculating a first memory bandwidth size used by the process group for accessing the nonvolatile memory according to the memory bandwidth size and the proportion. Since the memory address accessed by the memory operation includes a memory address accessed by the non-volatile memory operation and a memory address accessed by the volatile memory operation. The memory type and the memory size of the memory accessed by the memory operation can be determined according to the memory address accessed by the memory operation. The memory types include non-volatile memory and volatile memory. The memory size includes the memory size of the process group accessing the volatile memory and the memory size of the process group accessing the non-volatile memory. And further, the processor core determines the ratio of the access amount of the process group to the nonvolatile memory and the access amount of the process group to the volatile memory according to the memory size and the memory type of the memory operation. It is understood that the access amount of the process group to the nonvolatile memory is the memory size of the process group to the nonvolatile memory. The access amount of the process group to the volatile memory is the memory size of the process group to the volatile memory.

Optionally, the memory operation executed in the preset period is all or part of the memory operation in the preset period.

Further, after calculating a first memory bandwidth size used by the process group to access the nonvolatile memory according to the memory bandwidth size and the counted memory operations, the method further includes: and if the first memory bandwidth size of the nonvolatile memory is larger than or equal to the nonvolatile memory bandwidth threshold, setting memory bandwidth limit of the process group, wherein the nonvolatile memory bandwidth threshold is the maximum value of memory bandwidth which is allowed to be used by the process group for accessing the nonvolatile memory. Therefore, the size of the memory bandwidth used by the process group for accessing the volatile memory is controlled through the limitation measure, and the size of the memory bandwidth used by the process group for accessing the nonvolatile memory is indirectly limited. The problem that other process groups, containers or virtual machines cannot access the nonvolatile memory due to the fact that the process groups, the containers or the virtual machines use excessive nonvolatile memory bandwidth is avoided, and the problem that service performance is degraded and even interrupted due to adjacent position interference fault diffusion is solved.

Setting the memory bandwidth limit of the process group comprises one or more of the following steps: and adjusting the first volatile memory bandwidth threshold of the process group to be a second volatile memory bandwidth threshold, wherein the first volatile memory bandwidth threshold is larger than the second volatile memory bandwidth threshold, and the first volatile memory bandwidth threshold and the second volatile memory bandwidth threshold both refer to the maximum value of memory bandwidth which is allowed to be used by the process group to access the volatile memory. The maximum value of the memory bandwidth of the volatile memory allowed to be used by the process group for accessing the volatile memory is reduced, so that the total memory bandwidth of the volatile memory and the nonvolatile memory used by the process group is reduced, the memory bandwidth of the nonvolatile memory used by the process group is indirectly reduced, and the memory bandwidth of the nonvolatile memory is limited to any value.

The process included in the process group is migrated from the first processor core to the second processor core running the process group. The number of processes included in the process group operated by the processor core is reduced, so that the memory operation of the process group on the volatile memory and the nonvolatile memory is reduced, the total memory bandwidth of the process group using the volatile memory and the nonvolatile memory is reduced, the memory bandwidth of the nonvolatile memory indirectly used by the process group is reduced, and the memory bandwidth of the nonvolatile memory is limited to any value.

And adjusting the first time slice of the process group into a second time slice, wherein the first time slice is larger than the second time slice, and the first time slice and the second time slice are the time length of the process group occupying the first processor core. The time length of the processor core occupied by the process group is shortened, so that the memory operation of the process group on the volatile memory and the nonvolatile memory is reduced, the total memory bandwidth of the process group using the volatile memory and the nonvolatile memory is reduced, the memory bandwidth of the nonvolatile memory indirectly used by the process group is reduced, and the memory bandwidth of the nonvolatile memory is limited to any value.

In one possible design, if the first volatile memory bandwidth threshold of the process group is adjusted to the second volatile memory bandwidth threshold, when the size of the second memory bandwidth of the nonvolatile memory is greater than or equal to the nonvolatile memory bandwidth threshold, the process included in the process group is migrated from the first processor core running the process group to the second processor core. Optionally, the first processor core and the second processor core belong to one or more NUMA nodes in a non-uniform memory access (NUMA) system.

In one possible design, if a process included in the process group is migrated from the first processor core running the process group to the second processor core, when the third memory bandwidth size of the nonvolatile memory is greater than or equal to the nonvolatile memory bandwidth threshold, the first time slice of the process group is adjusted to the second time slice.

Therefore, the memory bandwidth of the nonvolatile memory can be accurately controlled to a specific value by adopting a dynamic adjustment method, the service performance deterioration and even interruption are avoided, and the resource deployment cost is reduced.

After the memory bandwidth of the nonvolatile memory is limited, if the memory bandwidth of the nonvolatile memory monitored by the processor core is smaller than the nonvolatile memory bandwidth threshold, the limitation of the process group on accessing the volatile memory can be removed, the memory bandwidth used by the process group for accessing the nonvolatile memory is indirectly improved, and the process group has sufficient available resources.

In one possible design, after adjusting the first time slice of the process group to the second time slice, the method further includes: and when the fourth memory bandwidth size of the nonvolatile memory is smaller than the nonvolatile memory bandwidth threshold, adjusting the second time slice of the process group into the first time slice. Because the duration of the process group occupying the processor core is increased, the memory operation of the process group on the volatile memory and the nonvolatile memory is increased, the total memory bandwidth of the process group using the volatile memory and the nonvolatile memory is increased, the memory bandwidth of the nonvolatile memory indirectly used by the process group is increased, and the process group has sufficient available resources.

In one possible design, after adjusting the second time slice of the process group to the first time slice, the method further includes: and when the fifth memory bandwidth size of the nonvolatile memory is smaller than the nonvolatile memory bandwidth threshold, migrating the process contained in the process group from the second processor core to the first processor core. The number of the processes included in the process group operated by the processor core is increased, so that the memory operation of the process group on the volatile memory and the nonvolatile memory is increased, the total memory bandwidth of the process group using the volatile memory and the nonvolatile memory is increased, the memory bandwidth of the nonvolatile memory indirectly used by the process group is also increased, and the process group has sufficient available resources.

In one possible design, after migrating the process included in the process group from the second processor core to the first processor core, the method further includes: and when the sixth memory bandwidth size of the nonvolatile memory is smaller than the nonvolatile memory bandwidth threshold, adjusting the second volatile memory bandwidth threshold of the process group to be the first volatile memory bandwidth threshold. The maximum value of the memory bandwidth of the volatile memory used by the process group is increased, so that the total memory bandwidth of the volatile memory and the nonvolatile memory used by the process group is increased, the memory bandwidth of the nonvolatile memory used by the process group is indirectly increased, and the process group has sufficient available resources.

It should be noted that the nonvolatile memory bandwidth threshold is set through the first file system interface. The first volatile memory bandwidth threshold and the second volatile memory bandwidth threshold are set via a second file system interface.

In a second aspect, a method for limiting a memory bandwidth is provided, including: if the size of a first memory bandwidth used by the process group for accessing the nonvolatile memory in a preset period is larger than or equal to a nonvolatile memory bandwidth threshold, adjusting the first volatile memory bandwidth threshold of the process group to be a second volatile memory bandwidth threshold, wherein the nonvolatile memory bandwidth threshold is the maximum value of memory bandwidth allowed by the process group for accessing the nonvolatile memory, the first volatile memory bandwidth threshold is larger than the second volatile memory bandwidth threshold, the first volatile memory bandwidth threshold and the second volatile memory bandwidth threshold both refer to the maximum value of memory bandwidth allowed by the process group for accessing the volatile memory, and the process group comprises at least one process; and when the second memory bandwidth size of the nonvolatile memory is larger than or equal to the nonvolatile memory bandwidth threshold, migrating the process contained in the process group from the first processor core for running the process group to the second processor core. Therefore, the method controls the volatile memory bandwidth used by the process group for accessing the volatile memory by adopting a dynamic adjustment method, indirectly limits the memory bandwidth of the nonvolatile memory to any value, avoids the influence on the fact that other process groups, containers or virtual machines cannot access the nonvolatile memory due to the fact that the process groups, containers or virtual machines use excessive nonvolatile memory bandwidth, and solves the problem that service performance is degraded and even interrupted due to adjacent position interference fault diffusion.

In one possible design, after migrating a process included in the process group from a first processor core running the process group to a second processor core, the method further includes: and when the third memory bandwidth size of the nonvolatile memory is larger than or equal to the nonvolatile memory bandwidth threshold, adjusting the first time slice of the process group into a second time slice, wherein the first time slice is larger than the second time slice, and the first time slice and the second time slice are the time length of the process group occupying the first processor core.

In one possible design, after adjusting the first time slice of the process group to the second time slice, the method further includes: and when the fourth memory bandwidth size of the nonvolatile memory is smaller than the nonvolatile memory bandwidth threshold, adjusting the second time slice of the process group into the first time slice.

In one possible design, after adjusting the second time slice of the process group to the first time slice, the method further includes: and when the fifth memory bandwidth size of the nonvolatile memory is smaller than the nonvolatile memory bandwidth threshold, migrating the process contained in the process group from the second processor core to the first processor core.

In one possible design, after migrating the process included in the process group from the second processor core to the first processor core, the method further includes: and when the sixth memory bandwidth size of the nonvolatile memory is smaller than the nonvolatile memory bandwidth threshold, adjusting the second volatile memory bandwidth threshold of the process group to be the first volatile memory bandwidth threshold.

In a third aspect, a device for monitoring a memory bandwidth is provided, and for beneficial effects, reference may be made to the description of the first aspect, which is not described herein again. The apparatus for monitoring memory bandwidth has the function of implementing the behavior in the method example of the first aspect. The functions can be realized by hardware, and the functions can also be realized by executing corresponding software by hardware. The hardware or software includes one or more modules corresponding to the above-described functions. In one possible design, the means for monitoring memory bandwidth includes: the device comprises an acquisition unit, a monitoring unit and a limiting unit. The acquiring unit is configured to acquire a memory bandwidth size used by the process group to access the volatile memory in a preset period, and count memory operations executed by the process group in the preset period, where the memory operations include a nonvolatile memory operation and a volatile memory operation, and the process group includes at least one process. The monitoring unit is used for calculating a first memory bandwidth size used by the process group for accessing the nonvolatile memory according to the memory bandwidth size and the counted memory operation. The limiting unit is configured to set memory bandwidth limitation of the process group if the first memory bandwidth size is greater than or equal to a nonvolatile memory bandwidth threshold, where the nonvolatile memory bandwidth threshold is a maximum value of memory bandwidth that is allowed to be used by the process group to access the nonvolatile memory. The units may perform corresponding functions in the method example of the first aspect, for specific reference, detailed description of the method example is given, and details are not repeated here.

In a fourth aspect, an apparatus for limiting a memory bandwidth is provided, and for beneficial effects, reference may be made to the description of the second aspect, which is not described herein again. The means for limiting memory bandwidth has the functionality to implement the behavior in the method example of the second aspect described above. The functions can be realized by hardware, and the functions can also be realized by executing corresponding software by hardware. The hardware or software includes one or more modules corresponding to the above-described functions. In one possible design, the means for limiting memory bandwidth includes: an acquisition unit and a restriction unit. The acquiring unit is used for acquiring the memory bandwidth size used by the process group accessing the nonvolatile memory in the preset period. The limiting unit is configured to, if a first memory bandwidth size used by the process group to access the nonvolatile memory in a preset period is greater than or equal to a nonvolatile memory bandwidth threshold, adjust the first volatile memory bandwidth threshold of the process group to a second volatile memory bandwidth threshold, where the nonvolatile memory bandwidth threshold is a maximum value of a memory bandwidth that the process group allows to access the nonvolatile memory, the first volatile memory bandwidth threshold is greater than the second volatile memory bandwidth threshold, and both the first volatile memory bandwidth threshold and the second volatile memory bandwidth threshold refer to maximum values of memory bandwidths that the process group allows to access the volatile memory, and the process group includes at least one process. The limiting unit is further configured to migrate the process included in the process group from the first processor core to the second processor core when the second memory bandwidth size of the nonvolatile memory is greater than or equal to the nonvolatile memory bandwidth threshold. The limiting unit is further configured to adjust a first time slice of the process group to a second time slice when the third memory bandwidth size of the nonvolatile memory is greater than or equal to the nonvolatile memory bandwidth threshold, where the first time slice is greater than the second time slice, and both the first time slice and the second time slice are durations when the process group occupies the first processor core. The modules may perform corresponding functions in the method example of the second aspect, for specific reference, detailed description of the method example is given, and details are not repeated here.

In a fifth aspect, a processor is provided, where the processor includes a plurality of processor cores, and the processor cores are configured to perform the method for monitoring memory bandwidth in the first aspect or any one of the possible designs of the first aspect. The processor core may perform the operation steps of the method executed by the first processor core in the method example of the first aspect, which is specifically referred to in the detailed description of the method example, and is not described herein again.

In a sixth aspect, a processor is provided, the processor comprising a plurality of processor cores for performing the method of limiting memory bandwidth of the second aspect or any of the possible designs of the second aspect. The processor core may perform the operation steps of the method executed by the second processor core in the above method example of the second aspect, for specific reference, detailed description in the method example is given, and details are not repeated here.

In a seventh aspect, a server is provided, where the server includes at least one processor according to the fifth aspect and a main memory, where the processor includes multiple processor cores, and each processor core is configured to execute the operation steps of the method for monitoring the memory bandwidth in the first aspect or any one of the possible implementation manners of the first aspect.

In an eighth aspect, a server is provided, where the server includes at least one processor according to the sixth aspect and a main memory, and the processor includes a plurality of processor cores, and each processor core is configured to execute the operation steps of the method for limiting the memory bandwidth in any one of the possible implementations of the second aspect or the second aspect.

In a ninth aspect, there is provided a computer-readable storage medium comprising: computer software instructions; the computer software instructions, when executed in a server, cause the server to perform the operational steps of the method as described in the first aspect or any one of the possible implementations of the first aspect.

In a tenth aspect, there is provided a computer-readable storage medium comprising: computer software instructions; the computer software instructions, when executed in a server, cause the server to perform the operational steps of the method as described in the second aspect or any one of the possible implementations of the second aspect.

In an eleventh aspect, a computer program product is provided, which, when run on a computer, causes the computer to perform the operational steps of the method as described in the first aspect or any one of the possible implementations of the first aspect.

In a twelfth aspect, a computer program product is provided, which, when run on a computer, causes the computer to perform the operational steps of the method as described in the second aspect or any one of the possible implementations of the second aspect.

The present application can further combine to provide more implementations on the basis of the implementations provided by the above aspects.

Drawings

FIG. 1 is a simplified schematic diagram of a cloud environment provided by an embodiment of the present application;

fig. 2 is a flowchart of a method for monitoring a memory bandwidth according to an embodiment of the present disclosure;

fig. 3 is a flowchart of a method for monitoring a memory bandwidth according to an embodiment of the present disclosure;

fig. 4 is a flowchart of a method for monitoring a memory bandwidth according to an embodiment of the present disclosure;

fig. 5 is a schematic process migration diagram according to an embodiment of the present application;

fig. 6 is a flowchart of a method for limiting a memory bandwidth according to an embodiment of the present disclosure;

fig. 7 is a flowchart of a method for limiting a memory bandwidth according to an embodiment of the present disclosure;

fig. 8 is a schematic diagram illustrating a process of dynamically limiting a memory bandwidth according to an embodiment of the present disclosure;

fig. 9 is a schematic diagram illustrating a configuration of an apparatus for monitoring a memory bandwidth according to an embodiment of the present disclosure;

fig. 10 is a schematic diagram illustrating a device for limiting a memory bandwidth according to an embodiment of the present disclosure;

fig. 11 is a schematic composition diagram of a server according to an embodiment of the present application.

Detailed Description

Embodiments of the present application will be described in detail below with reference to the accompanying drawings.

The cloud environment is an entity which provides cloud services to users by using basic resources in a cloud computing mode. As shown in fig. 1, cloud environment 100 includes a cloud data center 110 and a cloud service platform 120. The cloud data center 110 includes a large number of base resources owned by a cloud service provider (including computing resources 111, storage resources 112, and memory resources 113).

The computing resources 111 may be a large number of computing devices (e.g., servers). The computing device includes multiple processors, such as processor 1111 and processor 1112 shown in fig. 1. Processor 1111 is the control center for the computing device. Typically, processor 1111 is a Central Processing Unit (CPU) including a processor core or a plurality of processor cores, such asprocessor core 0 andprocessor core 1 shown in fig. 1. Further, the processor 1111 may also be an Application Specific Integrated Circuit (ASIC), or be configured as one or more integrated circuits, such as: one or more microprocessors (digital signal processors, DSPs), or one or more Field Programmable Gate Arrays (FPGAs).Processor core 0 andprocessor core 1 may refer to a physical processor core or a logical processor core in processor 1111. The processor 1111 may perform various functions of the computing device by running or executing software programs stored within the storage resource 112, as well as invoking data stored within the storage resource 112 and memory resource 113. The processor 1112 may have a processor of the same physical form as the processor 1111, or may have a processor of a different physical form from the processor 1111. The processor 1112 is a processing chip with computing power for sharing the running process of the processor 1111 to reduce the computing burden of the processor 1111.

Memory resources 113 include non-volatile memory 1131 and volatile memory 1132. Volatile memory includes Random Access Memory (RAM). The nonvolatile memory has the advantages of nonvolatility, byte access, high storage density, low energy consumption, reading and writing performance close to a Dynamic Random Access Memory (DRAM), asymmetric reading and writing speed, far faster reading and writing and limited service life. When the current is turned off, the data stored in the nonvolatile memory does not disappear. Common non-volatile memories include Phase Change Memories (PCMs), magnetoresistive memories (MRAMs), resistive/Resistive Random Access Memories (RRAMs), ferroelectric memories (ferams), racetrack memories (random access memories), and graphene memories (graphene memories).

In physical form, the storage resource 112 may be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a Random Access Memory (RAM) or other types of dynamic storage devices that can store information and instructions, an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact disc, laser disc, optical disc, digital versatile disc, blu-ray disc, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited to such. The storage resource 112 may be separate or may be connected to the computing resource 111 via a communication bus. The storage resource 112 may also be integrated with the computing resource 111, without limitation. The communication bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, an Extended ISA (EISA) bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc.

In addition, the storage resource 112 is also used for storing software programs for executing the scheme of the application, and is controlled by the computing resource 111 to execute.

The user can access various services (such as financial services, game services and the like) provided by the cloud service platform 120 through the terminal device 130. When the computing device runs the processes 114 of the multiple services of different users, the processes of the multiple services share basic resources (such as the computing resource 111, the storage resource 112, the memory resource 113 and the like).

In order to avoid the unfair problem caused by the sharing of the basic resource by the multiple processes, a resource control group (cgroup) technology is adopted to divide the multiple processes into different process groups, and the different process groups use different resources (such as computing resources, storage resources and memory resources). A process group includes at least one process.

A resource control group is a resource control mechanism, i.e. all processes in an operating system are divided into groups, and all process groups are organized in a hierarchical structure. Each process group specifies a set of access resources (e.g., computing resources, storage resources, and memory resources). Different process groups access different resources. For example, processes in different process groups access different memory sizes and different memory bandwidths. The system administrator may configure the processes included in each process group through the first file system interface. The first file system interface is used for configuring the processes contained in the process group. The application processes of one user can be divided into the same process group, and can also be divided into different process groups. The process group may contain processes of the same application, or may contain processes of different applications.

The processor core may access both volatile and non-volatile memory when executing processes included in the process group. In the conventional technology, a resource director technology (resource director technology) is used to identify a process occupying a large amount of memory bandwidth of a volatile memory and limit the process to occupy the memory bandwidth of the volatile memory, so as to ensure that other processes acquire sufficient memory resources. Since the non-volatile memory does not provide a memory bandwidth limiting function, the resource allocation technology cannot monitor and limit the memory bandwidth of the non-volatile memory. The embodiment provides a method for monitoring a memory bandwidth, which includes that a memory bandwidth used by a process group to access a volatile memory in a preset period and a memory bandwidth used by a process group to access a nonvolatile memory are estimated according to memory operations, so that the memory bandwidth of the nonvolatile memory is monitored by taking the process group as a granularity, and the memory bandwidth of the nonvolatile memory is taken as a basis for limiting the memory bandwidth.

Next, a method for monitoring a memory bandwidth provided in this embodiment is described in detail with reference to fig. 2.

S201, the first processor core obtains the memory bandwidth size used by the process group to access the volatile memory in the preset period, and counts the memory operation executed by the process group in the preset period.

The kernel is the core of an operating system and is responsible for managing processes, memories, device drivers, files and network systems of the system, and determining the performance and stability of the system. When the first processor core runs a process in a process group, a Memory Bandwidth Monitoring (MBM) technology may be used to check memory management information in the kernel to obtain a memory bandwidth size used by the process group to access the volatile memory in a preset period. The preset period may be 1 second.

The memory operations include non-volatile memory operations and volatile memory operations. The memory operation executed by the process group in the preset period may be understood as a memory address accessed by the memory operation executed by the process group in the preset period.

In some embodiments, the first processor core monitors a read-write interface of the file system, collects memory operations on a memory in the system through the read-write interface of the file system in a preset period, and acquires a memory address accessed by the memory operations. Since the system includes the nonvolatile memory and the volatile memory, the memory address accessed by the memory operation includes the memory address of the nonvolatile memory and the memory address of the volatile memory.

In other embodiments, the first processor core collects memory operations for other memory accesses using a Precision Event Based Sampling (PEBS) technique. Other memory operations that access memory include, but are not limited to: mapping a file or other object into memory operations of the memory, memory operations accessing shared memory, memory operations accessing file descriptors, memory operations accessing pipeline files.

Optionally, the memory operation executed in the preset period is all or part of the memory operation in the preset period. For example, the memory operation counted by the first processor core may be a memory operation of a part of duration in a preset period. For example, a memory operation of half the duration of a predetermined period. The memory operation includes memory read-write operation of a volatile memory and memory read-write operation of a non-volatile memory.

S202, the first processor core calculates the memory bandwidth size used by the process group for accessing the nonvolatile memory according to the memory bandwidth size and the counted memory operation.

Specifically, the method flow described in fig. 3 is an explanation of a specific operation process included in S202 in fig. 2, as shown in the figure: s2021, the first processor core determines the ratio of the access amount of the process group to the nonvolatile memory and the access amount of the process group to the volatile memory according to the memory address accessed by the memory operation. S2022, the first processor core calculates the memory bandwidth size used by the process group for accessing the nonvolatile memory according to the memory bandwidth size and the proportion.

Because the memory address accessed by the memory operation includes the memory address accessed by the non-volatile memory operation executed by the process group and the memory address accessed by the volatile memory operation executed by the process group. The memory type of the memory accessed by the memory operation can be determined to comprise a nonvolatile memory and a volatile memory according to the memory address accessed by the memory operation.

The access amount of the non-volatile memory may be determined according to the memory address accessed by the process group to perform the memory operation of the non-volatile memory. The amount of access to the non-volatile memory may be understood as the memory size of the process group accessing the non-volatile memory.

The access amount of the volatile memory may be determined according to the memory address accessed by the process group to perform the memory operation of the volatile memory. The amount of access to volatile memory may be understood as the memory size of the process group accessing volatile memory.

And further, the first processor core determines the ratio of the access amount of the process group to the nonvolatile memory and the access amount of the process group to the volatile memory according to the memory size of the process group to the nonvolatile memory and the memory size of the process group to the volatile memory.

The memory bandwidth size used by the process group to access the non-volatile memory satisfies equation (1).

B2＝B1*(d2/d1) (1)

B2 represents the memory bandwidth used by the process group in the preset period to access the nonvolatile memory, B1 represents the memory bandwidth used by the process group in the preset period to access the volatile memory, d1 represents the access amount of the process group in the preset period to access the volatile memory, and d2 represents the access amount of the process group in the preset period to access the nonvolatile memory. d2/d1 represents the ratio of the amount of access to the non-volatile memory by the group of processes to the amount of access to the volatile memory by the group of processes.

It can be understood that the first processor core may use the MBM technology to check the information about memory management in the kernel to obtain the memory bandwidth size B1 used by the process group to access the volatile memory in the preset period. d1 and d2 are acquired by the first processor core collecting memory operations of the memory in the system and other memory operations for accessing the memory through the read-write interface of the file system.

For example, a system administrator may assign a unique identifier to a service process of a user, and the first processor core may monitor the size of a memory bandwidth used by a process group to access a volatile memory in a preset period and a memory address accessed by a memory operation executed by the process group by using the identifier. Specifically, the first processor core monitors that a memory bandwidth monitoring value at a starting time T1 of a preset period is Bo, a memory bandwidth monitoring value at an ending time T2 of the preset period is Bn, and an absolute value of a difference between Bn and Bo is a memory bandwidth used by a process group in the preset period to access the volatile memory. Assuming that the memory bandwidth B1 used by the process group to access the volatile memory in the preset period is 10G/s, the first processor core samples memory addresses accessed by 60000 memory operations in the preset period, where 20000 addresses are addresses of the non-volatile memory and 40000 addresses are addresses of the volatile memory. The ratio of the access amount of the process group to the nonvolatile memory to the access amount of the process group to the volatile memory is 20000/40000-0.5. The memory bandwidth used by the process group to access the nonvolatile memory is 20000/40000 × 10G/s-5G/s.

Therefore, the processor core estimates the memory bandwidth used by the process group for accessing the volatile memory based on the nonvolatile memory operation, the volatile memory operation and the memory bandwidth used by the process group for accessing the volatile memory in the preset period, the memory bandwidth of the nonvolatile memory is monitored by taking the process group as granularity through a software method, and the memory bandwidth of the nonvolatile memory is used as a basis for limiting the memory bandwidth of the nonvolatile memory.

Further, after monitoring the memory bandwidth size (for short, the memory bandwidth size of the nonvolatile memory) used by the process group to access the nonvolatile memory, the memory bandwidth size of the nonvolatile memory may be used as a basis for limiting the memory bandwidth of the nonvolatile memory, and the method for limiting the memory bandwidth provided in this embodiment is described in detail with reference to fig. 4.

S401, the first processor core judges whether the memory bandwidth size of the nonvolatile memory is larger than or equal to the nonvolatile memory bandwidth threshold value.

If the memory bandwidth size of the nonvolatile memory is larger than or equal to the nonvolatile memory bandwidth threshold, executing S402; if the memory bandwidth size of the nonvolatile memory is smaller than the nonvolatile memory bandwidth threshold, at this time, if the first processor core has not set the memory bandwidth limit of the process group, S201 and S202 are continuously executed. Optionally, if the first processor core sets a memory bandwidth limit of the process group, S403 is executed. The non-volatile memory bandwidth threshold is the maximum amount of memory bandwidth that is allowed to be used to access the non-volatile memory. The system administrator can set the nonvolatile memory bandwidth threshold value of the nonvolatile memory accessed by different process groups through the second file system interface. For example, the bandwidth of the non-volatile memory allowed to be used by different process groups in each preset period may be limited.

S402, the first processor core sets memory bandwidth limit of the process group.

After the first processor core sets the memory bandwidth limit of the process group, S201 and S202 are executed, that is, the memory bandwidth size used by the process group to access the nonvolatile memory is continuously monitored, and whether the memory bandwidth size of the nonvolatile memory is greater than or equal to the nonvolatile memory bandwidth threshold is determined.

S403, the first processor core relieves the memory bandwidth limitation of the process group.

The first processor core may remove the memory bandwidth limitation of the process group by setting the memory bandwidth limitation of the process group in a reverse operation. After the first processor core removes the memory bandwidth limitation of the process group, S201 and S202 are executed, that is, the memory bandwidth size used by the process group for accessing the nonvolatile memory is continuously monitored, and whether the memory bandwidth size of the nonvolatile memory is greater than or equal to the nonvolatile memory bandwidth threshold is determined.

A specific implementation manner of setting the memory bandwidth limit of the process group by the first processor core is described in detail below.

In a first possible implementation manner, the first processor core adjusts the first volatile memory bandwidth threshold of the process group to the second volatile memory bandwidth threshold. The first volatile memory bandwidth threshold is greater than the second volatile memory bandwidth threshold, and both the first volatile memory bandwidth threshold and the second volatile memory bandwidth threshold refer to the maximum value of the memory bandwidth which is allowed to be used by the process group for accessing the volatile memory. The first processor core may invoke a third file system interface to adjust a maximum amount of memory bandwidth that the process group is allowed to use to access the volatile memory.

In some embodiments, the first processor core may adjust the first volatile memory bandwidth threshold at a granularity of an adjustment step size of 0.2G/s. For example, if the memory bandwidth size of the nonvolatile memory in the ith preset period is greater than or equal to the nonvolatile memory bandwidth threshold, the first processor core reduces the first volatile memory bandwidth threshold by 0.2G/s to obtain a third volatile memory bandwidth threshold, and the third volatile memory bandwidth threshold is greater than the second volatile memory bandwidth threshold. And then, the first processor core obtains the memory bandwidth size of the nonvolatile memory in the (i + 1) th preset period, if the memory bandwidth size of the nonvolatile memory in the (i + 1) th preset period is larger than or equal to the nonvolatile memory bandwidth threshold, the first processor core continuously reduces the third volatile memory bandwidth threshold by 0.2G/s to obtain a fourth volatile memory bandwidth threshold, and the fourth volatile memory bandwidth threshold is larger than the second volatile memory bandwidth threshold. If the memory bandwidth size of the nonvolatile memory in the (i + 1) th preset period is smaller than the nonvolatile memory bandwidth threshold, the memory bandwidth limit of the process group does not need to be set. i is an integer. The system administrator can set the adjustment step length according to factors such as business needs and the like.

If the first processor core adjusts the first volatile memory bandwidth threshold with a granularity of 0.2G/s until the first volatile memory bandwidth threshold is reduced to the second volatile memory bandwidth threshold, but the memory bandwidth size of the nonvolatile memory is still greater than or equal to the nonvolatile memory bandwidth threshold, the first processor executes a second possible implementation manner, that is, the first processor core migrates the process included in the process group from the first processor core running the process group to the second processor core.

It will be appreciated that the second volatile memory bandwidth threshold is the maximum limit of memory bandwidth that the set of processes is restricted from using to access the volatile memory. A system administrator may set the first volatile memory bandwidth threshold through the third file system interface. The system administrator may be a person of the service deployment. For example, a system administrator sets a first volatile memory bandwidth threshold for a process group through a third file system interface by using a Memory Bandwidth Allocation (MBA) technique for a volatile memory.

The maximum value of the memory bandwidth of the volatile memory used by the process group is reduced, namely the process group is limited from accessing the volatile memory, and the memory bandwidth of the volatile memory used by the process group is reduced, so that the total memory bandwidth of the volatile memory and the nonvolatile memory used by the process group is reduced, the memory bandwidth of the nonvolatile memory used by the process group is indirectly reduced, and the memory bandwidth of the nonvolatile memory used by the process group is limited to any value.

In a second possible implementation manner, the first processor core migrates the process included in the process group from the first processor core running the process group to the second processor core, and the second processor core runs the process migrated from the process group. The second processor core may be the first processor core running fewer processes. The number of processes migrated from the first processor core to the second processor core may be set by a system administrator or determined by the system itself. The first processor core may migrate one process at a time or may migrate two processes, without limitation. If the first processor core migrates half of the processes included in the process group to the second processor core, and the memory bandwidth size of the nonvolatile memory is still larger than or equal to the nonvolatile memory bandwidth threshold, the first processor core executes a third possible implementation manner, that is, the first processor core adjusts the first time slice of the process group to the second time slice, and the first time slice is larger than the second time slice.

The number of processes included in the process group operated by the first processor core is reduced, so that the memory operation of the process group on the volatile memory and the nonvolatile memory is reduced, the total memory bandwidth of the process group using the volatile memory and the nonvolatile memory is reduced, the memory bandwidth of the nonvolatile memory indirectly used by the process group is reduced, and the memory bandwidth of the nonvolatile memory is limited to any value.

In some embodiments, the first processor core and the second processor core belong to one or more NUMA nodes in a NUMA system. It is understood that the first processor core and the second processor core belong to the same NUMA node in the NUMA system or that the first processor core and the second processor core belong to different NUMA nodes in the NUMA system.

Typically, a NUMA system includes a plurality of nodes, each node including a plurality of processor cores. A processor contains multiple physical processor cores. Each physical processor core may also be divided into two logical processor cores. A logical processor core in a physical processor may be partitioned into NUMA nodes (or nodes for short).

It is worth noting that the first processor core may be a physical processor core or a logical processor core. If the first processor core is a physical processor core, the first processor core comprises a plurality of logical processor cores. The first processor core and the second processor core may be cores in the same processor or cores in different processors.

For example, as shown in fig. 5, the processor includes 8 processor cores, and the 8 processor cores may be physical processor cores or logical processor cores. The 8 processor cores are divided into 2 nodes. Assuming thatprocessor core 1 runs a process group,processor core 1 may migrate a process in the process group fromprocessor core 1 to processor core 2. Alternatively, theprocessor core 1 may migrate a process in the process group from theprocessor core 1 to theprocessor core 5.

In a third possible implementation manner, the first processor core adjusts the first time slice of the process group to be the second time slice, the first time slice is greater than the second time slice, and both the first time slice and the second time slice are durations when the process group occupies the first processor core. The first processor core can call an interface of the file system to adjust the duration of the process group occupying the first processor core.

The time length of the first processor core allocated to the process group for running the processes in the process group is reduced, so that the time length of the first processor core for running the processes in the process group is shortened, the memory operation of the process group on the volatile memory and the nonvolatile memory is reduced, the total memory bandwidth of the process group using the volatile memory and the nonvolatile memory is reduced, the memory bandwidth of the nonvolatile memory indirectly used by the process group is reduced, and the memory bandwidth of the nonvolatile memory is limited to any value.

The first processor core strengthens or relaxes the limitation on the process group according to the size of the nonvolatile memory bandwidth used by the process group in the ith preset period and the nonvolatile memory bandwidth threshold value, so that the process group is allowed to use less or more nonvolatile memory bandwidth resources in the (i + 1) th preset period.

Therefore, the size of the memory bandwidth used by the process group for accessing the volatile memory is controlled through the limitation measure, and the size of the memory bandwidth used by the process group for accessing the nonvolatile memory is indirectly limited. The problem that other process groups, containers or virtual machines cannot access the nonvolatile memory due to the fact that the process groups, the containers or the virtual machines use excessive nonvolatile memory bandwidth is avoided, and the problem that service performance is degraded and even interrupted due to adjacent position interference fault diffusion is solved.

In the above embodiment, the first processor core optionally limits the memory bandwidth of the nonvolatile memory used by the process group in any one of three possible implementation manners. However, after limiting the memory bandwidth of the non-volatile memory used by the process group, the memory bandwidth size of the non-volatile memory may still be greater than or equal to the non-volatile memory bandwidth threshold. At this time, the first processor core may further dynamically limit the memory bandwidth of the nonvolatile memory, as shown in fig. 6, this embodiment further provides a method for dynamically limiting the memory bandwidth.

S601, the first processor core obtains a first memory bandwidth size used by the process group to access the nonvolatile memory in a preset period.

S602, the first processor core judges whether the first memory bandwidth size of the nonvolatile memory is larger than or equal to the nonvolatile memory bandwidth threshold.

If the first memory bandwidth size used by the process group to access the nonvolatile memory is greater than or equal to the nonvolatile memory bandwidth threshold, S603 is executed. If the first memory bandwidth size used by the process group to access the non-volatile memory is smaller than the non-volatile memory bandwidth threshold, S604 is executed.

S603, the first processor core adjusts the first volatile memory bandwidth threshold of the process group to be a second volatile memory bandwidth threshold. S604 is performed.

S604, the first processor core obtains a second memory bandwidth size used by the process group to access the nonvolatile memory in the preset period.

S605, the first processor core judges whether the second memory bandwidth size of the nonvolatile memory is larger than or equal to the nonvolatile memory bandwidth threshold value.

If the second memory bandwidth size used by the process group to access the nonvolatile memory is greater than or equal to the nonvolatile memory bandwidth threshold, S606 is executed. If the second memory bandwidth size used by the process group to access the nonvolatile memory is smaller than the nonvolatile memory bandwidth threshold, S607 is executed.

Optionally, if the first processor core adjusts the first volatile memory bandwidth threshold of the process group to the second volatile memory bandwidth threshold, the size of the second memory bandwidth used by the process group to access the nonvolatile memory is smaller than the nonvolatile memory bandwidth threshold, and the first processor core may also adjust the second volatile memory bandwidth threshold of the process group to the first volatile memory bandwidth threshold according to the adjustment step size. For example, when the service requirement increases, the first processor core may further adjust the second volatile memory bandwidth threshold of the process group to the first volatile memory bandwidth threshold according to the adjustment step size.

S606, the first processor core migrates the process contained in the process group from the first processor core running the process group to the second processor core. S607 is executed.

S607, the first processor core obtains a third memory bandwidth used by the process group to access the nonvolatile memory in the preset period.

S608, the first processor core determines whether the third memory bandwidth size of the nonvolatile memory is greater than or equal to the nonvolatile memory bandwidth threshold.

If the third memory bandwidth size used by the process group to access the nonvolatile memory is greater than or equal to the nonvolatile memory bandwidth threshold, S609 is executed. If the third memory bandwidth size used by the process group to access the nonvolatile memory is smaller than the nonvolatile memory bandwidth threshold, S610 is executed.

Optionally, if after the first processor core migrates the process included in the process group from the first processor core running the process group to the second processor core, the third memory bandwidth size used by the process group to access the nonvolatile memory is smaller than the nonvolatile memory bandwidth threshold, and the first processor core may also migrate the process included in the process group from the second processor core to the first processor core.

And S609, the first processor core adjusts the first time slice of the process group into a second time slice. S610 is performed.

For a specific method for the first processor core to obtain the memory bandwidth size (including the first memory bandwidth size, the second memory bandwidth size, and the third memory bandwidth size) used by the process group for accessing the nonvolatile memory, reference may be made to the detailed descriptions of S201 and S202, which are not repeated herein. The detailed explanation of S603 may refer to the explanation in the first possible implementation manner described above. The detailed explanation of S606 can refer to the explanation in the second possible implementation manner described above. The detailed explanation of S609 may refer to the above explanation in the third possible implementation.

It should be noted that, after the first processor core limits the memory bandwidth of the nonvolatile memory used by the process group by using one of three possible implementation manners, the memory bandwidth of the nonvolatile memory used by the process group is periodically monitored. The first processor core can acquire the memory bandwidth size of the nonvolatile memory in adjacent preset periods, and also can acquire the memory bandwidth size of the nonvolatile memory in non-adjacent preset periods. For example, the first processor core may obtain a first memory bandwidth size used by the process group to access the nonvolatile memory in an ith preset period, the first processor core may obtain a second memory bandwidth size used by the process group to access the nonvolatile memory in an (i + 1) th preset period, and the first processor core may also obtain a second memory bandwidth size used by the process group to access the nonvolatile memory in an (i + 2) th preset period. i is an integer. The number of cycles of the interval of the memory bandwidth size of the non-volatile memory acquired by the first processor is not limited.

In the above embodiment, the first processor core limits the memory bandwidth of the nonvolatile memory in a dynamic manner. After the memory bandwidth of the nonvolatile memory is limited, if the memory bandwidth of the nonvolatile memory is smaller than the threshold of the memory bandwidth of the nonvolatile memory, the memory bandwidth of the process group can be increased, that is, the limitation on the memory bandwidth of the nonvolatile memory is removed, so that the process group has sufficient available resources. As shown in fig. 7, the present embodiment further provides a method for dynamically limiting the memory bandwidth.

S610, the first processor core obtains a fourth memory bandwidth used by the process group to access the nonvolatile memory in the preset period.

S611, the first processor core determines that the fourth memory bandwidth size of the nonvolatile memory is smaller than the nonvolatile memory bandwidth threshold. S612 is performed.

And S612, the first processor core adjusts the second time slice of the process group into the first time slice. S613 is executed.

The first processor core adjusts the second time slice of the process group into the first time slice, namely, the time length of the process group occupying the processor core is increased, so that the memory operation of the process group on the volatile memory and the nonvolatile memory is increased, the total memory bandwidth of the process group using the volatile memory and the nonvolatile memory is increased, the memory bandwidth of the nonvolatile memory indirectly used by the process group is increased, and the process group has sufficient available resources. The specific adjustment method is a reverse process of adjusting the first time slice of the process group to the second time slice, and specific reference may be made to the specific explanation of the third possible implementation manner above.

S613, the first processor core obtains a fifth memory bandwidth used by the process group to access the nonvolatile memory in the preset period.

And S614, the first processor core determines that the fifth memory bandwidth size of the nonvolatile memory is smaller than the nonvolatile memory bandwidth threshold. S615 is performed.

S615, the first processor core transfers the process contained in the process group from the second processor core to the first processor core. S616 is performed.

It will be appreciated that the process migrated from the second processor core to the first processor core is the process involved in the set of processes from which the first processor core was migrated to the second processor core. The specific migration manner may refer to the specific explanation of the second possible implementation manner. The number of the processes included in the process group operated by the processor core is increased, so that the memory operation of the process group on the volatile memory and the nonvolatile memory is increased, the total memory bandwidth of the process group using the volatile memory and the nonvolatile memory is increased, the memory bandwidth of the nonvolatile memory indirectly used by the process group is also increased, and the process group has sufficient available resources.

S616, the first processor core obtains a sixth memory bandwidth used by the process group to access the nonvolatile memory in the preset period.

S617, the first processor core determines that the sixth memory bandwidth size of the nonvolatile memory is smaller than the nonvolatile memory bandwidth threshold. S618 is executed.

S618, the first processor core adjusts the second volatile memory bandwidth threshold of the process group to the first volatile memory bandwidth threshold. And the first processor core continuously monitors the memory bandwidth size used by the process group for accessing the nonvolatile memory in the preset period. The maximum value of the memory bandwidth of the volatile memory used by the process group is increased, so that the total memory bandwidth of the volatile memory and the nonvolatile memory used by the process group is increased, the memory bandwidth of the nonvolatile memory used by the process group is indirectly increased, and the process group has sufficient available resources. The first processor core may increase the volatile memory bandwidth threshold to the first volatile memory bandwidth threshold according to the adjustment step size. The method for increasing the bandwidth threshold of the volatile memory according to the adjustment step size is a reverse process of decreasing the bandwidth threshold of the volatile memory, and the specific manner of adjusting the bandwidth threshold of the volatile memory may refer to the specific description of the first possible implementation manner.

For a specific method for the first processor core to obtain the memory bandwidth size (including the fourth memory bandwidth size, the fifth memory bandwidth size, and the sixth memory bandwidth size) used by the process group to access the nonvolatile memory, reference may be made to the detailed descriptions of S201 and S202, which are not described in detail.

For example, as shown in fig. 8 (a), in the user mode, the system administrator configures a process group, sets a non-volatile memory bandwidth threshold, and sets a volatile memory bandwidth threshold through different interfaces in the file system. For example, a system administrator configures a process group through a first file system interface. The system administrator sets the non-volatile memory bandwidth threshold through the second file system interface. The system administrator sets a first volatile memory bandwidth threshold through a third file system interface.

The first processor core checks the memory management information in the kernel by adopting an MBM technology to acquire the memory bandwidth size used by the process group to access the volatile memory in a preset period, and acquires the memory operation of the memory in the system and other memory access operations through the read-write interface of the file system. And the monitoring module in the first processor core calculates the memory bandwidth size used by the process group for accessing the nonvolatile memory according to the memory bandwidth size and the counted memory operation. If the memory bandwidth size of the nonvolatile memory is larger than or equal to the nonvolatile memory bandwidth threshold, the limiting module in the first processor core sets the memory bandwidth limitation of the process group by adopting any one of the time slices occupying the first processor core, which are used for adjusting the volatile memory bandwidth threshold, the migration process and the process group.

Assume that the nonvolatile memory bandwidth threshold B2' is 5 GB/s. If the nonvolatile memory bandwidth B2 used by the process group is 3GB/s, at this time, the nonvolatile memory bandwidth 3GB/s used by the process group is lower than the nonvolatile memory bandwidth threshold 5GB/s, that is, B2 ═ 3GB/s < B2 ═ 5GB/s, which does not limit the nonvolatile memory bandwidth used by the process group.

If the bandwidth of the nonvolatile memory used by the process group is 15GB/s, at this time, the bandwidth of the nonvolatile memory used by the process group, 15GB/s, is greater than the threshold value of the bandwidth of the nonvolatile memory, 5GB/s, that is, B2 ═ 15GB/s > B2 ═ 5 GB/s. As shown in fig. 8 (B), the first processor core adjusts the volatile memory bandwidth threshold B1', i.e., adjusts the first volatile memory bandwidth threshold for the process group to the second volatile memory bandwidth threshold.

After the volatile memory bandwidth threshold (maximum limit) is adjusted, the nonvolatile memory bandwidth used by the process group is 12 GB/s. The method comprises the steps that 12GB/s of a nonvolatile memory bandwidth used by a process group is larger than a nonvolatile memory bandwidth threshold value of 5GB/s, namely B2 is 12GB/s > B2' is 5GB/s, and a process of the process group is migrated by a first processor core, namely the process contained in the process group is migrated from the first processor core to a second processor core running the process group.

After the process is migrated, the bandwidth of the nonvolatile memory used by the process group is 6 GB/s. The method comprises the steps that the nonvolatile memory bandwidth 6GB/s used by a process group is larger than the nonvolatile memory bandwidth threshold value 5GB/s, namely B2 is 6GB/s and B2' is 5GB/s, the first processor core adjusts the duration of the process group occupying the first processor core, namely the first time slice of the process group is adjusted to be the second time slice. For example, the first time slice is the duration of a preset period. The second time slice is 83% of the duration of the preset period.

And after the duration (maximum limit) that the process group occupies the first processor core is adjusted, the bandwidth of the nonvolatile memory used by the process group is 1 GB/s. The bandwidth 1GB/s of the nonvolatile memory used by the process group is less than the threshold 5GB/s of the nonvolatile memory bandwidth, namely B2 ═ 1GB/s < B2 ═ 5 GB/s. And the first processor core adjusts the duration of the process group occupying the first processor core, namely, the second time slice of the process group is adjusted to the first time slice.

And after the duration that the process group occupies the first processor core is adjusted, the bandwidth of the nonvolatile memory used by the process group is 2 GB/s. The bandwidth 2GB/s of the nonvolatile memory used by the process group is less than the threshold 5GB/s of the nonvolatile memory bandwidth, namely B2 ═ 2GB/s < B2 ═ 5 GB/s. The first processor core migrates the process of the process group, namely, the process contained in the process group is migrated from the second processor core running the process group to the first processor core.

After the process is migrated, the bandwidth of the nonvolatile memory used by the process group is 3 GB/s. The bandwidth 3GB/s of the nonvolatile memory used by the process group is less than the threshold 5GB/s of the nonvolatile memory bandwidth, i.e. B2 ═ 3GB/s < B2 ═ 5 GB/s. The first processor core adjusts the volatile memory bandwidth threshold, i.e., adjusts the second volatile memory bandwidth threshold of the process group to the first volatile memory bandwidth threshold.

It is understood that, in order to implement the functions of the above embodiments, the server includes a corresponding hardware structure and/or software module for performing each function. Those of skill in the art will readily appreciate that the various illustrative elements and method steps described in connection with the embodiments disclosed herein may be implemented as hardware or combinations of hardware and computer software. Whether a function is performed as hardware or computer software driven hardware depends on the particular application scenario and design constraints imposed on the solution.

The method for monitoring the memory bandwidth and the method for limiting the memory bandwidth provided in the present embodiment are described in detail above with reference to fig. 1 to 8, and the apparatus for monitoring the memory bandwidth, the apparatus for limiting the memory bandwidth, and the server provided in the present embodiment are described below with reference to fig. 9 to 11.

Fig. 9 is a schematic structural diagram of a possible apparatus for monitoring a memory bandwidth according to this embodiment. The devices for monitoring the memory bandwidth can be used for realizing the functions of the processor cores in the method embodiments, so that the beneficial effects of the method embodiments can be realized. In this embodiment, the device for monitoring the memory bandwidth may be theprocessor core 0 shown in fig. 1, or may be a module (e.g., a chip) applied to a server.

As shown in fig. 9, the apparatus 900 for monitoring memory bandwidth includes an obtaining unit 910, a monitoring unit 920, and a limiting unit 930. The apparatus 900 for monitoring memory bandwidth is used to implement the function of the first processor core in the method embodiments shown in fig. 2, fig. 3 or fig. 4.

When the apparatus 900 for monitoring memory bandwidth is used to implement the function of the first processor core in the embodiment of the method shown in fig. 2: the obtaining unit 910 is configured to implement a function executed by the first processor core in S201; the monitoring unit 920 is configured to implement the function performed by the first processor core in S202.

When the apparatus 900 for monitoring memory bandwidth is used to implement the function of the first processor core in the embodiment of the method shown in fig. 3: the obtaining unit 910 is configured to implement a function executed by the first processor core in S201; the monitoring unit 920 is configured to implement the functions performed by the first processor core in S2021 and S2022.

When the apparatus 900 for monitoring memory bandwidth is used to implement the function of the first processor core in the embodiment of the method shown in fig. 4: the obtaining unit 910 is configured to implement a function executed by the first processor core in S201; the monitoring unit 920 is configured to implement the function executed by the first processor core in S202; the restriction unit 930 is configured to implement the functions performed by the first processor core in S401, S402, and S403.

More detailed descriptions about the obtaining unit 910, the monitoring unit 920, and the limiting unit 930 may be directly obtained by referring to the related descriptions in the method embodiments shown in fig. 2, fig. 3, or fig. 4, which are not repeated herein.

Fig. 10 is a schematic structural diagram of a possible device for limiting a memory bandwidth according to this embodiment. The devices for limiting the memory bandwidth can be used to implement the functions of the processor core in the above method embodiment, and therefore, the beneficial effects of the above method embodiment can also be achieved. In this embodiment, the device for limiting the memory bandwidth may be theprocessor core 0 shown in fig. 1, or may be a module (e.g., a chip) applied to a server.

As shown in fig. 10, the apparatus 1000 for limiting memory bandwidth includes an obtaining unit 1010 and a limiting unit 1020. The apparatus 1000 for limiting memory bandwidth is used to implement the function of the first processor core in the method embodiment shown in fig. 6 or fig. 7.

When the apparatus 1000 for limiting memory bandwidth is used to implement the function of the first processor core in the embodiment of the method shown in fig. 6: the obtaining unit 1010 is used for realizing the functions executed by the first processor core in S601, S604, S607 and S610; the restriction unit 1020 is configured to implement the functions performed by the first processor core in S602, S603, S605, S606, S608, and S609.

When the apparatus 1000 for limiting memory bandwidth is used to implement the function of the first processor core in the embodiment of the method shown in fig. 7: the obtaining unit 1010 is configured to implement the functions performed by the first processor core in S610, S613, and S616; the restriction unit 1020 is configured to implement the functions performed by the first processor core in S611, S612, S614, S615, S617, and S618.

More detailed descriptions about the obtaining unit 1010 and the limiting unit 1020 can be directly obtained by referring to the related descriptions in the method embodiment shown in fig. 6 or fig. 7, which are not repeated herein.

It is understood that the Processor in this embodiment may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, a transistor logic device, a hardware component or any combination thereof. The general purpose processor may be a microprocessor, but may be any conventional processor.

The processor may also be a Graphics Processing Unit (GPU), a neural Network Processing Unit (NPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of programs according to the present disclosure.

Fig. 11 is a schematic structural diagram of a server 1100 according to this embodiment. As shown, server 1100 includes aprocessor 1110, abus 1120, acommunication interface 1150, amain memory 1130, and amemory 1140.

It should be understood that in this embodiment, theprocessor 1110 may be a Central Processing Unit (CPU), and theprocessor 1110 may also be other general-purpose processors, Digital Signal Processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general purpose processor may be a microprocessor or any conventional processor or the like.

Thecommunication interface 1150 is used for enabling the server 1100 to communicate with external devices or apparatuses.

Bus 1120 may include a path for communicating information between the above components, such asprocessor 1110,main memory 1130, andmemory 1140. Thebus 1120 may include a power bus, a control bus, a status signal bus, and the like, in addition to a data bus. But for clarity of illustration the various busses are labeled in the drawings asbus 1120.

As one example, the server 1100 may include multiple processors. The processor may be a multi-core (multi-CPU) processor. A processor herein may refer to one or more devices, circuits, and/or computational units for processing data (e.g., computer program instructions). Theprocessor 1110 may monitor the memory bandwidth used by the running process group to access the volatile memory in the preset period, count the memory operations executed by the process group in the preset period, and calculate the memory bandwidth used by the process group to access the nonvolatile memory according to the memory bandwidth and the counted memory operations. And if the memory bandwidth size of the nonvolatile memory is larger than or equal to the nonvolatile memory bandwidth threshold, setting the memory bandwidth limit of the process group. The specific processes of monitoring the memory bandwidth size of the nonvolatile memory and setting the memory bandwidth limit of the process group may be directly obtained by referring to the related descriptions in the foregoing method embodiments, and details are not repeated here.

It is noted that, in fig. 11, only one server 1100 includes 1processor 1110 and 1main memory 1130, where theprocessor 1110 and themain memory 1130 are respectively used to indicate a type of device or apparatus, and in a specific embodiment, the number of each type of device or apparatus may be determined according to business requirements.

Thememory 1140 may be used to store relevant information in a cloud environment, for example, a disk, such as a mechanical hard disk or a solid state disk.

The server 1100 may be a general-purpose device or a special-purpose device. For example, the server 1100 may be a server based on X86, ARM, or other dedicated server, such as Policy Control and Charging (PCC) server. The embodiment of the present application does not limit the type of the server 1100.

It should be understood that the server 1100 according to this embodiment may correspond to the apparatus 900 for monitoring a memory bandwidth and the apparatus 1000 for limiting a memory bandwidth in this embodiment, and may correspond to a corresponding main body for executing any one of the methods according to fig. 2 to fig. 4, and fig. 6 and fig. 7, and the above and other operations and/or functions of each module in the apparatus are not described herein again for brevity in order to implement the corresponding flow of each method in fig. 2 to fig. 4, and fig. 6 and fig. 7, respectively.

The present embodiment further provides a processor, the structure of which is shown in fig. 11, and the processor includes a plurality of processor cores, and is configured to implement the operation steps of the methods shown in fig. 2 to fig. 4, and fig. 6 and fig. 7, and details are not repeated herein in order to avoid repetition.

The method steps in this embodiment may be implemented by hardware, or may be implemented by software instructions executed by a processor. The software instructions may consist of corresponding software modules that may be stored in Random Access Memory (RAM), flash memory, read-only memory (ROM), programmable ROM, Erasable PROM (EPROM), Electrically EPROM (EEPROM), registers, a hard disk, a removable hard disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. Of course, the storage medium may also be integral to the processor. The processor and the storage medium may reside in an ASIC. In addition, the ASIC may reside in a network device or a terminal device. Of course, the processor and the storage medium may reside as discrete components in a network device or a terminal device.

In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are performed in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, a network appliance, a user device, or other programmable apparatus. The computer program or instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer program or instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire or wirelessly. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that integrates one or more available media. The usable medium may be a magnetic medium, such as a floppy disk, a hard disk, a magnetic tape; or optical media such as Digital Video Disks (DVDs); it may also be a semiconductor medium, such as a Solid State Drive (SSD).

While the invention has been described with reference to specific embodiments, the scope of the invention is not limited thereto, and those skilled in the art can easily conceive various equivalent modifications or substitutions within the technical scope of the invention. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (31)

Translated fromChinese

1.一种监控内存带宽的方法，其特征在于，包括：1. a method for monitoring memory bandwidth, is characterized in that, comprising:获取预设周期内进程组访问易失性内存所使用的内存带宽大小，以及统计所述进程组在所述预设周期内执行的内存操作，所述内存操作包括非易失性内存操作和易失性内存操作，所述进程组包括至少一个进程；Obtain the memory bandwidth used by the process group to access the volatile memory in the preset period, and count the memory operations performed by the process group in the preset period, and the memory operations include non-volatile memory operations and volatile memory operations. volatile memory operation, the process group includes at least one process;根据所述内存带宽大小和统计的所述内存操作计算所述进程组访问非易失性内存所使用的第一内存带宽大小。A first memory bandwidth size used by the process group to access the non-volatile memory is calculated according to the memory bandwidth size and the statistical memory operations.2.根据权利要求1所述的方法，其特征在于，所述进程组在所述预设周期内执行的内存操作，包括：2. The method according to claim 1, wherein the memory operation performed by the process group in the preset period comprises:所述进程组在所述预设周期内执行的内存操作所访问的内存地址。The memory address accessed by the memory operation performed by the process group within the preset period.3.根据权利要求1或2所述的方法，其特征在于，根据所述内存带宽大小和统计的所述内存操作计算所述进程组访问非易失性内存所使用的第一内存带宽大小，包括：3. The method according to claim 1 or 2, wherein the first memory bandwidth size used by the process group to access the non-volatile memory is calculated according to the memory bandwidth size and the statistical memory operation, include:根据所述内存操作所访问的内存地址确定所述进程组访问所述非易失性内存的访问量和所述进程组访问所述易失性内存的访问量的比例；Determine the ratio of the access amount of the process group accessing the non-volatile memory to the access amount of the process group accessing the volatile memory according to the memory address accessed by the memory operation;根据所述内存带宽大小和所述比例计算所述进程组访问所述非易失性内存所使用的第一内存带宽大小。A first memory bandwidth size used by the process group to access the non-volatile memory is calculated according to the memory bandwidth size and the ratio.4.根据权利要求3所述的方法，其特征在于，根据所述内存操作所访问的内存地址确定所述进程组访问所述非易失性内存的访问量和所述进程组访问所述易失性内存的访问量的比例，包括：4. The method according to claim 3, wherein, according to the memory address accessed by the memory operation, the access amount of the process group accessing the non-volatile memory and the process group accessing the volatile memory are determined. The proportion of volatile memory accesses, including:根据所述内存操作所访问的内存地址确定所述内存操作的内存大小和内存类型，所述内存类型包括所述易失性内存和所述非易失性内存，所述内存大小包括所述进程组访问所述易失性内存的内存大小和所述进程组访问所述非易失性内存的内存大小；Determine the memory size and memory type of the memory operation according to the memory address accessed by the memory operation, where the memory type includes the volatile memory and the non-volatile memory, and the memory size includes the process the memory size of the group accessing the volatile memory and the memory size of the process group accessing the non-volatile memory;根据所述内存操作的内存大小和所述内存类型确定所述进程组访问所述非易失性内存的访问量和所述进程组访问所述易失性内存的访问量的比例。According to the memory size of the memory operation and the memory type, the ratio of the access amount of the process group accessing the non-volatile memory to the access amount of the process group accessing the volatile memory is determined.5.根据权利要求1-4中任一项所述的方法，其特征在于，所述预设周期内执行的内存操作是全部内存操作或部分内存操作。5. The method according to any one of claims 1-4, wherein the memory operation performed in the preset period is a whole memory operation or a part of the memory operation.6.根据权利要求1-5中任一项所述的方法，其特征在于，所述内存操作为内存读写操作。6. The method according to any one of claims 1-5, wherein the memory operation is a memory read-write operation.7.根据权利要求1-6中任一项所述的方法，其特征在于，在根据所述内存带宽大小和统计的所述内存操作计算所述进程组访问非易失性内存所使用的第一内存带宽大小之后，所述方法还包括：7. The method according to any one of claims 1-6, characterized in that, calculating the number of times used by the process group to access non-volatile memory according to the memory bandwidth size and statistics of the memory operation. After a memory bandwidth size, the method further includes:若所述第一内存带宽大小大于或等于非易失性内存带宽阈值，设置所述进程组的内存带宽限制，所述非易失性内存带宽阈值为所述进程组访问所述非易失性内存允许使用的内存带宽的最大值。If the size of the first memory bandwidth is greater than or equal to a non-volatile memory bandwidth threshold, set a memory bandwidth limit for the process group, and the non-volatile memory bandwidth threshold is the process group accessing the non-volatile memory bandwidth. The maximum amount of memory bandwidth that the memory is allowed to use.8.根据权利要求7所述的方法，其特征在于，设置所述进程组的内存带宽限制包括以下一种或多种：8. The method according to claim 7, wherein setting the memory bandwidth limit of the process group comprises one or more of the following:将所述进程组的第一易失性内存带宽阈值调整为第二易失性内存带宽阈值，所述第一易失性内存带宽阈值大于所述第二易失性内存带宽阈值，所述第一易失性内存带宽阈值和所述第二易失性内存带宽阈值均指所述进程组访问所述易失性内存允许使用的内存带宽的最大值；Adjust the first volatile memory bandwidth threshold of the process group to a second volatile memory bandwidth threshold, where the first volatile memory bandwidth threshold is greater than the second volatile memory bandwidth threshold, and the first volatile memory bandwidth threshold Both the first volatile memory bandwidth threshold and the second volatile memory bandwidth threshold refer to the maximum value of the memory bandwidth that the process group is allowed to use when accessing the volatile memory;将所述进程组包含的进程从运行所述进程组的第一处理器核迁移到第二处理器核；Migrating the processes included in the process group from the first processor core running the process group to the second processor core;将所述进程组的第一时间片调整为第二时间片，所述第一时间片大于所述第二时间片，所述第一时间片和所述第二时间片均为所述进程组占用所述第一处理器核的时长。Adjust the first time slice of the process group to the second time slice, the first time slice is larger than the second time slice, and the first time slice and the second time slice are both the process group The duration of occupying the first processor core.9.根据权利要求8所述的方法，其特征在于，将所述进程组包含的进程从运行所述进程组的第一处理器核迁移到第二处理器核，包括：9. The method according to claim 8, wherein migrating the processes included in the process group from the first processor core running the process group to the second processor core comprises:将所述进程组的第一易失性内存带宽阈值调整为第二易失性内存带宽阈值后，当所述非易失性内存的第二内存带宽大小大于或等于所述非易失性内存带宽阈值，将所述进程组包含的进程从运行所述进程组的第一处理器核迁移到所述第二处理器核。After adjusting the first volatile memory bandwidth threshold of the process group to the second volatile memory bandwidth threshold, when the second memory bandwidth size of the non-volatile memory is greater than or equal to the non-volatile memory A bandwidth threshold, for migrating the processes included in the process group from the first processor core running the process group to the second processor core.10.根据权利要求9所述的方法，其特征在于，将所述进程组的第一时间片调整为第二时间片，包括：10. The method according to claim 9, wherein adjusting the first time slice of the process group to the second time slice, comprising:将所述进程组包含的进程从运行所述进程组的第一处理器核迁移到所述第二处理器核后，当所述非易失性内存的第三内存带宽大小大于或等于所述非易失性内存带宽阈值，将所述进程组的第一时间片调整为所述第二时间片。After the processes included in the process group are migrated from the first processor core running the process group to the second processor core, when the third memory bandwidth size of the non-volatile memory is greater than or equal to the The non-volatile memory bandwidth threshold, adjust the first time slice of the process group to the second time slice.11.根据权利要求10所述的方法，其特征在于，将所述进程组的第一时间片调整为所述第二时间片之后，所述方法还包括：11. The method according to claim 10, wherein after adjusting the first time slice of the process group to the second time slice, the method further comprises:当所述非易失性内存的第四内存带宽大小小于所述非易失性内存带宽阈值，将所述进程组的第二时间片调整为所述第一时间片。When the fourth memory bandwidth size of the non-volatile memory is smaller than the non-volatile memory bandwidth threshold, the second time slice of the process group is adjusted to the first time slice.12.根据权利要求11所述的方法，其特征在于，将所述进程组的第二时间片调整为所述第一时间片之后，所述方法还包括：12. The method according to claim 11, wherein after adjusting the second time slice of the process group to the first time slice, the method further comprises:当所述非易失性内存的第五内存带宽大小小于所述非易失性内存带宽阈值，将所述进程组包含的进程从所述第二处理器核迁移到所述第一处理器核。When the fifth memory bandwidth size of the non-volatile memory is smaller than the non-volatile memory bandwidth threshold, migrate the processes included in the process group from the second processor core to the first processor core .13.根据权利要求12所述的方法，其特征在于，将所述进程组包含的进程从所述第二处理器核迁移到所述第一处理器核之后，所述方法还包括：13. The method according to claim 12, wherein after migrating the processes included in the process group from the second processor core to the first processor core, the method further comprises:当所述非易失性内存的第六内存带宽大小小于所述非易失性内存带宽阈值，将所述进程组的第二易失性内存带宽阈值调整为所述第一易失性内存带宽阈值。When the sixth memory bandwidth size of the non-volatile memory is smaller than the non-volatile memory bandwidth threshold, adjust the second volatile memory bandwidth threshold of the process group to the first volatile memory bandwidth threshold.14.根据权利要求7-13中任一项所述的方法，其特征在于，所述非易失性内存带宽阈值是通过第一文件系统接口设置的。14. The method according to any one of claims 7-13, wherein the non-volatile memory bandwidth threshold is set through a first file system interface.15.根据权利要求8-14中任一项所述的方法，其特征在于，第一易失性内存带宽阈值和第二易失性内存带宽阈值是通过第二文件系统接口设置的。15. The method according to any one of claims 8-14, wherein the first volatile memory bandwidth threshold and the second volatile memory bandwidth threshold are set through a second file system interface.16.根据权利要求8-15中任一项所述的方法，其特征在于，第一处理器核和第二处理器核属于非一致性内存访问NUMA系统中一个或多个NUMA节点。16. The method according to any one of claims 8-15, wherein the first processor core and the second processor core belong to one or more NUMA nodes in a non-coherent memory access NUMA system.17.一种限制内存带宽的方法，其特征在于，包括：17. A method of limiting memory bandwidth, comprising:若进程组在预设周期内访问非易失性内存所使用的第一内存带宽大小大于或等于非易失性内存带宽阈值，将所述进程组的第一易失性内存带宽阈值调整为第二易失性内存带宽阈值，所述非易失性内存带宽阈值为所述进程组访问所述非易失性内存允许使用的内存带宽的最大值，所述第一易失性内存带宽阈值大于所述第二易失性内存带宽阈值，所述第一易失性内存带宽阈值和所述第二易失性内存带宽阈值均指所述进程组访问易失性内存允许使用的内存带宽的最大值，所述进程组包括至少一个进程；If the size of the first memory bandwidth used by the process group to access the non-volatile memory within the preset period is greater than or equal to the non-volatile memory bandwidth threshold, adjust the first volatile memory bandwidth threshold of the process group to the third Two volatile memory bandwidth thresholds, the non-volatile memory bandwidth threshold is the maximum value of the memory bandwidth allowed to be used by the process group accessing the non-volatile memory, and the first volatile memory bandwidth threshold is greater than The second volatile memory bandwidth threshold, the first volatile memory bandwidth threshold, and the second volatile memory bandwidth threshold all refer to the maximum memory bandwidth that the process group is allowed to use when accessing the volatile memory. value, the process group includes at least one process;当所述非易失性内存的第二内存带宽大小大于或等于所述非易失性内存带宽阈值，将所述进程组包含的进程从运行所述进程组的第一处理器核迁移到第二处理器核。When the second memory bandwidth size of the non-volatile memory is greater than or equal to the non-volatile memory bandwidth threshold, migrate the processes included in the process group from the first processor core running the process group to the first processor core running the process group. Two processor cores.18.根据权利要求17所述的方法，其特征在于，在将所述进程组包含的进程从运行所述进程组的第一处理器核迁移到所述第二处理器核之后，所述方法还包括：18. The method according to claim 17, wherein after migrating the processes included in the process group from the first processor core running the process group to the second processor core, the method Also includes:当所述非易失性内存的第三内存带宽大小大于或等于所述非易失性内存带宽阈值，将所述进程组的第一时间片调整为第二时间片，所述第一时间片大于所述第二时间片，所述第一时间片和所述第二时间片均为所述进程组占用所述第一处理器核的时长。When the third memory bandwidth size of the non-volatile memory is greater than or equal to the non-volatile memory bandwidth threshold, the first time slice of the process group is adjusted to the second time slice, the first time slice is greater than the second time slice, and both the first time slice and the second time slice are the length of time during which the process group occupies the first processor core.19.根据权利要求18所述的方法，其特征在于，将所述进程组的第一时间片调整为所述第二时间片之后，所述方法还包括：19. The method according to claim 18, wherein after adjusting the first time slice of the process group to the second time slice, the method further comprises:当所述非易失性内存的第四内存带宽大小小于所述非易失性内存带宽阈值，将所述进程组的第二时间片调整为所述第一时间片。When the fourth memory bandwidth size of the non-volatile memory is smaller than the non-volatile memory bandwidth threshold, the second time slice of the process group is adjusted to the first time slice.20.根据权利要求19所述的方法，其特征在于，将所述进程组的第二时间片调整为所述第一时间片之后，所述方法还包括：20. The method according to claim 19, wherein after adjusting the second time slice of the process group to the first time slice, the method further comprises:当所述非易失性内存的第五内存带宽大小小于所述非易失性内存带宽阈值，将所述进程组包含的进程从所述第二处理器核迁移到所述第一处理器核。When the fifth memory bandwidth size of the non-volatile memory is smaller than the non-volatile memory bandwidth threshold, migrate the processes included in the process group from the second processor core to the first processor core .21.根据权利要求20所述的方法，其特征在于，将所述进程组包含的进程从所述第二处理器核迁移到所述第一处理器核之后，所述方法还包括：21. The method according to claim 20, wherein after migrating the processes included in the process group from the second processor core to the first processor core, the method further comprises:当所述非易失性内存的第六内存带宽大小小于所述非易失性内存带宽阈值，将所述进程组的第二易失性内存带宽阈值调整为所述第一易失性内存带宽阈值。When the sixth memory bandwidth size of the non-volatile memory is smaller than the non-volatile memory bandwidth threshold, adjust the second volatile memory bandwidth threshold of the process group to the first volatile memory bandwidth threshold.22.根据权利要求17-21中任一项所述的方法，其特征在于，所述非易失性内存带宽阈值是通过第一文件系统接口设置的，所述第一易失性内存带宽阈值和所述第二易失性内存带宽阈值是通过第二文件系统接口设置的。22. The method according to any one of claims 17-21, wherein the non-volatile memory bandwidth threshold is set through a first file system interface, and the first volatile memory bandwidth threshold is and the second volatile memory bandwidth threshold is set through the second file system interface.23.根据权利要求17-22中任一项所述的方法，其特征在于，所述第一处理器核和所述第二处理器核属于非一致性内存访问NUMA系统中一个或多个NUMA节点。23. The method according to any one of claims 17-22, wherein the first processor core and the second processor core belong to one or more NUMA systems in a non-uniform memory access NUMA system node.24.一种监控内存带宽的装置，其特征在于，包括：24. A device for monitoring memory bandwidth, comprising:获取单元，用于获取预设周期内进程组访问易失性内存所使用的内存带宽大小，以及统计所述进程组在所述预设周期内执行的内存操作，所述内存操作包括非易失性内存操作和易失性内存操作，所述进程组包括至少一个进程；an acquisition unit, configured to acquire the memory bandwidth used by the process group to access the volatile memory in a preset period, and to count the memory operations performed by the process group in the preset period, and the memory operations include non-volatile memory volatile memory operations and volatile memory operations, the process group includes at least one process;监控单元，用于根据所述内存带宽大小和统计的所述内存操作计算所述进程组访问非易失性内存所使用的第一内存带宽大小。A monitoring unit, configured to calculate a first memory bandwidth size used by the process group to access the non-volatile memory according to the memory bandwidth size and the statistics of the memory operations.25.根据权利要求24所述的装置，其特征在于，在所述监控单元根据所述内存带宽大小和统计的所述内存操作计算所述进程组访问非易失性内存所使用的第一内存带宽大小时，所述监控单元具体用于：25 . The device according to claim 24 , wherein the monitoring unit calculates the first memory used by the process group to access non-volatile memory according to the memory bandwidth size and the statistical memory operation. 26 . When the bandwidth is large, the monitoring unit is specifically used for:根据所述内存操作所访问的内存地址确定所述进程组访问所述非易失性内存的访问量和所述进程组访问所述易失性内存的访问量的比例；Determine the ratio of the access amount of the process group accessing the non-volatile memory to the access amount of the process group accessing the volatile memory according to the memory address accessed by the memory operation;根据所述内存带宽大小和所述比例计算所述进程组访问所述非易失性内存所使用的第一内存带宽大小。A first memory bandwidth size used by the process group to access the non-volatile memory is calculated according to the memory bandwidth size and the ratio.26.根据权利要求24或25所述的装置，其特征在于，所述装置还包括限制单元，26. The device according to claim 24 or 25, characterized in that the device further comprises a restriction unit,所述限制单元，用于若所述第一内存带宽大小大于或等于非易失性内存带宽阈值，设置所述进程组的内存带宽限制，所述非易失性内存带宽阈值为所述进程组访问所述非易失性内存允许使用的内存带宽的最大值。The limiting unit is configured to set a memory bandwidth limit for the process group if the first memory bandwidth size is greater than or equal to a non-volatile memory bandwidth threshold, where the non-volatile memory bandwidth threshold is the process group The maximum amount of memory bandwidth allowed to access the non-volatile memory.27.根据权利要求26所述的装置，其特征在于，所述限制单元，具体用于设置所述进程组的内存带宽限制包括以下一种或多种，27. The apparatus according to claim 26, wherein the limiting unit, specifically configured to set the memory bandwidth limit of the process group, comprises one or more of the following:将所述进程组的第一易失性内存带宽阈值调整为第二易失性内存带宽阈值，所述第一易失性内存带宽阈值大于所述第二易失性内存带宽阈值，所述第一易失性内存带宽阈值和所述第二易失性内存带宽阈值均指所述进程组访问所述易失性内存允许使用的内存带宽的最大值；Adjust the first volatile memory bandwidth threshold of the process group to a second volatile memory bandwidth threshold, where the first volatile memory bandwidth threshold is greater than the second volatile memory bandwidth threshold, and the first volatile memory bandwidth threshold Both the first volatile memory bandwidth threshold and the second volatile memory bandwidth threshold refer to the maximum value of the memory bandwidth that the process group is allowed to use when accessing the volatile memory;将所述进程组包含的进程从运行所述进程组的第一处理器核迁移到第二处理器核；Migrating the processes included in the process group from the first processor core running the process group to the second processor core;将所述进程组的第一时间片调整为第二时间片，所述第一时间片大于所述第二时间片，所述第一时间片和所述第二时间片均为所述进程组占用所述第一处理器核的时长。Adjust the first time slice of the process group to the second time slice, the first time slice is larger than the second time slice, and the first time slice and the second time slice are both the process group The duration of occupying the first processor core.28.一种限制内存带宽的装置，其特征在于，包括：28. A device for limiting memory bandwidth, comprising:限制单元，用于若进程组在预设周期内访问非易失性内存所使用的第一内存带宽大小大于或等于非易失性内存带宽阈值，将所述进程组的第一易失性内存带宽阈值调整为第二易失性内存带宽阈值，所述非易失性内存带宽阈值为所述进程组访问所述非易失性内存允许使用的内存带宽的最大值，所述第一易失性内存带宽阈值大于所述第二易失性内存带宽阈值，所述第一易失性内存带宽阈值和所述第二易失性内存带宽阈值均指所述进程组访问易失性内存允许使用的内存带宽的最大值，所述进程组包括至少一个进程；The limiting unit is configured to restrict the first volatile memory of the process group to The bandwidth threshold is adjusted to the second volatile memory bandwidth threshold, the non-volatile memory bandwidth threshold is the maximum value of the memory bandwidth allowed to be used by the process group accessing the non-volatile memory, and the first volatile memory bandwidth The volatile memory bandwidth threshold is greater than the second volatile memory bandwidth threshold, and both the first volatile memory bandwidth threshold and the second volatile memory bandwidth threshold refer to the process group accessing the volatile memory to allow use of The maximum value of the memory bandwidth, the process group includes at least one process;所述限制单元，还用于当所述非易失性内存的第二内存带宽大小大于或等于所述非易失性内存带宽阈值，将所述进程组包含的进程从运行所述进程组的第一处理器核迁移到第二处理器核。The limiting unit is further configured to, when the second memory bandwidth size of the non-volatile memory is greater than or equal to the non-volatile memory bandwidth threshold, remove the processes included in the process group from running the process group. The first processor core migrates to the second processor core.29.根据权利要求28所述的装置，其特征在于，在所述限制单元将所述进程组包含的进程从运行所述进程组的第一处理器核迁移到所述第二处理器核后，所述限制单元，还用于：29. The apparatus according to claim 28, wherein after the limiting unit migrates the processes included in the process group from the first processor core running the process group to the second processor core , the limiting unit, is also used to:当所述非易失性内存的第三内存带宽大小大于或等于所述非易失性内存带宽阈值，将所述进程组的第一时间片调整为第二时间片，所述第一时间片大于所述第二时间片，所述第一时间片和所述第二时间片均为所述进程组占用所述第一处理器核的时长。When the third memory bandwidth size of the non-volatile memory is greater than or equal to the non-volatile memory bandwidth threshold, the first time slice of the process group is adjusted to the second time slice, the first time slice is greater than the second time slice, and both the first time slice and the second time slice are the length of time during which the process group occupies the first processor core.30.一种服务器，其特征在于，所述服务器包括存储器和处理器，所述处理器包括多个处理器核，所述存储器用于存储一组计算机指令；当所述处理器核执行所述一组计算机指令时，实现上述权利要求1至16中任一项所述的方法。30. A server, characterized in that the server comprises a memory and a processor, the processor comprises a plurality of processor cores, the memory is used to store a set of computer instructions; when the processor core executes the A set of computer instructions implementing the method of any of the preceding claims 1 to 16.31.一种服务器，其特征在于，所述服务器包括存储器和处理器，所述存储器用于存储一组计算机指令；当所述处理器核执行所述一组计算机指令时，实现上述权利要求17至23中任一项所述的方法。31. A server, characterized in that the server comprises a memory and a processor, the memory is used to store a set of computer instructions; when the processor core executes the set of computer instructions, the above claim 17 is implemented The method of any one of to 23.

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