Disclosure of Invention
One of the objects of the present invention is to provide an I2C bus detection apparatus and method, which are implemented by using a gate-level circuit, so that the area of the circuit can be reduced, and the performance of a chip per unit area can be improved.
Another object of the present invention is to provide an I2C bus detection apparatus and method, which has no system clock, is designed for an asynchronous circuit, and can improve the compatibility of modules.
The invention further aims to provide an I2C bus detection device and method, which can reduce the total power consumption of a chip on the basis of reducing the circuit area and can improve the endurance after being applied to mobile equipment.
In order to achieve at least one of the above objects, the present invention further provides an I2C bus detection apparatus, the apparatus comprising:
A bus state detection module;
A counter;
a register set;
A data conversion module;
An address comparison module;
The bus state detection module is connected with the counter, the counter is connected with the data conversion module, the data conversion module is connected with the register set, and the address comparison module is connected with the register set.
According to one preferred embodiment of the present invention, the data conversion module includes an input data serial-to-parallel conversion module and an output data parallel-to-serial conversion module, and the register set includes a first output end and a second output end, wherein the first output end is connected to the input data serial-to-parallel conversion module, and the second output end is connected to the output data parallel-to-serial conversion module.
According to another preferred embodiment of the present invention, the address comparing module includes a slave address comparing module and an on-chip address selecting module, wherein the input data serial-parallel conversion module is connected to the slave address comparing module, the slave address comparing module is connected to the on-chip address selecting module, and the on-chip address selecting module is connected to the register set.
According to another preferred embodiment of the present invention, the device includes a data input interface, a clock input interface and a data output interface, and the counter is a memory having 8 bits, where the data input interface is respectively disposed in the bus state detection module, the input data serial-parallel conversion module and the address comparison module.
According to another preferred embodiment of the present invention, the apparatus includes a data output line enable interface and a reset interface, wherein the data output line enable interface is disposed on the output data parallel-serial conversion module, and the reset interface is disposed on the bus state detection module.
According to another preferred embodiment of the present invention, the register set comprises 9 registers, wherein the 9 registers are configured as 8-bit registers,
According to another preferred embodiment of the present invention, the counter includes a clock signal output interface, and the clock signal output interface is respectively connected to the input data serial-parallel conversion module, the output data parallel-serial conversion module and the address comparison module.
According to another preferred embodiment of the present invention, the bus state detection module includes a clock signal enable interface, and the clock signal enable interface is connected to the counter.
According to another preferred embodiment of the present invention, the bus state detection module includes a signal start interface and a signal stop interface, wherein the signal start interface and the signal stop interface are respectively connected to the counter.
In order to achieve at least one of the above objects, the present invention further provides a method for detecting an I2C bus, including:
The bus state detection module samples a D trigger of an input clock signal on the falling edge of an input data signal to generate a first detection signal;
Sampling the first detection signal at the rising edge of the clock signal to generate a second detection signal, and generating an initial detection signal by taking the inverted signal phases of the first detection signal and the second detection signal;
the clock output signal counts and outputs according to the clock cycle of the clock SCL;
the reset signal and the reset error signal asynchronously clear the count when the reset signal is pulled up;
or when the count enable signal is high and the reference signal is high and address comparison fails, synchronously clearing the count.
According to one preferred embodiment of the present invention, the input serial-parallel conversion module includes a shift register, when the count enable signal is high, serial data is stored in the input serial-parallel conversion module through a data input interface, when the count value is 8, the stored 8-bit serial data is compared with the own slave address by 1 bit, if the comparison is successful, a response signal is recovered, and if the comparison is failed, a non-response signal is recovered, and the host executes communication and non-communication instructions according to the response signal and the non-response signal, respectively.
The present invention further provides a computer readable storage medium storing a computer program executable by a processor for performing the method of detecting an I2C bus.
Detailed Description
The following description is presented to enable one of ordinary skill in the art to make and use the invention. The preferred embodiments in the following description are by way of example only and other obvious variations will occur to those skilled in the art. The basic principles of the invention defined in the following description may be applied to other embodiments, variations, modifications, equivalents, and other technical solutions without departing from the spirit and scope of the invention.
It will be understood that the terms "a" and "an" should be interpreted as referring to "at least one" or "one or more," i.e., in one embodiment, the number of elements may be one, while in another embodiment, the number of elements may be plural, and the term "a" should not be interpreted as limiting the number.
Referring to fig. 1-7, the invention discloses a detection device and a method for an I2C bus, wherein the device comprises a bus state detection module, a counter, a register set, a data conversion module and an address comparison module, wherein the bus state detection module is connected with a corresponding I2C bus for detecting I2C bus related signals, the bus state detection module is connected with the counter, the counter comprises an SCL clock and counts according to the cycle of the SCL clock, the counter is connected with the data conversion module, the data conversion module comprises an input data serial-to-parallel conversion module and an output data parallel-to-serial conversion module, the counter is connected with the input data serial-to-parallel conversion module, the register comprises a first output interface and a second output interface, the first output interface is connected with the input data serial-to-parallel conversion module, the second output interface is connected with the output data parallel-to-serial conversion module, the address comparison module comprises a slave address comparison module and an off-chip address selection module, the input data serial-to-parallel conversion module is connected with the slave address comparison module, and the output port is connected with the address comparison module.
Referring to fig. 2 specifically, the invention discloses an interface schematic diagram of the bus state detection module, wherein the bus state detection module is connected with an i_scl signal line, the i_scl signal line is connected with a clock interface of the bus state detection module and is used for inputting a clock signal (i_scl), the bus state detection module is also connected with an i_sda signal line, the i_sda signal line is connected with a data input interface of the bus state detection module and is used for acquiring a data input signal (i_sda), an output end of the bus state detection module comprises a start signal interface and is used for outputting a start signal (start), the bus state detection module comprises a reference signal interface and is used for outputting a reference signal (rs), the bus state detection module comprises an error reference signal interface and is used for outputting an error reference signal (rs_error), and the bus state detection module comprises a stop signal interface and a count signal enabling interface, the stop signal interface is used for generating a stop signal (stop), and the count signal enabling interface is used for generating a count enabling signal (cnt_en). It should be noted that the bus state detection module may include, but is not limited to, a single chip microcomputer, and the functions may be implemented through different interfaces and logic settings, which is not described in detail in the present invention.
Referring to fig. 3, the input end of the counter includes a start signal interface, a stop signal interface, an error reference signal interface and a count enable interface, which are respectively connected to the start signal interface, the stop signal interface, the error reference signal interface and the count enable interface corresponding to the output end of the bus state detection module, and the output end of the counter includes a count signal output interface for outputting a count signal (cnt_scl), wherein the counter includes a shift register, and the shift register.
Referring to fig. 4, the counter is connected to an input data serial-parallel conversion module, wherein an input end of the input data serial-parallel conversion module includes a count signal input interface, and the count signal input interface is connected to a count signal output interface of the counter, and is used for obtaining a count signal (cnt_scl), wherein an input end of the input data serial-parallel conversion module further includes a data input interface, and wherein the data input interface of the input data serial-parallel conversion module is connected to a register set, and is used for obtaining a data input signal (i_sda) in the register set, and the input data serial-parallel conversion module further includes a clock interface, and the clock interface is connected to the register set, and is used for obtaining an input clock signal (i_scl) in the register set. The input data serial-parallel conversion module comprises an output end, a data signal input interface and a clock signal input interface, wherein the output end of the input data serial-parallel conversion module is used for outputting parallel data (reg_data), the input end of the address comparison module comprises a counting signal input interface, the counting signal input interface is connected with a counting signal output interface of the counter and used for acquiring a counting signal (cnt_scl) on the counter, the input end of the address comparison module further comprises a data signal input interface and a clock signal input interface which are respectively used for acquiring an external data input signal and a clock signal, and the address comparison module further comprises a reference signal input interface which is used for acquiring a reference signal of a storage register. The address comparison module comprises an address matching output interface for outputting an address matching signal (match/rd_match). The input end of the output data parallel-serial conversion module comprises a counting signal input interface, a parallel data input interface, a clock signal input interface and an address matching signal input interface, which are respectively used for receiving a counting signal (cnt_scl), parallel data (reg_data), a clock signal (i_scl) and an address matching signal (match/rd_match), and the signals of the input end of the output data parallel-serial conversion module are obtained from the register set. The output end of the output data parallel-serial conversion module comprises a data output interface and an output data line enabling interface which are respectively used for externally forming a data output signal (o_sda) and generating an enabling signal (o_sda_en) of the output data.
In order to better illustrate the present invention, the present invention further provides a specific I2C bus detection method based on the above-mentioned I2C bus detection device:
The start signal start_cnd0 is detected by a D flip-flop that samples i_scl at its falling edge, and a start_cnd1 signal is generated by sampling start_cd0 at its rising edge. The start pulse signal is formed by the inverse of the start_cnd0 signal and the start_cnd1 signal, and is the actual circuit start signal. The cnt_en signal will pull high when the i_scl falling edge detects that the start signal is high and asynchronously reset when the stop signal is high. After cnt_en is pulled high, cnt_scl will count SCL clock cycles at i_scl rising edge until cnt_en is low and the count value is not increased any more, and the count value is cleared asynchronously after rs_error signal and stop signal are pulled high. The shift register in the input serial-parallel conversion unit stores serial data of the i_sda line when cnt_en is high, and stores 8-bit data of the i_sda line when cnt_scl is 8, and compares the serial data with the own 7-bit slave address plus 1-bit write (low), wherein o_sda_en is an o_sda enable signal pulled high, and o_sda outputs an opposite value of a comparison result, namely, comparison success pulled low o_sda and comparison failure pulled high o_sda, so as to reply a response signal ACK or a non-response signal NACK. The upper 8-bit and lower 8-bit addresses of the internal registers are compared when cnt_scl is 17 and 26, respectively. And after the response, if the rs signal is not pulled high, the rs signal is read, and the rs signal detection method is consistent with the start signal, but is kept asynchronous zero clearing after the stop is high. During a read operation, the selected register is written with the value of the shift register 0 at the moment when the count is 35, after the response signal is replied, the host sends a stop signal stop, the register configuration is completed, the stop signal i_sda signal rising edge sampling i_scl is generated, and the asynchronous zero clearing is performed when the next start signal is pulled high. If rs is high, the data in the shift register 0 is compared when cnt_scl counts to 36, the comparison value is that the slave address is added with 1 bit to read (high), if the comparison is successful, the 8-bit data of the selected configuration register is written into the shift register 1 at the falling edge of i_scl, and the next 8 i_scl clock periods i_sda sequentially output 8 data. The communication is ended after the host replies the non-response signal and the termination signal. If an abnormal repeated starting signal is detected in the transmission process, the rs_error signal generates a single-period pulse to asynchronously clear the count value of the counter, and if the ending signal is abnormal, the transmission is directly ended.
In particular, according to embodiments of the present disclosure, the processes described above with reference to flowcharts may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a computer readable medium, the computer program comprising program code for performing the method shown in the flowcharts. In such embodiments, the computer program may be downloaded and installed from a network via a communication portion, and/or installed from a removable medium. The above-described functions defined in the method of the present application are performed when the computer program is executed by a Central Processing Unit (CPU). The computer readable medium of the present application may be a computer readable signal medium or a computer readable storage medium, or any combination of the two. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of a computer-readable storage medium may include, but are not limited to, an electrical connection having one or more wire segments, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In the present application, however, the computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, with the computer-readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless segments, radio lines, fiber optic cables, RF, etc., or any suitable combination of the foregoing.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
It will be understood by those skilled in the art that the embodiments of the present invention described above and shown in the drawings are merely illustrative and not restrictive of the current invention, and that this invention has been shown and described with respect to the functional and structural principles thereof, without departing from such principles, and that any modifications or adaptations of the embodiments of the invention may be possible and practical.