Disclosure of Invention
In order to solve the technical problems, the invention provides an avalanche photodiode and a preparation method thereof. The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview and is intended to neither identify key/critical elements nor delineate the scope of such embodiments. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is presented later.
The invention adopts the following technical scheme:
In some alternative embodiments, an avalanche photodiode is provided comprising a substrate comprising a top layer substrate and an avalanche multiplication layer over the top layer substrate;
The top layer substrate comprises a top layer central region and a first surrounding region, wherein the net effective doping concentration of the top layer central region is larger than that of the first surrounding region so as to form an electric field control table top.
Further, a middle region is arranged at the bottom of the avalanche multiplication layer, and doped impurities in the central region of the top layer are diffused into the middle region, so that the net effective doping concentration of the middle region is larger than that of other regions of the avalanche multiplication layer to form the upper half part of the electric field control table top. Further, the top layer substrate further comprises a second surrounding area surrounding the first surrounding area, and the net effective doping concentration of the second surrounding area is larger than or equal to that of the first surrounding area.
The substrate comprises a top layer substrate, a bottom layer substrate, a middle layer substrate and a middle layer surrounding area, wherein the middle layer substrate comprises a middle layer central area and a middle layer surrounding area, the position of the middle layer surrounding area corresponds to the position of the second surrounding area, the position of the middle layer central area corresponds to the position of the top layer central area and the position of the first surrounding area, and the net effective doping concentration of the middle layer surrounding area is more than or equal to the net effective doping concentration of the middle layer central area.
Further, a top contact layer, an absorption layer and a charge control layer are sequentially arranged on the top of the avalanche multiplication layer from top to bottom;
The top contact layer is made of germanium or polysilicon, the absorption layer is made of germanium, germanium-silicon alloy, germanium-silicon quantum dots or germanium-silicon quantum hydrazines, the charge control layer and the avalanche multiplication layer are made of silicon, the middle layer substrate and the top layer substrate are made of silicon, and the bottom layer substrate is made of silicon or a combination of silicon oxide and silicon.
In some alternative embodiments, the invention provides a method for preparing an avalanche photodiode, comprising doping a top layer center region of a top layer substrate of the avalanche photodiode with different degrees from a first surrounding region, so that a net effective doping concentration of the top layer center region is greater than a net effective doping concentration of the first surrounding region to form an electric field control mesa.
Further, the preparation method of the avalanche photodiode further comprises the step of carrying out a diffusion process to diffuse the doped impurities in the central region of the top layer to the avalanche multiplication layer, so that the net effective doping concentration of the middle region of the avalanche multiplication layer is greater than that of other regions of the avalanche multiplication layer to form the upper half part of the electric field control table top.
Further, the process of doping the top layer center region of the top layer substrate of the avalanche photodiode and the first surrounding region to different degrees comprises the steps of carrying out compensation doping with the polarity opposite to that of the avalanche photodiode on the first surrounding region of the top layer substrate of the avalanche photodiode or carrying out heavy doping on the top layer center region of the top layer substrate of the avalanche photodiode.
Further, the method includes preparing a substrate;
when the first surrounding area needs to be subjected to compensation doping, the prepared substrate is an undoped substrate or a lightly doped substrate or a heavily doped substrate, and when the substrate is an undoped substrate or a lightly doped substrate, the method further comprises the steps of carrying out heavy doping on a top layer substrate and a middle layer substrate of the avalanche photodiode;
when the top layer central region is required to be heavily doped, the prepared substrate is an undoped substrate or a lightly doped substrate, and the method further comprises the step of heavily doping the middle layer substrate of the avalanche photodiode.
Further, the preparation method of the avalanche photodiode further comprises the steps of carrying out heavy doping on the second surrounding area, and controlling doping depth to enable the doping area to be expanded to the middle-layer substrate.
The invention has the beneficial effects that the design and the manufacturing method of the APD with the SACM structure are provided, and particularly, the APD with the Ge/Si structure can be used for an electric field control table top without using a special epitaxial layer and a special one-step epitaxial process, and the invention has the advantages that a one-step time-consuming epitaxial process flow is omitted, so that the process period can be effectively shortened, the parameter uncertainty caused by the epitaxial process is reduced, the consumption of epitaxial tools and gas raw materials is reduced, and the APD can be ensured to have lower dark current and higher multiplication coefficient.
Detailed Description
The following description and the drawings sufficiently illustrate specific embodiments of the invention to enable those skilled in the art to practice them. Other embodiments may involve structural, logical, electrical, process, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in, or substituted for, those of others.
The net effective doping concentration mentioned herein refers to the doping concentration after the doping concentration of two or more doping impurities in the same region and the doping concentrations of the impurities with opposite electric polarities are offset, and the doping concentrations with the same electric polarities are overlapped.
Doping is to add conductive elements into the semiconductor, such as trivalent boron or pentavalent phosphorus into tetravalent silicon and germanium to improve conductivity, and the more the doping is, the stronger the conductivity of the semiconductor material is. The invention is divided into undoped, lightly doped, medium doped and heavy doped according to the proportion of doped impurities so as to represent doping amounts of different grades, wherein the doping amounts are undoped, lightly doped, medium doped and heavy doped.
In some illustrative embodiments, as shown in FIG. 1, an avalanche photodiode is provided, which includes, in order from top to bottom, a top contact layer 1, an absorption layer 2, a charge control layer 3, an avalanche multiplication layer 4, and a substrate, including a top substrate 5, a middle substrate 6, and a bottom substrate 7.
The top substrate 5 is sequentially provided with a top central region 5D, a first surrounding region 5E and a second surrounding region 5A from inside to outside. The middle layer substrate 6 is sequentially provided with a middle layer central area 6B and a middle layer surrounding area 6C from inside to outside. The position of the middle surrounding area 6C corresponds to the position of the second surrounding area 5A, and the position of the middle central area 6B corresponds to the positions of the top central area 5D and the first surrounding area 5E.
The substrate is divided into three layers, the substrate can be processed respectively, the bottommost layer is a common substrate and can support a structure which is the same as the common process, and different doping is carried out in the second layer and the third layer, so that the electric field control table top can be formed.
The net effective doping concentration of the top layer center region 5D is greater than the net effective doping concentration of the first surrounding region 5E to form an electric field control mesa, and thus the electric field control mesa is located in the top layer center region 5D, the net effective doping concentration of the first surrounding region 5E may be one thousandth or less of the net effective doping concentration of the top layer center region 5D. The net effective doping concentration of the second surrounding region 5A is equal to or greater than the net effective doping concentration of the first surrounding region 5E. The net effective doping concentration of the middle surrounding region 6C is equal to or greater than the net effective doping concentration of the middle central region 6B.
The electric field controls the mesa to have a substantially high doping concentration in the central region and a substantially low doping concentration in the region surrounding it, so that the resistivity of the mesa region is less or substantially less than the resistivity of the region surrounding it, whereby the potential at the mesa differs from the potential of the region surrounding it when a voltage is applied, the greater the difference in resistivity and the greater the difference in potential. The top central region 5D is doped with a higher concentration than the first surrounding region 5E, which is a necessary condition for forming the electric field control mesa, and the second surrounding region 5A is also doped with a higher concentration than the first surrounding region 5E, which is required to reduce the resistivity at this location. The middle surrounding region 6C may be doped with a higher concentration than the middle centralizer 6B, also to reduce the resistivity therein. Typically, the outermost regions of the substrate, such as the second surrounding region 5A and the middle surrounding region 6C, should have as low a resistivity as possible, since ohmic contacts are required there, so that the contact resistance can be reduced as much as possible.
In one embodiment, the top contact layer 1 is made of germanium or polysilicon, the absorption layer 2 is made of germanium, a germanium-silicon alloy, germanium-silicon quantum dots or germanium-silicon quantum hydrazines, the charge control layer 3 and the avalanche multiplication layer 4 are made of silicon, the middle layer substrate 6 and the top layer substrate 5 are made of silicon, the bottom layer substrate 7 is made of silicon or a combination of silicon oxide and silicon, and the silicon oxide is located above the silicon in the second case.
As shown in fig. 1,2,3 and 7, the top contact layer 1 comprises a top contact central region 11 and a top contact surrounding region 12 from inside to outside, wherein the top contact central region 11 is P-type heavily doped polysilicon, and the top contact surrounding region 12 is undoped polysilicon. The absorption layer 2 is germanium. The charge control layer 3 is P-type medium doped silicon. The avalanche multiplication layer 4 is intrinsic or lightly doped silicon, and can be doped with N type or P type when lightly doped. The middle central region 6B, the middle surrounding region 6C and the second surrounding region 5A are made of N-type heavily doped silicon. The top central region 5D is N-type medium doped silicon. The first surrounding region 5E is undoped silicon or N-type lightly doped silicon or P-type doped silicon.
As shown in fig. 2, the net effective doping concentrations of the middle central region 6B, the middle surrounding region 6C, and the second surrounding region 5A may be the same.
In some illustrative embodiments, the second surrounding region 5A may be heavily doped again, with the electrical polarity of the doped impurities remaining consistent with the existing doping. In this doping, the doping depth can be controlled to be below the second surrounding region 5A of the top substrate, i.e. the middle surrounding region 6C of the middle substrate is also doped, and the specific structure is shown in fig. 3, where the net effective doping concentration of the middle surrounding region 6C and the second surrounding region 5A can be greater than the net effective doping concentration of the middle central region 6B, or greater than the net effective doping concentration of the top central region 5D, i.e. the electric field control mesa.
The first surrounding region 5E has the same or opposite electric polarity as the other regions of the substrate, the opposite electric polarity is shown in fig. 7, the first surrounding region 5E is a P-type doped region, the same electric polarity is shown in fig. 2 and 3, and the first surrounding region 5E is an undoped or N-type lightly doped region.
As shown in fig. 8, the bottom of the avalanche multiplication layer 4 is provided with a middle region 41, and the doped impurities of the top central region 5D diffuse into the middle region 41, so that the net effective doping concentration of the middle region is greater than the other regions of the avalanche multiplication layer to form the upper half of the electric field control mesa, and the top central region 5D serves as the lower half of the electric field control mesa. The width of the electric field control mesa is approximately the same as the width of the top central region 5D.
At this time, the structure of the APD is shown in fig. 9 and 10, and the top contact layer 1 includes, from inside to outside, a top contact central region 11 and a top contact surrounding region 12, where the top contact central region 11 is P-type heavily doped polysilicon, and the top contact surrounding region 12 is undoped polysilicon. The absorption layer 2 is germanium. The charge control layer 3 comprises a charge control center region 31 and a charge control surrounding region 32 from inside to outside, and the charge control layer 3 is P-type medium doped silicon. The avalanche multiplication layer 4 is intrinsic or lightly doped silicon and the middle region 41 is N-type mid-doped silicon. The top and middle substrates 5 and 6 are heavily doped silicon of N type. The underlying substrate 7 is of a material of silicon or a combination of silicon oxide and silicon, in the second case silicon oxide being located above the silicon.
As shown in fig. 9, the net effective doping concentrations of the first surrounding region 5E and the second surrounding region 5A are the same, and the net effective doping concentrations of the middle surrounding region 6C and the middle central region 6B are the same, which may not be distinguished. As shown in fig. 10, the net effective doping concentration of the second surrounding region 5A and the middle surrounding region 6C may be greater than the net effective doping concentration of the middle central region 6B and the first surrounding region 5E.
In some illustrative embodiments, as shown in fig. 4, a method of making an avalanche photodiode is provided, comprising:
S1, manufacturing an SOI or bulk silicon substrate with special doping distribution, wherein the doping impurity is N type. The structure with special doping distribution refers to the structure manufactured by the process shown in fig. 5 and 6, namely, the structure with special doping distribution of the middle layer substrate and the top layer substrate.
S2, manufacturing an avalanche multiplication layer 4.
And S3, manufacturing a charge control layer 3.
S4, manufacturing an absorption layer 2.
S5, manufacturing a top contact layer 1.
When the substrate is manufactured, the top central region 5D and the first surrounding region 5E of the top substrate 5 of the avalanche photodiode are doped to different degrees, so that the net effective doping concentration of the top central region 5D is greater than that of the first surrounding region 5E to form the electric field control mesa.
The process of doping the top layer center region 5D of the top layer substrate of the avalanche photodiode with different degrees than the first surrounding region 5E includes compensation doping of the first surrounding region 5E of the top layer substrate of the avalanche photodiode with opposite polarity to the avalanche photodiode or heavy doping of the top layer center region 5D of the top layer substrate of the avalanche photodiode.
As shown in fig. 5, when the electric field control mesa is only located on the top substrate 5 and the first surrounding region 5E of the top substrate of the avalanche photodiode is doped with a compensation opposite to the avalanche photodiode, step S1 includes the following steps:
s51, preparing an undoped substrate or an N-type lightly doped substrate;
s52, N-type heavy doping is carried out on the top layer substrate 5 and the middle layer substrate 6;
S53, P-type doping is carried out on the first surrounding area 5E of the top layer substrate, namely compensation doping with opposite electric polarities is carried out, the P-type doping is compensation doping, the concentration of the area after compensation is far less than that of the top layer central area 5D when the area is net doped into N-type, or the electric polarities of net effective doping impurities of the compensated top layer central area 5D can be opposite to the electric polarities of the substrate, the structure with opposite electric polarities is shown in figure 7, and the structure with the same electric polarities is shown in figures 2 and 3;
S54, N-type heavy doping is carried out on the second surrounding area 5A of the top layer substrate and the middle layer surrounding area 6C of the middle layer substrate, wherein the step is an optional step, and heavy doping is carried out on the second surrounding area 5A again, so that the doping concentration of a doping position can be increased, and the resistivity is further reduced;
S55, N-type heavy doping is carried out on the top layer central region 5D of the top layer substrate and the middle layer central region 6B of the middle layer substrate, the step is an optional step, the heavy doping is carried out on the top layer central region 5D, the doping concentration of the central region can be further improved, the doping concentration of the first surrounding region 5E is unchanged, the doping concentration contrast of the two regions is further increased, the electric field control table top is enabled to be more outstanding, the larger the doping concentration contrast is, the larger the resistivity difference between the center and the edge is, and the larger the electric potential difference is.
At this time, the structure of the prepared photodetector is shown in fig. 2, and at this time, the net effective doping concentration of the top central region 5D of the top substrate, i.e., the electric field control mesa, is the same as the net effective doping concentration of the second surrounding regions 5A of the middle substrate and the top substrate.
In some illustrative embodiments, step S56 may be substituted for step S51 and step S52. S56, preparing an N-type heavily doped substrate, wherein the structure of the prepared photoelectric detector is shown in fig. 2, and the net effective doping concentration of a top layer center region 5D of the top layer substrate, namely an electric field control table top, is the same as the net effective doping concentration of a second surrounding region 5A of the middle layer substrate and the top layer substrate.
As shown in fig. 6, when the electric field control mesa is located only on the top substrate 5 and the top central region 5D of the top substrate of the avalanche photodiode is heavily doped, step S1 includes the steps of:
S61, preparing an undoped substrate or a lightly doped substrate;
s62, carrying out N-type heavy doping on the middle substrate 6;
s63, carrying out N-type heavy doping on the top layer central region 5D and the second surrounding region 5A of the top layer substrate;
S64, carrying out N-type heavy doping on the second surrounding area 5A of the top layer substrate, wherein the step is an optional step, and carrying out heavy doping on the second surrounding area 5A again, so that the doping concentration of a doping position can be increased, and the resistivity is further reduced;
S65, P-type doping is carried out on the first surrounding area 5E of the top layer substrate, wherein the step is an optional step, impurity atoms with opposite polarities are doped, the net effective N-type doping concentration of the first surrounding area 5E is further reduced, and therefore the doping concentration difference between the first surrounding area 5E and the top layer central area 5D is increased.
At this time, the structure of the prepared photodetector is shown in fig. 2 and 3, and the net effective doping concentration of the top central region 5D of the top substrate, i.e., the electric field control mesa, is the same as the net effective doping concentration of the second surrounding regions 5A of the middle substrate and the top substrate.
In some illustrative embodiments, the top central region 5D and the second surrounding region 5A of the top substrate may be heavily doped N-type in two steps, and thus, step S66 and step S67 are used instead of step S63 and step S64. The step S66 is to make N-type heavy doping on the top central region 5D of the top substrate, and the step S67 is to make N-type heavy doping on the second surrounding region 5A of the top substrate. At this time, the structure of the prepared photodetector is shown in fig. 2, and at this time, the net effective doping concentration of the top central region 5D of the top substrate, that is, the electric field control mesa, may be the same as or different from the net effective doping concentration of the second surrounding regions 5A of the middle substrate and the top substrate.
In the above method for manufacturing a substrate, after all the steps are completed, optionally, the second surrounding area 5A of the top substrate is heavily doped again, and the doping depth is controlled to extend the doped area to the middle substrate 6, so that the device structure in the specific embodiment is shown in fig. 3. And the heavy doping is carried out again, so that the doping concentration of the doping position can be increased, and the resistivity is further reduced.
Generally, the doped impurities need to be activated and diffused at high temperature, which belongs to the standard semiconductor process, and the process flows of fig. 4-6 are not repeated.
The invention further comprises performing a diffusion process to diffuse the doping impurities of the top central region 5D of the top substrate into the avalanche multiplication layer 4 such that the net effective doping concentration of the middle region 41 of the avalanche multiplication layer 4 is greater than the other regions of the avalanche multiplication layer to form the upper half of the electric field control mesa. At this time, the preparation flow of the avalanche photodiode is shown in fig. 11, and includes the following steps:
s111, preparing an N-type heavily doped substrate.
S112, N-type heavy doping is performed on the second surrounding area 5A of the top layer substrate, the doping depth is controlled to be expanded to the middle layer substrate, the step is optional, the device structure in the specific embodiment is shown in FIG. 10, heavy doping is performed on the second surrounding area 5A again, the doping concentration of the doping position can be increased, and the resistivity is further reduced.
S113, N-type doping is carried out in the top layer central region 5D of the top layer substrate, the electric polarity of the doped impurities is the same as that of the original doped impurities of the heavily doped substrate, and optionally, the atomic mass of the impurity doped again can be smaller than that of the impurity atoms in the original heavily doped substrate.
And S114, preparing an avalanche multiplication layer.
S115, performing diffusion process, namely activating and diffusing doped impurities, wherein the heavily doped impurities in the top layer central region 5D of the top layer substrate are diffused to the bottom of the avalanche multiplication layer to form an electric field control table surface, and the effect of doping the top layer central region of the top layer substrate to perform the diffusion process is shown in FIG. 12.
The diffusion process is a common CMOS standard process and mainly comprises the steps of depositing a layer of substances containing impurity atoms to be diffused, placing the substances in a high-temperature environment for a period of time under a protective gas atmosphere, completing diffusion, and cooling and taking out a chip.
And S116, preparing a charge control layer.
S117, preparing an absorption layer.
And S118, preparing a top contact layer.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.