技术领域Technical Field
本申请涉及半导体制造技术领域，具体涉及一种DMOS器件及其形成方法。The present application relates to the field of semiconductor manufacturing technology, and in particular to a DMOS device and a method for forming the same.
背景技术Background technique
双扩散金属氧化物半导体场效应管(double-diffused metal-oxide-semiconductor field-effect transistor，DMOSFET，本申请中简称为“DMOS”)由于具有耐高压、大电流驱动能力和极低功耗等特点，被广泛应用于电源管理电路中。Double-diffused metal-oxide-semiconductor field-effect transistor (DMOSFET, referred to as "DMOS" in this application) is widely used in power management circuits due to its high voltage resistance, large current driving capability and extremely low power consumption.
DMOS主要有两种类型：垂直双扩散金属氧化物半导体场效应管(verticaldouble-diffused metal-oxide-semiconductor field-effect transistor，VDMOSFET，可简称为“VDMOS”)和横向双扩散金属氧化物半导体场效应管(lateral double-diffusedmetal-oxide-semiconductor field-effect transistor，LDMOSFET，本申请中简称为“LDMOS”)。对于LDMOS器件，导通电阻(specific on-resistance，Rsp)、击穿电压(brakevoltage，BV)以及关态漏电流(off-state leakage current，Ioff)是衡量其电学性能的重要参数。There are two main types of DMOS: vertical double-diffused metal-oxide-semiconductor field-effect transistor (VDMOSFET, referred to as "VDMOS") and lateral double-diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET, referred to as "LDMOS" in this application). For LDMOS devices, specific on-resistance (Rsp ), breakdown voltage (BV) and off-state leakage current (Ioff ) are important parameters for measuring their electrical performance.
参考图1，其示出了相关技术中提供的一种LDMOS器件的剖面示意图，如图1所示，背面衬底101上形成有埋层氧化层102，埋层氧化层102上形成有顶层硅103，顶层硅103上形成有栅绝缘介质层105，栅绝缘介质层105上形成有栅极多晶硅106，栅极多晶硅106的两侧生长有侧墙109，器件的有源区(active area，AA)的周侧的顶层硅103中形成有浅槽隔离(shallow trench isolation，STI)结构104，栅极多晶硅106两侧的顶层硅103中形成有轻掺杂漏(lightly doped drain，LDD)区107，轻掺杂漏区107中形成有重掺杂区110，在轻掺杂漏区107各自面对的边缘形成有口袋(pocket)注入区(通过晕环(halo)注入或口袋注入形成)108。Referring to FIG. 1 , a cross-sectional schematic diagram of an LDMOS device provided in the related art is shown. As shown in FIG. 1 , a buried oxide layer 102 is formed on a back substrate 101, a top silicon layer 103 is formed on the buried oxide layer 102, a gate insulating dielectric layer 105 is formed on the top silicon layer 103, a gate polysilicon 106 is formed on the gate insulating dielectric layer 105, sidewalls 109 are grown on both sides of the gate polysilicon 106, a shallow trench isolation (STI) structure 104 is formed in the top silicon 103 on the peripheral side of the active area (AA) of the device, a lightly doped drain (LDD) region 107 is formed in the top silicon 103 on both sides of the gate polysilicon 106, a heavily doped region 110 is formed in the lightly doped drain region 107, and pocket implantation regions (formed by halo implantation or pocket implantation) 108 are formed at the edges facing each other of the lightly doped drain regions 107.
相关技术中提供的LDMOS器件中，轻掺杂漏区的边缘至口袋注入区的边缘的宽度大致相同，可将口袋注入区的形貌视为轻掺杂漏区的平移，当施加较高的电压时，器件内的碰撞电离容易发生在顶层硅表面的轻掺杂漏区与口袋注入区的界面处(如图1中虚线所示)，从而导致顶层硅表面的离子浓度过大，且口袋注入区表面区域过宽不利于提高器件的击穿电压，降低关态漏电流，进而降低了器件的电学性能。In the LDMOS device provided in the related art, the width from the edge of the lightly doped drain region to the edge of the pocket injection region is roughly the same, and the morphology of the pocket injection region can be regarded as a translation of the lightly doped drain region. When a higher voltage is applied, impact ionization in the device is likely to occur at the interface between the lightly doped drain region and the pocket injection region on the surface of the top silicon (as shown by the dotted line in Figure 1), resulting in an excessively high ion concentration on the surface of the top silicon. The excessively wide surface area of the pocket injection region is not conducive to improving the breakdown voltage of the device, reducing the off-state leakage current, and thus reducing the electrical performance of the device.
发明内容Summary of the invention
本申请提供了一种DMOS器件及其形成方法，可以解决相关技术中提供的DMOS器件电学性能较差的问题。The present application provides a DMOS device and a method for forming the same, which can solve the problem of poor electrical performance of the DMOS device provided in the related art.
一方面，本申请实施例提供了一种DMOS器件，包括：On the one hand, an embodiment of the present application provides a DMOS device, including:
衬底，所述衬底上形成有栅绝缘介质层；A substrate having a gate insulating dielectric layer formed thereon;
栅极，所述栅极形成于所述栅绝缘介质层上；A gate, the gate being formed on the gate insulating dielectric layer;
所述栅极两侧的衬底中形成有轻掺杂漏区，所述轻掺杂漏区中形成有重掺杂区，所述轻掺杂漏区之间的衬底中形成有口袋注入区，所述口袋注入区与所述轻掺杂漏区接触，沿所述衬底的厚度的方向，所述口袋注入区的横向宽度从上至下越来越宽。Lightly doped drain regions are formed in the substrate on both sides of the gate, heavily doped regions are formed in the lightly doped drain regions, pocket injection regions are formed in the substrate between the lightly doped drain regions, the pocket injection regions are in contact with the lightly doped drain regions, and along the thickness direction of the substrate, the lateral width of the pocket injection regions becomes wider from top to bottom.
可选的，所述衬底从下至上依次包括背面衬底、埋层氧化层和顶层硅；Optionally, the substrate includes, from bottom to top, a back substrate, a buried oxide layer and a top silicon layer;
所述轻掺杂漏区、所述重掺杂区和所述口袋注入区形成于所述顶层硅中。The lightly doped drain region, the heavily doped region and the pocket implant region are formed in the top silicon layer.
可选的，所述口袋注入区包覆所述轻掺杂漏区在所述顶层硅的上表面和所述埋层氧化层的上表面之间的表面。Optionally, the pocket implantation region covers a surface of the lightly doped drain region between an upper surface of the top silicon layer and an upper surface of the buried oxide layer.
可选的，所述口袋注入区通过口袋离子注入或晕环离子注入形成。Optionally, the pocket injection region is formed by pocket ion injection or halo ion injection.
可选的，所述DMOS器件为开关管DMOS器件。Optionally, the DMOS device is a switch tube DMOS device.
另一方面，本申请实施例提供了一种DMOS器件的形成方法包括：On the other hand, an embodiment of the present application provides a method for forming a DMOS device, including:
提供一衬底，所述衬底上形成有栅绝缘介质层，所述栅绝缘介质层上形成有栅极，所述栅极两侧的衬底中形成有轻掺杂漏区；A substrate is provided, wherein a gate insulating dielectric layer is formed on the substrate, a gate is formed on the gate insulating dielectric layer, and lightly doped drain regions are formed in the substrate on both sides of the gate;
进行第一次离子注入，在所述轻掺杂漏区之间的衬底中形成口袋注入区，所述口袋注入区与所述轻掺杂漏区接触，沿所述衬底的厚度的方向，所述口袋注入区的横向宽度从上至下越来越宽；Performing a first ion implantation to form a pocket implantation region in the substrate between the lightly doped drain regions, wherein the pocket implantation region contacts the lightly doped drain regions, and the lateral width of the pocket implantation region becomes wider from top to bottom along the thickness direction of the substrate;
进行第二次离子注入，在所述轻掺杂漏区中形成重掺杂区。A second ion implantation is performed to form a heavily doped region in the lightly doped drain region.
可选的，所述进行第一次离子注入，包括：Optionally, the first ion implantation includes:
通过口袋离子注入或晕环离子注入进行所述第一次离子注入。The first ion implantation is performed by pocket ion implantation or halo ion implantation.
可选的，其特征在于，Optionally, it is characterized in that
可选的，所述衬底从下至上依次包括背面衬底、埋层氧化层和顶层硅；Optionally, the substrate includes, from bottom to top, a back substrate, a buried oxide layer and a top silicon layer;
所述轻掺杂漏区、所述重掺杂区和所述口袋注入区形成于所述顶层硅中。The lightly doped drain region, the heavily doped region and the pocket implant region are formed in the top silicon layer.
可选的，所述口袋注入区包覆所述轻掺杂漏区在所述顶层硅的上表面和所述埋层氧化层的上表面之间的表面。Optionally, the pocket implantation region covers a surface of the lightly doped drain region between an upper surface of the top silicon layer and an upper surface of the buried oxide layer.
可选的，所述DMOS器件为开关管DMOS器件。Optionally, the DMOS device is a switch tube DMOS device.
本申请技术方案，至少包括如下优点：The technical solution of this application has at least the following advantages:
通过在DMOS器件的轻掺杂漏区之间的衬底中形成口袋注入区，该口袋注入区沿衬底的厚度的方向，其横向宽度从上至下越来越宽，从而在衬底表面形成一个更加缓变的结，从而能够减弱器件内的碰撞电离强度，提高了该器件的击穿电压，同时降低了器件的关态漏电流，提高了器件的电学性能。By forming a pocket injection region in the substrate between the lightly doped drain regions of the DMOS device, the lateral width of the pocket injection region becomes wider from top to bottom along the thickness direction of the substrate, thereby forming a more gradual junction on the substrate surface, thereby weakening the impact ionization intensity in the device, improving the breakdown voltage of the device, and reducing the off-state leakage current of the device, thereby improving the electrical performance of the device.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
为了更清楚地说明本申请具体实施方式或现有技术中的技术方案，下面将对具体实施方式或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
图1是相关技术中提供的一种LDMOS器件的剖面示意图；FIG1 is a cross-sectional schematic diagram of an LDMOS device provided in the related art;
图2是本申请一个示例性实施例提供的DMOS器件的剖面示意图；FIG2 is a cross-sectional schematic diagram of a DMOS device provided by an exemplary embodiment of the present application;
图3是本申请一个示例性实施例提供的DMOS器件的形成方法的流程图。FIG. 3 is a flow chart of a method for forming a DMOS device provided by an exemplary embodiment of the present application.
具体实施方式Detailed ways
下面将结合附图，对本申请中的技术方案进行清楚、完整的描述，显然，所描述的实施例是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在不做出创造性劳动的前提下所获得的所有其它实施例，都属于本申请保护的范围。The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.
在本申请的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”、“第三”仅用于描述目的，而不能理解为指示或暗示相对重要性。In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电气连接；可以是直接相连，也可以通过中间媒介间接相连，还可以是两个元件内部的连通，可以是无线连接，也可以是有线连接。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
此外，下面所描述的本申请不同实施方式中所涉及的技术特征只要彼此之间未构成冲突就可以相互结合。In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
参考图2，其示出了本申请一个示例性实施例提供的DMOS器件的剖面示意图，如图2所示，本申请实施例中，DMOS器件的栅极从俯视角度观察为矩形，定义该矩形的长所在的方向为X轴，该矩形的宽所在的方向为Y轴，衬底的厚度所在的方向为Z轴进行描述，该DMOS器件可以是开关管DMOS器件，其包括：Referring to FIG. 2 , a cross-sectional schematic diagram of a DMOS device provided by an exemplary embodiment of the present application is shown. As shown in FIG. 2 , in the embodiment of the present application, the gate of the DMOS device is a rectangle when viewed from a top view, and the direction in which the length of the rectangle is defined as the X-axis, the direction in which the width of the rectangle is defined as the Y-axis, and the direction in which the thickness of the substrate is defined as the Z-axis for description. The DMOS device may be a switch tube DMOS device, which includes:
衬底，其上形成有栅绝缘介质层205。A substrate having a gate insulating dielectric layer 205 formed thereon.
该衬底可以是硅衬底、具有外延层的硅衬底或绝缘硅(silicon-on-insulator，SOI)衬底。如图2所示，以绝缘硅衬底为例，进行说明：该衬底从下至上(本申请实施例中，上方是朝向栅极206的方向，下方是朝向背面衬底201的方向)依次包括背面衬底201、埋层氧化层202和顶层硅203，顶层硅203的表面形成有栅绝缘介质层205，该栅绝缘介质层205可包括硅氧化物(例如，二氧化硅(SiO2))层。The substrate may be a silicon substrate, a silicon substrate with an epitaxial layer, or a silicon-on-insulator (SOI) substrate. As shown in FIG2 , an insulating silicon substrate is taken as an example for explanation: the substrate includes, from bottom to top (in the embodiment of the present application, the top is the direction toward the gate 206, and the bottom is the direction toward the back substrate 201), a back substrate 201, a buried oxide layer 202, and a top silicon layer 203, a gate insulating dielectric layer 205 is formed on the surface of the top silicon layer 203, and the gate insulating dielectric layer 205 may include a silicon oxide (e.g., silicon dioxide (SiO2 )) layer.
栅极206，其形成于栅绝缘介质层205上。The gate 206 is formed on the gate insulating dielectric layer 205 .
栅极206两侧的衬底中形成有轻掺杂漏区207，轻掺杂漏区207中形成有重掺杂区210，轻掺杂漏区207之间的衬底中形成有口袋注入区208，口袋注入区208与轻掺杂漏区207接触，口袋注入区208之间不接触，沿Z轴方向，口袋注入区208的横向宽度(即沿X轴方向的宽墩)从上至下越来越宽。Lightly doped drain regions 207 are formed in the substrate on both sides of the gate 206, heavily doped regions 210 are formed in the lightly doped drain regions 207, pocket injection regions 208 are formed in the substrate between the lightly doped drain regions 207, the pocket injection regions 208 are in contact with the lightly doped drain regions 207, and the pocket injection regions 208 are not in contact with each other. Along the Z-axis direction, the lateral width of the pocket injection region 208 (i.e., the width along the X-axis direction) becomes wider from top to bottom.
示例性的，如图2所示，轻掺杂漏区207、重掺杂区210和口袋注入区208形成于顶层硅203中，沿Z轴方向，口袋注入区208的横向宽度从上至下越来越宽，且口袋注入区208包覆轻掺杂漏区207在顶层硅203的上表面和埋层氧化层202的上表面之间的表面，因此，口袋注入区208在顶层硅203的上表面具有较窄的宽度(如图2中椭圆形虚线所示)，从而在顶层硅203的表面形成一个更加缓变的结，从而能够减弱器件内的碰撞电离强度。Exemplarily, as shown in FIG2 , a lightly doped drain region 207, a heavily doped region 210 and a pocket injection region 208 are formed in the top silicon 203. Along the Z-axis direction, the lateral width of the pocket injection region 208 becomes wider and wider from top to bottom, and the pocket injection region 208 covers the surface of the lightly doped drain region 207 between the upper surface of the top silicon 203 and the upper surface of the buried oxide layer 202. Therefore, the pocket injection region 208 has a narrower width on the upper surface of the top silicon 203 (as shown by the elliptical dotted line in FIG2 ), thereby forming a more gradual junction on the surface of the top silicon 203, thereby being able to weaken the impact ionization intensity within the device.
其中，口袋注入区208通过口袋离子注入或晕环离子注入形成；口袋注入区208中的杂质类型与顶层硅203中的杂质类型相同，轻掺杂漏区207中的杂质类型与顶层硅203中的杂质类型不同，重掺杂区210中的杂质类型与顶层硅203中的杂质类型不同；重掺杂区210中的杂质浓度大于轻掺杂漏区207中的杂质浓度以及口袋注入区208中的杂质浓度。Among them, the pocket injection region 208 is formed by pocket ion implantation or halo ion implantation; the impurity type in the pocket injection region 208 is the same as the impurity type in the top silicon 203, the impurity type in the lightly doped drain region 207 is different from the impurity type in the top silicon 203, and the impurity type in the heavily doped region 210 is different from the impurity type in the top silicon 203; the impurity concentration in the heavily doped region 210 is greater than the impurity concentration in the lightly doped drain region 207 and the impurity concentration in the pocket injection region 208.
当顶层硅203中的杂质类型为P(positive)型时，口袋注入区208中的杂质类型为P型，轻掺杂漏区207中的杂质类型为N(negative)型，重掺杂区210中的杂质类型为N型；当顶层硅203中的杂质类型为N型时，口袋注入区208中的杂质类型为N型，轻掺杂漏区207中的杂质类型为P型，重掺杂区210中的杂质类型为P型。When the impurity type in the top silicon 203 is P (positive) type, the impurity type in the pocket injection region 208 is P type, the impurity type in the lightly doped drain region 207 is N (negative) type, and the impurity type in the heavily doped region 210 is N type; when the impurity type in the top silicon 203 is N type, the impurity type in the pocket injection region 208 is N type, the impurity type in the lightly doped drain region 207 is P type, and the impurity type in the heavily doped region 210 is P type.
可选的，DMOS器件的有源区(active area，AA)的周侧的顶层硅203形成有浅槽隔离(shallow trench isolation，STI)结构204；可选的，栅极206和栅绝缘介质层205的两侧形成有侧墙209。Optionally, a shallow trench isolation (STI) structure 204 is formed on the top silicon layer 203 around the active area (AA) of the DMOS device; optionally, sidewall spacers 209 are formed on both sides of the gate 206 and the gate insulating dielectric layer 205 .
综上所述，本申请实施例中，通过在DMOS器件的轻掺杂漏区之间的衬底中形成口袋注入区，该口袋注入区沿衬底的厚度的方向，其横向宽度从上至下越来越宽，从而在衬底表面形成一个更加缓变的结，从而能够减弱器件内的碰撞电离强度，提高了该器件的击穿电压，同时降低了器件的关态漏电流，提高了器件的电学性能。To summarize, in the embodiments of the present application, a pocket injection region is formed in the substrate between the lightly doped drain regions of the DMOS device, and the lateral width of the pocket injection region becomes wider from top to bottom along the thickness direction of the substrate, thereby forming a more gradual junction on the surface of the substrate, thereby weakening the impact ionization intensity within the device, improving the breakdown voltage of the device, and at the same time reducing the off-state leakage current of the device, thereby improving the electrical performance of the device.
参考图3，其示出了本申请一个示例性实施例提供的DMOS器件的形成方法，该方法可应用于图2实施例中提供的DMOS器件的制造中，该方法包括：Referring to FIG. 3 , a method for forming a DMOS device provided in an exemplary embodiment of the present application is shown. The method can be applied to the manufacture of the DMOS device provided in the embodiment of FIG. 2 . The method includes:
步骤301，提供一衬底，衬底上形成有栅绝缘介质层，栅绝缘介质层上形成有栅极，栅极两侧的衬底中形成有轻掺杂漏区。Step 301, providing a substrate, a gate insulating dielectric layer is formed on the substrate, a gate is formed on the gate insulating dielectric layer, and lightly doped drain regions are formed in the substrate at both sides of the gate.
步骤302，进行第一次离子注入，在轻掺杂漏区之间的衬底中形成口袋注入区，口袋注入区与轻掺杂漏区接触，沿衬底的厚度的方向，口袋注入区的横向宽度从上至下越来越宽。Step 302, performing the first ion implantation to form a pocket implantation region in the substrate between the lightly doped drain regions, the pocket implantation region contacts the lightly doped drain regions, and the lateral width of the pocket implantation region becomes wider from top to bottom along the thickness direction of the substrate.
其中，第一次离子注入的杂质包括氟化硼(BF2)和硼(B)，可将氟化硼的注入能量控制为30千电子伏特(KeV)至100千电子伏特，硼的注入能量控制为10千电子伏特至40千电子伏特，杂质的注入剂量控制为5×1012至1×1014每平方厘米，离子注入的倾斜角度控制为10度(°)至45度，以形成本申请实施例中的口袋注入区208的形貌。Among them, the impurities of the first ion implantation include boron fluoride (BF2 ) and boron (B), the implantation energy of boron fluoride can be controlled to be 30 kiloelectronvolts (KeV) to 100 kiloelectronvolts (KeV), the implantation energy of boron can be controlled to be 10 kiloelectronvolts to 40 kiloelectronvolts, the implantation dose of impurities can be controlled to be 5×1012 to 1×1014 per square centimeter, and the inclination angle of ion implantation can be controlled to be 10 degrees (°) to 45 degrees to form the morphology of the pocket implantation region 208 in the embodiment of the present application.
步骤303，进行第二次离子注入，在轻掺杂漏区中形成重掺杂区。Step 303 , performing a second ion implantation to form a heavily doped region in the lightly doped drain region.
形成得到的DMOS器件可参考图2实施例，在此不做赘述。The DMOS device thus formed may refer to the embodiment shown in FIG. 2 , and will not be described in detail here.
显然，上述实施例仅仅是为清楚地说明所作的举例，而并非对实施方式的限定。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。而由此所引伸出的显而易见的变化或变动仍处于本申请创造的保护范围之中。Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.
| Application Number | Priority Date | Filing Date | Title |
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| CN202111119225.5ACN113871451B (en) | 2021-09-24 | 2021-09-24 | DMOS device and method for forming the same |
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| CN202111119225.5ACN113871451B (en) | 2021-09-24 | 2021-09-24 | DMOS device and method for forming the same |
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| CN202111119225.5AActiveCN113871451B (en) | 2021-09-24 | 2021-09-24 | DMOS device and method for forming the same |
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