CN113870764A - Pixel circuit and display panel - Google Patents

Abstract

Translated fromChinese

本发明实施例公开了一种像素电路和显示面板，像素电路包括数据写入模块、存储模块、电压选择模块和发光模块，通过设置电压选择模块包括第一传输门和第二传输门，且第一传输门和第二传输门均包括至少两个并联的不同沟道类型的晶体管，相对于单个晶体管来说不同沟道类型的晶体管之间可以实现特性互补，以及具有更小的导通电阻，进而可以具有更快的导通和关断速度，快速实现对第一电源电压和第二电源电压的选择，进而精确快速地控制发光模块的亮暗状态，可以使得发光模块的发光时长可以得到精确控制，进而在每一帧内准确显示灰阶，进而保证良好的显示效果。

The embodiment of the present invention discloses a pixel circuit and a display panel. The pixel circuit includes a data writing module, a storage module, a voltage selection module, and a light-emitting module. The voltage selection module includes a first transmission gate and a second transmission gate by setting the voltage selection module, and the first transmission gate Both the first transmission gate and the second transmission gate include at least two parallel-connected transistors of different channel types. Compared with a single transistor, the transistors of different channel types can realize complementary characteristics and have smaller on-resistance. Furthermore, it can have a faster turn-on and turn-off speed, quickly realize the selection of the first power supply voltage and the second power supply voltage, and then accurately and quickly control the light and dark states of the light-emitting module, so that the light-emitting duration of the light-emitting module can be accurately obtained. Control, and then accurately display the gray scale in each frame, thereby ensuring a good display effect.

Description

Pixel circuit and display panel

Technical Field

The embodiment of the invention relates to the technical field of display, in particular to a pixel circuit and a display panel.

Background

With the development of display technology, the requirements for display effects are also higher and higher.

The conventional pixel circuit generally includes a plurality of transistors and a light emitting device, and the transistors control the brightness of the light emitting device, thereby controlling gray scale switching.

However, the existing display panel has the problems of poor transistor characteristics, slow on/off switching speed, slow control speed of the light-emitting device in the bright and dark states and poor display effect.

Disclosure of Invention

The invention provides a pixel circuit and a display panel, which are used for quickly controlling the bright and dark states of a light-emitting device and realizing that the display gray scale can be quickly switched, thereby ensuring a good display effect.

In a first aspect, an embodiment of the present invention provides a pixel circuit, including a data writing module, a storage module, a voltage selection module, and a light emitting module;

the data writing module is used for writing the data voltage into the storage module, and the storage module is used for storing the data voltage;

the voltage selection module is electrically connected with the storage module and comprises a first transmission gate and a second transmission gate, the first transmission gate and the second transmission gate respectively comprise at least two transistors which are connected in parallel and have different channel types, the voltage selection module is used for controlling the conduction states of the first transmission gate and the second transmission gate according to the storage data voltage of the storage module, transmitting a first power voltage to the light emitting module to enable the light emitting module to be lightened when the first transmission gate is conducted, and transmitting a second power voltage to the light emitting module to enable the light emitting module to be turned off when the second transmission gate is conducted.

Optionally, the first transmission gate includes a first control terminal, a second control terminal, a first input terminal and a first output terminal, and the second transmission gate includes a third control terminal, a fourth control terminal, a second input terminal and a second output terminal; the first input end is electrically connected with the first power supply voltage input end, and the second input end is electrically connected with the second power supply voltage input end;

the voltage selection module further comprises an inverter, the input end of the inverter is electrically connected with the storage module, the input end of the inverter is also electrically connected with the first control end and the third control end respectively, and the output end of the inverter is electrically connected with the second control end and the fourth control end respectively; the first output end of the first transmission gate and the second output end of the second transmission gate are electrically connected with the light-emitting module;

the first transmission gate is used for conducting according to signals of the first control end and the second control end when an input signal of the input end of the inverter is a first voltage signal; the second transmission gate is used for being conducted according to signals of the third control terminal and the fourth control terminal when an input signal of the input end of the inverter is a second voltage signal.

Optionally, the first transmission gate includes a first transistor and a second transistor, and the second transmission gate includes a third transistor and a fourth transistor, where the channel types of the first transistor and the fourth transistor are the same, the channel types of the second transistor and the third transistor are the same, and the channel types of the first transistor and the second transistor are different;

the grid electrode of the first transistor is used as a first control end, the grid electrode of the second transistor is used as a second control end, the first pole of the first transistor and the first pole of the second transistor are both electrically connected with the first power supply voltage input end, and the second pole of the first transistor and the second pole of the second transistor are both electrically connected with the first output end;

the grid electrode of the third transistor is used as a third control end, the grid electrode of the fourth transistor is used as a fourth control end, the first pole of the third transistor and the first pole of the fourth transistor are both electrically connected with the second power supply voltage input end, and the second pole of the third transistor and the second pole of the fourth transistor are both electrically connected with the second output end. Through setting up first transmission gate and second transmission gate and all including two parallelly connected transistors, and the type of two transistors is different, and transistor characteristic is complementary in realizing first transmission gate and second transmission gate, reduces on-resistance, and then realizes selecting fast first mains voltage and second mains voltage, and then carries out the basis of quick control to light emitting module's bright dark state, can be so that the quantity of transistor is less in the pixel circuit, and then be favorable to improving pixel density.

Optionally, the pixel circuit further includes a reset module, where the reset module is configured to provide a second voltage signal to the input terminal of the inverter at least in an initial stage of one frame, so as to turn on the second transmission gate;

the reset module is further used for resetting the storage module at least in an initial stage of one frame. Residual charges of a frame on the light emitting module can be cleared; so that the data voltage stored by the memory module can also be cleared.

Optionally, one frame includes at least two subframes, and the reset module is configured to provide the second voltage signal to the input terminal of the inverter at an initial stage in each subframe to turn on the second transmission gate; the reset module is also used for resetting the storage module in the initial stage in each subframe. Residual charges of a frame on the light emitting module can be cleared; so that the data voltage stored by the memory module can also be cleared.

Optionally, the control end of the reset module is electrically connected to the reset control signal end, the first end of the reset module is used for accessing the second voltage signal, and the second end of the reset module is electrically connected to the input end of the inverter;

optionally, the second voltage signal is provided by the first supply voltage input.

Optionally, the storage module includes a latch, an input end of the latch is electrically connected to the data writing module, and an output end of the latch is electrically connected to the voltage selection module;

the latch comprises a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor, wherein the grid electrode of the fifth transistor is electrically connected with the grid electrode of the sixth transistor, the first electrode of the fifth transistor is electrically connected with the third power supply voltage input end, the second electrode of the fifth transistor is electrically connected with the first electrode of the sixth transistor, and the second electrode of the sixth transistor is electrically connected with the fourth power supply voltage input end;

a gate of the seventh transistor is electrically connected to a gate of the eighth transistor, a first pole of the seventh transistor is electrically connected to the third power supply voltage input terminal, a second pole of the seventh transistor is electrically connected to the first pole of the eighth transistor, and a second pole of the eighth transistor is electrically connected to the fourth power supply voltage input terminal;

a common terminal of a gate of the fifth transistor and a gate of the sixth transistor is electrically connected to the second pole of the seventh transistor, and the gate of the fifth transistor and the gate of the sixth transistor serve as input terminals of the latch;

a common terminal of a gate of the seventh transistor and a gate of the eighth transistor is electrically connected to the second diode of the fifth transistor; the second pole of the fifth transistor and the first pole of the sixth transistor are used as output ends of the latch;

the channel types of the fifth transistor and the seventh transistor are the same, the channel types of the sixth transistor and the eighth transistor are the same, and the channel types of the fifth transistor and the sixth transistor are different; this arrangement enables the data voltage to be maintained more satisfactorily.

Optionally, the third power supply voltage input terminal and the first power supply voltage input terminal are the same input terminal; the number of power supplies for supplying power to the pixel circuit can be reduced, which is advantageous for cost saving.

Optionally, the fourth supply voltage input and the second supply voltage input Vss1 are the same input. The number of power supplies for supplying power to the pixel circuit can be reduced, which is advantageous for cost saving.

Optionally, the first transmission gate and the second transmission gate are both electrically connected to the first end of the light emitting module, and the second end of the light emitting module is electrically connected to the fifth power voltage input end; preferably, the fifth supply voltage input and the second supply voltage input are the same input.

Optionally, the data writing module includes a ninth transistor, and is configured to transmit the data voltage at the data voltage input end to the storage module under the control of a first scan signal accessed to a gate of the ninth transistor;

optionally, the data writing module further includes a tenth transistor, the tenth transistor and the ninth transistor are connected in parallel, and the channel type of the tenth transistor is opposite to that of the ninth transistor; the gate of the tenth transistor is used for receiving a second scanning signal, and the level of the second scanning signal is opposite to that of the first scanning signal. For single transistor, turn on and turn off speed and accelerate, and then can realize the quick transmission to storage module to the data voltage to and realize the quick disconnection of data voltage input and storage module, and then be favorable to the promotion of display effect.

In a second aspect, an embodiment of the present invention further provides a display panel, including the pixel circuit provided in the first aspect.

The embodiment of the invention provides a pixel circuit and a display panel, wherein the pixel circuit comprises a data writing module, a storage module, a voltage selection module and a light-emitting module, by arranging the voltage selection module to comprise the first transmission gate and the second transmission gate, and the first transmission gate and the second transmission gate both comprise at least two transistors which are connected in parallel and have different channel types, characteristic complementation can be realized between the transistors with different channel types relative to a single transistor, and the on-state resistance of the transistor is smaller, thereby having faster on and off speed, quickly realizing the selection of the first power supply voltage and the second power supply voltage, and then the bright and dark state of the light-emitting module is accurately and quickly controlled, so that the light-emitting duration of the light-emitting module can be accurately controlled, the gray scale can be accurately displayed in each frame, and the good display effect can be ensured.

Drawings

Fig. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;

fig. 3 is a driving timing diagram of a pixel circuit according to an embodiment of the invention;

fig. 4 is another driving timing diagram of a pixel circuit according to an embodiment of the invention;

fig. 5 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram of a display panel according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

As described in the background art, the conventional display panel has the problems of poor transistor characteristics and low on/off switching speed, which results in poor display effect. The inventor researches and discovers that the problems are caused because the conventional display panel comprises a plurality of pixel circuits, each pixel circuit usually comprises a plurality of transistors, and in the manufacturing process of the display panel, the problems that the characteristics of partial transistors are poor due to unavoidable process factors, and the on-resistance of a single transistor is usually large, so that the on-off switching speed is slow, the transistors cannot be turned on or off in time during gray scale switching, and particularly for a digital driving pixel circuit, the display gray scale is determined by the light emitting duration of a light emitting device, so that the light emitting duration of the light emitting device is inaccurate due to the fact that the transistors cannot be turned on or off in time, and further the display gray scale is inaccurate, and the display effect is influenced.

In view of the above problems, an embodiment of the present invention provides a pixel circuit, which includes a data writing module, a storage module, a voltage selection module, and a light emitting module; the data writing module is used for writing the data voltage into the storage module, and the storage module is used for storing the data voltage; the voltage selection module is electrically connected with the storage module and comprises a first transmission gate and a second transmission gate, the first transmission gate and the second transmission gate respectively comprise at least two transistors which are connected in parallel and have different channel types, the voltage selection module is used for controlling the conduction states of the first transmission gate and the second transmission gate according to the storage data voltage of the storage module, transmitting a first power voltage to the light emitting module to enable the light emitting module to be lightened when the first transmission gate is conducted, and transmitting a second power voltage to the light emitting module to enable the light emitting module to be turned off when the second transmission gate is conducted.

Specifically, the transmission gate includes at least two parallel transistors with different channel types, so that the characteristics of the two transistors with different channel types are complementary, and the at least two parallel transistors are equivalent to the structure of a single transistor, and the on-resistance is reduced, so that the problem of slow on-speed caused by poor characteristics and large on-resistance of the single transistor can be solved; when light emitting module need turn-off (becoming dark promptly), the data voltage according to the storage module storage of first transmission gate is turn-off fast, and the data voltage that the second transmission gate was saved according to the storage module switches on fast, and then transmits second mains voltage to light emitting module for light emitting module becomes dark fast, and then the accurate bright and dark state of controlling light emitting module fast. Optionally, the pixel circuit of this embodiment may be a digital driving pixel circuit, and in the digital driving pixel circuit, the display gray scale is determined by the light emitting duration of the light emitting module, so that the display gray scale is accurate by accurately and rapidly controlling the bright and dark states of the light emitting module, and the display gray scale can be rapidly switched, thereby ensuring a good display effect.

The pixel circuit of the embodiment comprises a first transmission gate and a second transmission gate by arranging the voltage selection module, wherein the first transmission gate and the second transmission gate comprise at least two transistors which are connected in parallel and have different channel types, the characteristics of the transistors which are different from the channel type can be complemented with each other compared with a single transistor, and the transistors have smaller on-resistance, so that the pixel circuit can have faster on-off speed, the selection of the first power supply voltage and the second power supply voltage is realized rapidly, the bright and dark state of the light-emitting module is controlled precisely and rapidly, the light-emitting duration of the light-emitting module can be controlled precisely, the gray scale can be displayed accurately in each frame, and a good display effect is ensured.

The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without any creative work belong to the protection scope of the present invention.

Fig. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention, and referring to fig. 1, the pixel circuit includes a data writing module 110, amemory module 120, avoltage selection module 130, and alight emitting module 140, and thevoltage selection module 130 includes a first transmission gate 131 and a second transmission gate 132.

Optionally, the first transmission gate 131 includes a first control terminal G1, a second control terminal G2, a first input terminal and a first output terminal, and the second transmission gate 132 includes a third control terminal G3, a fourth control terminal G4, a second input terminal and a second output terminal; the first input is electrically connected to a first supply voltage input Vdd1 and the second input is electrically connected to a second supply voltage input Vss 1.

Thevoltage selection module 130 further includes aninverter 133, an input terminal of theinverter 133 is electrically connected to thememory module 120, input terminals of theinverter 133 are electrically connected to the first control terminal G1 and the third control terminal G3, respectively, and output terminals of theinverter 133 are electrically connected to the second control terminal G2 and the fourth control terminal G4, respectively; a first output terminal of the first transmission gate 131 and a second output terminal of the second transmission gate 132 are electrically connected to thelight emitting module 140.

The first transmission gate 131 is configured to be turned on according to signals of the first control terminal G1 and the second control terminal G2 when the input signal of the input terminal of theinverter 133 is a first voltage signal; the second transmission gate 132 is configured to be turned on according to signals of the third control terminal G3 and the fourth control terminal G4 when the input signal of the input terminal of theinverter 133 is the second voltage signal.

In particular, the first supply voltage input Vdd1 may be used for inputting a first supply voltage, and the second supply voltage input Vss1 may be used for inputting a second supply voltage, and optionally, the first supply voltage may be equal to the second voltage signal, and the second supply voltage may be equal to the first voltage signal. The data writing module 110 may be turned on or off under the control of a first Scan signal input by the first Scan signal input terminal Scan1, when the data writing module 110 is turned on, a data voltage is transmitted to thestorage module 120 through the data writing module 110, thestorage module 120 stores the data voltage, thevoltage selection module 130 selects the turn-on of the first transmission gate 131 and the second transmission gate 132 according to the data voltage stored in thestorage module 120, and further controls the voltage transmitted to thelight emitting module 140, thereby implementing the control of the brightness of thelight emitting module 140.

Referring to fig. 1, thevoltage selection module 130 includes aninverter 133, when an input signal at an input terminal of theinverter 133 is a first voltage signal, an output terminal of theinverter 133 outputs a second voltage signal, that is, the first voltage signal and the second voltage signal are inverted, at this time, the first transmission gate 131 is turned on according to the first voltage signal at the first control terminal G1 and the second voltage signal at the second control terminal G2, the second transmission gate 132 is turned off according to the first voltage signal at the third control terminal G3 and the second voltage signal at the fourth control terminal G4, so that the first power voltage input at the first power voltage input terminal Vdd1 is transmitted to thelight emitting module 140 through the first transmission gate 131, and thelight emitting module 140 is turned on. When the input signal of the input terminal of theinverter 133 is the second voltage signal, the output terminal of theinverter 133 outputs the first voltage signal, at this time, the first transmission gate 131 may be turned off according to the second voltage signal of the first control terminal G1 and the first voltage signal of the second control terminal G2, the second transmission gate 132 may be turned on according to the second voltage signal of the third control terminal G3 and the first voltage signal of the fourth control terminal G4, so that the second power voltage input by the second power voltage input terminal Vss1 is transmitted to thelight emitting module 140 through the second transmission gate 132, and thelight emitting module 140 is dimmed.

With continued reference to fig. 1, optionally, the first transmission gate 131 includes a first transistor T1 and a second transistor T2, and the second transmission gate 132 includes a third transistor T3 and a fourth transistor T4, wherein the first transistor T1 is the same channel type as the fourth transistor T4, the second transistor T2 is the same channel type as the third transistor T3, and the first transistor T1 is different channel type from the second transistor T2.

A gate of the first transistor T1 serves as a first control terminal G1, a gate of the second transistor T2 serves as a second control terminal G2, a first pole of the first transistor T1 and a first pole of the second transistor T2 are both electrically connected to the first power supply voltage input terminal Vdd1, and a second pole of the first transistor T1 and a second pole of the second transistor T2 are both electrically connected to the first output terminal.

A gate of the third transistor T3 is used as the third control terminal G3, a gate of the fourth transistor T4 is used as the fourth control terminal G4, a first pole of the third transistor T3 and a first pole of the fourth transistor T4 are electrically connected to the second power supply voltage input terminal Vss1, and a second pole of the third transistor T3 and a second pole of the fourth transistor T4 are electrically connected to the second output terminal.

Optionally, the first transistor T1 and the fourth transistor T4 are P-type transistors, and the second transistor T2 and the third transistor T3 are N-type transistors; of course, the first transistor T1 and the fourth transistor T4 may also be N-type transistors, and the second transistor T2 and the third transistor T3 are P-type transistors at this time, which is not limited in this embodiment. The following embodiments are described by taking as examples that the first transistor T1 and the fourth transistor T4 are P-type transistors, and the second transistor T2 and the third transistor T3 are N-type transistors.

When the data voltage written into thememory module 120 by the data writing module 110 is a first voltage signal, thememory module 120 stores the first voltage signal, the input terminal of theinverter 133 inputs the first voltage signal, and accordingly, the output terminal of theinverter 133 outputs a second voltage signal, and when the first transistor T1 and the fourth transistor T4 are P-type transistors and the second transistor T2 and the third transistor T3 are N-type transistors, the first voltage signal may be a low level signal and the second voltage signal may be a high level signal. The first transistor T1 is turned on according to the first voltage signal of the gate thereof, the second transistor T2 is turned on according to the second voltage signal of the gate thereof, that is, the first transmission gate 131 is turned on, and the first power voltage is transmitted to thelight emitting module 140 through the turned-on first transmission gate 131, so that thelight emitting module 140 is turned on. And the third transistor T3 is turned off according to the first voltage signal of its gate, and the fourth transistor T4 is turned off according to the second voltage signal of its gate, i.e., the second transmission gate 132 is turned off.

When the data voltage written into thememory module 120 by the data writing module 110 is a second voltage signal, thememory module 120 stores the second voltage signal, the second voltage signal is input to the input terminal of theinverter 133, and correspondingly, the first voltage signal is output from the output terminal of theinverter 133. The first transistor T1 is turned off according to the second voltage signal at the gate thereof, the second transistor T2 is turned off according to the first voltage signal at the gate thereof, that is, the first transmission gate 131 is turned off, and the first power voltage cannot be transmitted to thelight emitting module 140. And the third transistor T3 is turned on according to the second voltage signal of the gate thereof, the fourth transistor T4 is turned on according to the first voltage signal of the gate thereof, that is, the second transmission gate 132 is turned on, and the second power voltage is transmitted to thelight emitting module 140 through the turned-on second transmission gate 132, so that thelight emitting module 140 is turned off.

In this embodiment, the first transmission gate 131 and the second transmission gate 132 are arranged to include two transistors connected in parallel, and the two transistors are different in type, so that the transistor characteristics in the first transmission gate 131 and the second transmission gate 132 are complementary, the on-resistance is reduced, and then the first power supply voltage and the second power supply voltage are selected quickly, and further on the basis of quickly controlling the brightness state of the light emitting module, the number of transistors in the pixel circuit can be reduced, and further, the pixel density can be improved.

Fig. 2 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention, the pixel circuit further includes areset module 150, and thereset module 150 is configured to provide a second voltage signal to the input terminal of theinverter 133 at least in an initial stage of a frame, so as to turn on the second transmission gate 132.

Thereset module 150 is further configured to reset thestorage module 120 at least during an initial period of a frame.

Specifically, the present embodiment may be a digital driving pixel circuit or an analog driving pixel circuit, wherein when the pixel circuit is an analog driving pixel circuit, the initial stage in one frame is a stage before the data writing stage in one frame; when the pixel circuit is a digital driving pixel circuit, the initial stage in a frame is a stage before the data writing stage of the first subframe in a frame.

Thereset module 150 provides the second voltage signal to the input terminal of theinverter 133 at least at an initial stage in one frame, so that at least at the initial stage in one frame, the second transmission gate 132 is turned on according to the second voltage signal, and the first transmission gate 131 is turned off according to the second voltage signal, so that at least at the initial stage in one frame, the second power voltage can be transmitted to thelight emitting module 140 through the second transmission gate 132, thereby removing the residual charge of the last frame of thelight emitting module 140, avoiding the influence of the display of the last frame on the current frame, and ensuring a better display effect. In addition, thereset module 150 also resets thestorage module 120 at least at an initial stage within one frame, so that the data voltage stored in thestorage module 120 can be cleared, thereby further avoiding the influence of the previous frame display on the current frame and further ensuring a good display effect.

With continued reference to fig. 2, optionally, one frame includes at least two subframes, and thereset module 150 is configured to provide the second voltage signal to the input terminal of theinverter 133 to turn on the second transmission gate 132 at an initial stage in each subframe; thereset module 150 is also used to reset thestorage module 120 at an initial stage within each subframe.

Specifically, the pixel circuit of this embodiment may be a digital driving pixel circuit, and when the digital driving pixel circuit is driven, one frame is usually divided into at least two subframes, the time lengths corresponding to the different subframes are different, the light emitting time of thelight emitting module 140 in one frame is controlled by controlling the brightness of thelight emitting module 140 in each subframe, and the display gray scale of thelight emitting module 140 is controlled by controlling the light emitting time of thelight emitting module 140 in one frame. The initial phase of each subframe may be performed before the data writing phase of each subframe. Thereset module 150 provides the second voltage signal to the input terminal of theinverter 133 at the initial stage in each subframe, so that the second transmission gate 132 is turned on according to the second voltage signal and the first transmission gate 131 is turned off according to the second voltage signal at the initial stage in each subframe, and further, at the initial stage in each subframe, the second power voltage can be transmitted to thelight emitting module 140 through the second transmission gate 132, so as to clear the residual charge of a subframe on thelight emitting module 140. Thereset module 150 also resets thememory module 120 at an initial stage in each subframe, so that the data voltage stored in thememory module 120 can be cleared.

With continued reference to fig. 2, optionally, the control terminal of theRESET module 150 is electrically connected to a RESET control signal terminal RESET, the first terminal of theRESET module 150 is configured to receive the second voltage signal, and the second terminal of theRESET module 150 is electrically connected to the input terminal of theinverter 133.

Optionally, the second voltage signal is provided by the first supply voltage input Vdd 1.

Fig. 3 is a driving timing diagram of a pixel circuit according to an embodiment of the invention, where the driving timing may be used to drive the pixel circuit shown in fig. 2, and referring to fig. 2 and fig. 3, when the pixel circuit is an analog driving pixel circuit, the driving timing shown in fig. 3 may correspond to a driving timing of one frame, and an operation process of the pixel circuit in one frame includes an initial stage t1, a data writing stage t2, and a light emitting stage t 3. The description will be given taking an example in which the RESET control signal input from the RESET control signal terminal RESET is active low, the first voltage signal is a low-level signal, and the second voltage signal is a high-level signal.

At the initial stage T1, the RESET control signal terminal RESET inputs a low level signal, theRESET module 150 is turned on, the second voltage signal is transmitted to the input terminal of theinverter 133, the first voltage signal is input to the output terminal of theinverter 133, the third transistor T3 is turned on according to the second voltage signal of the gate, and the fourth transistor T4 is turned on according to the first voltage signal of the gate, the second power voltage is transmitted to thelight emitting module 140, so that thelight emitting module 140 is RESET.

In the Data writing phase t2, the first Scan signal input terminal Scan1 inputs a low level signal (a first voltage signal), the Data voltage input from the Data voltage input terminal Data is transmitted to thememory module 120 through the turned-on Data writing module 110, and thevoltage selection module 130 turns on the first transmission gate 131 according to the first voltage signal stored in thememory module 120, so as to transmit the first power voltage to thelight emitting module 140.

In the lighting period t3, thelighting module 140 is lit.

Fig. 4 is another driving timing diagram of a pixel circuit according to an embodiment of the present invention, where the driving timing diagram is used to drive the pixel circuit shown in fig. 2, the driving timing diagram is a digital driving manner, the driving timing diagram is a driving timing diagram for driving the pixel circuit by using a subframe method, fig. 4 schematically illustrates a case where oneframe 1H is divided into 8 subframes, which are respectively a first subframe F1, a second subframe F2, a third subframe F3, a fourth subframe F4, a fifth subframe F5, a sixth subframe F6, a seventh subframe F7, and an eighth subframe F8, and optionally, the time lengths corresponding to the 8 subframes are different. The working process of each subframe may include a first phase t0 and a second phase t3, wherein the first phase t0 may include an initial phase t1 and a data writing phase t2, and the second phase t3 is a light emitting phase. At this time, the driving timing shown in fig. 3 may correspond to the driving timing of any subframe in fig. 4, and the working process of each working phase has been analyzed in the foregoing embodiment, which is not described herein again.

Fig. 5 is a schematic structural diagram of another pixel circuit provided in an embodiment of the present invention, and referring to fig. 5, optionally, thestorage module 120 includes a latch, an input terminal of the latch is electrically connected to the data writing module 110, and an output terminal of the latch is electrically connected to thevoltage selection module 130.

The latch includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8, a gate of the fifth transistor T5 is electrically connected to a gate of the sixth transistor T6, a first pole of the fifth transistor T5 is electrically connected to the third power supply voltage input terminal Vdd2, a second pole of the fifth transistor T5 is electrically connected to a first pole of the sixth transistor T6, and a second pole of the sixth transistor T6 is electrically connected to the fourth power supply voltage input terminal Vss 2.

A gate of the seventh transistor T7 is electrically connected to a gate of the eighth transistor T8, a first pole of the seventh transistor T7 is electrically connected to the third power supply voltage input terminal Vdd2, a second pole of the seventh transistor T7 is electrically connected to the first pole of the eighth transistor T8, and a second pole of the eighth transistor T8 is electrically connected to the fourth power supply voltage input terminal Vss 2.

A common terminal of the gate of the fifth transistor T5 and the gate of the sixth transistor T6 is electrically connected to the second pole of the seventh transistor T7, and the gate of the fifth transistor T5 and the gate of the sixth transistor T6 serve as input terminals of the latch.

A common terminal of the gate of the seventh transistor T7 and the gate of the eighth transistor T8 is electrically connected to the second pole of the fifth transistor T5; the second pole of the fifth transistor T5 and the first pole of the sixth transistor T6 serve as output terminals of the latch.

The channel types of the fifth transistor T5 and the seventh transistor T7 are the same, the channel types of the sixth transistor T6 and the eighth transistor T8 are the same, and the channel types of the fifth transistor T5 and the sixth transistor T6 are different.

Optionally, the fifth transistor T5 and the seventh transistor T7 are P-type transistors, and the sixth transistor T6 and the eighth transistor T8 are N-type transistors; of course, in other embodiments, the fifth transistor T5 and the seventh transistor T7 may be N-type transistors, and the sixth transistor T6 and the eighth transistor T8 may be N-type transistors, which is not limited in this embodiment.

In the pixel circuit provided by this embodiment, thestorage module 120 is configured as a latch structure, and because the latch structure has a power supply (electrically connected to the third power voltage input terminal Vdd2 and the fourth power voltage input terminal Vss2, respectively), compared to a pixel circuit in which a capacitor is used as thestorage module 120 in the prior art, the data voltage can be better maintained, and because thevoltage selection module 130 needs to control the first transmission gate 131 or the second transmission gate 132 to be turned on according to the data voltage, the stable maintenance of the data voltage can enable the first transmission gate 131 and the second transmission gate 132 in thevoltage selection module 130 to be turned on or off accurately, so as to accurately control the turn-on and turn-off of thelight emitting module 140, thereby ensuring a good display effect.

When thememory module 120 is in the latch structure, when thereset module 150 resets thememory module 120, the second voltage signal is transmitted to the gates of the seventh transistor T7 and the eighth transistor T8, the eighth transistor T8 is turned on, and the voltage signal of the fourth power voltage input terminal Vss2 is transmitted to the gates of the fifth transistor T5 and the sixth transistor T6, so that the latch is reset.

Optionally, the third power voltage input terminal Vdd2 and the first power voltage input terminal Vdd1 are the same input terminal, so that the number of power supplies for the pixel circuit can be reduced, which is beneficial to saving cost, and the power supplies are usually disposed in a non-display area of the display panel, thereby being beneficial to realizing a narrow bezel.

Optionally, the fourth power voltage input terminal Vss2 and the second power voltage input terminal Vss1 are the same input terminal, so that the number of power supplies for providing power to the pixel circuit can be reduced, which is beneficial to saving cost, and the power supplies are usually disposed in a non-display area of the display panel, thereby being beneficial to realizing a narrow frame.

Referring to fig. 1, fig. 2 and fig. 5, on the basis of the above embodiments, optionally, the first transmission gate 131 and the second transmission gate 132 are both electrically connected to the first end of thelight emitting module 140, and the second end of thelight emitting module 140 is electrically connected to the fifth power supply voltage input terminal Vss 3.

Optionally, thelight emitting module 140 may be an Organic Light Emitting Device (OLED), an inorganic light emitting device (e.g., Micro-LED), and the like, and this embodiment is not limited in detail herein. Hereinafter, the organic light emitting device and the inorganic light emitting device may be collectively referred to as a light emitting device D1, wherein a first end of thelight emitting module 140 may be an anode of the light emitting device D1 and a second end of thelight emitting module 140 may be a cathode of the light emitting device D1.

The difference between the input first power voltage at the first power voltage input terminal Vdd1 and the input voltage at the fifth power voltage input terminal Vss3 may be greater than the voltage across the light emitting device D1, so that the light emitting device D1 may light up after the first power voltage is transmitted to the anode of the light emitting device D1. A difference between the input second power voltage of the second power voltage input terminal Vss1 and the input voltage of the fifth power voltage input terminal Vss3 may be less than a voltage across the light emitting device D1, so that the light emitting device D1 may be turned off after the second power voltage is transmitted to the anode of the light emitting device D1.

Optionally, the fifth power voltage input terminal Vss3 and the second power voltage input terminal Vss1 are the same input terminal, so that the number of power supplies for providing power to the pixel circuit can be reduced, which is beneficial to saving cost, and the power supplies are usually disposed in a non-display area of the display panel, thereby being beneficial to realizing a narrow bezel.

With continued reference to fig. 5, optionally, the Data writing module 110 includes a ninth transistor T9 for transmitting the Data voltage at the Data voltage input terminal Data to thememory module 120 under the control of the first scan signal inputted to the gate of the ninth transistor T9.

Fig. 6 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention, and referring to fig. 6, optionally, the data writing module 110 further includes a tenth transistor T10, the tenth transistor T10 is connected in parallel with the ninth transistor T9, and the channel types of the tenth transistor T10 and the ninth transistor T9 are opposite; the gate of the tenth transistor T10 is for receiving the second scan signal, which is opposite in level to the first scan signal.

Specifically, the gate of the ninth transistor T9 may be electrically connected to the first Scan signal input terminal Scan1, the gate of the tenth transistor T10 may be electrically connected to the second Scan signal input terminal Scan2, and the ninth transistor T9 and the tenth transistor T10 may form a transmission gate structure, thereby reducing on-resistance with respect to a single transistor; and the ninth transistor T9 and the tenth transistor T10 have different channel types and complementary characteristics, so that compared with a single transistor, the on/off speed is increased, and thus the Data voltage can be rapidly transmitted to thememory module 120, and the Data voltage input terminal Data and thememory module 120 can be rapidly cut off, thereby facilitating the improvement of the display effect.

Fig. 7 is a schematic structural diagram of a display panel according to an embodiment of the present invention, and the display panel 10 includes thepixel circuit 100 according to any embodiment of the present invention.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims (10)

Translated fromChinese

1.一种像素电路，其特征在于，包括数据写入模块、存储模块、电压选择模块和发光模块；1. A pixel circuit, characterized in that, comprising a data writing module, a storage module, a voltage selection module and a light-emitting module;所述数据写入模块用于将数据电压写入到所述存储模块，所述存储模块用于存储所述数据电压；The data writing module is used for writing the data voltage into the storage module, and the storage module is used for storing the data voltage;所述电压选择模块与所述存储模块电连接，所述电压选择模块包括第一传输门和第二传输门，所述第一传输门和所述第二传输门均包括至少两个并联的不同沟道类型的晶体管，所述电压选择模块用于根据所述存储模块存储数据电压控制所述第一传输门和所述第二传输门的导通状态，并在所述第一传输门导通时，将第一电源电压传输至发光模块以使所述发光模块点亮，以及在所述第二传输门导通时，将第二电源电压传输至所述发光模块以使所述发光模块关断。The voltage selection module is electrically connected to the storage module, the voltage selection module includes a first transmission gate and a second transmission gate, and both the first transmission gate and the second transmission gate include at least two different a channel type transistor, the voltage selection module is configured to control the conduction states of the first transmission gate and the second transmission gate according to the stored data voltage of the storage module, and conduct the first transmission gate When the first power supply voltage is transmitted to the light-emitting module to turn on the light-emitting module, and when the second transmission gate is turned on, the second power supply voltage is transmitted to the light-emitting module to turn the light-emitting module off. break.2.根据权利要求1所述的像素电路，其特征在于，所述第一传输门包括第一控制端、第二控制端、第一输入端和第一输出端，所述第二传输门包括第三控制端、第四控制端、第二输入端和第二输出端；所述第一输入端与第一电源电压输入端电连接，所述第二输入端与第二电源电压输入端电连接；2. The pixel circuit according to claim 1, wherein the first transmission gate comprises a first control terminal, a second control terminal, a first input terminal and a first output terminal, and the second transmission gate comprises a third control terminal, a fourth control terminal, a second input terminal and a second output terminal; the first input terminal is electrically connected to the first power supply voltage input terminal, and the second input terminal is electrically connected to the second power supply voltage input terminal connect;所述电压选择模块还包括反相器，所述反相器的输入端与存储模块电连接，所述反相器的输入端还分别与所述第一控制端和第三控制端电连接，所述反相器的输出端分别与所述第二控制端和第四控制端电连接；所述第一传输门的第一输出端和所述第二传输门的第二输出端均与所述发光模块电连接；The voltage selection module further includes an inverter, the input terminal of the inverter is electrically connected to the storage module, and the input terminal of the inverter is also electrically connected to the first control terminal and the third control terminal, respectively, The output end of the inverter is respectively electrically connected with the second control end and the fourth control end; the first output end of the first transmission gate and the second output end of the second transmission gate are both connected to the second control end and the fourth control end; the light-emitting module is electrically connected;所述第一传输门用于在所述反相器的输入端的输入信号为第一电压信号时，根据所述第一控制端和所述第二控制端的信号导通；所述第二传输门用于在所述反相器的输入端的输入信号为第二电压信号时，根据所述第三控制端和所述第四控制端的信号导通。The first transmission gate is used for conducting conduction according to the signals of the first control terminal and the second control terminal when the input signal of the input terminal of the inverter is a first voltage signal; the second transmission gate When the input signal of the input end of the inverter is the second voltage signal, the signal is turned on according to the signals of the third control end and the fourth control end.3.根据权利要求2所述的像素电路，其特征在于，所述第一传输门包括第一晶体管和第二晶体管，所述第二传输门包括第三晶体管和第四晶体管，其中所述第一晶体管与所述第四晶体管的沟道类型相同，所述第二晶体管和所述第三晶体管的沟道类型相同，所述第一晶体管和所述第二晶体管的沟道类型不同；3. The pixel circuit according to claim 2, wherein the first transmission gate comprises a first transistor and a second transistor, the second transmission gate comprises a third transistor and a fourth transistor, wherein the first transmission gate A transistor has the same channel type as the fourth transistor, the second transistor and the third transistor have the same channel type, and the first transistor and the second transistor have different channel types;所述第一晶体管的栅极作为所述第一控制端，所述第二晶体管的栅极作为第二控制端，所述第一晶体管的第一极和所述第二晶体管的第一极均与所述第一电源电压输入端电连接，所述第一晶体管的第二极和所述第二晶体管的第二极均与所述第一输出端电连接；The gate of the first transistor is used as the first control terminal, the gate of the second transistor is used as the second control terminal, the first electrode of the first transistor and the first electrode of the second transistor are both is electrically connected to the first power supply voltage input terminal, and both the second pole of the first transistor and the second pole of the second transistor are electrically connected to the first output terminal;所述第三晶体管的栅极作为所述第三控制端，所述第四晶体管的栅极作为第四控制端，所述第三晶体管的第一极和所述第四晶体管的第一极均与所述第二电源电压输入端电连接，所述第三晶体管的第二极和所述第四晶体管的第二极均与所述第二输出端电连接。The gate of the third transistor is used as the third control terminal, the gate of the fourth transistor is used as the fourth control terminal, the first electrode of the third transistor and the first electrode of the fourth transistor are both It is electrically connected to the second power supply voltage input terminal, and the second pole of the third transistor and the second pole of the fourth transistor are both electrically connected to the second output terminal.4.根据权利要求2所述的像素电路，其特征在于，还包括复位模块，所述复位模块用于至少在一帧内的初始阶段，向所述反相器的输入端提供第二电压信号，以使所述第二传输门导通；4 . The pixel circuit according to claim 2 , further comprising a reset module, wherein the reset module is configured to provide a second voltage signal to the input terminal of the inverter at least at an initial stage within a frame. 5 . , so that the second transmission gate is turned on;所述复位模块还用于至少在一帧内的初始阶段，对所述存储模块进行复位。The reset module is further configured to reset the storage module at least in an initial stage within a frame.5.根据权利要求4所述的像素电路，其特征在于，所述一帧包括至少两个子帧，所述复位模块用于在每一所述子帧内的初始阶段，向所述反相器的输入端提供第二电压信号，以使所述第二传输门导通；所述复位模块还用于在每一所述子帧内的初始阶段，对所述存储模块进行复位。5 . The pixel circuit according to claim 4 , wherein the one frame includes at least two subframes, and the reset module is configured to, in an initial stage in each of the subframes, send the inverter to the inverter. 6 . The input terminal of the device provides a second voltage signal to turn on the second transmission gate; the reset module is further configured to reset the storage module at the initial stage in each of the subframes.6.根据权利要求4所述的像素电路，其特征在于，所述复位模块的控制端与复位控制信号端电连接，所述复位模块的第一端用于接入第二电压信号，所述复位模块的第二端与所述反相器的输入端电连接；6 . The pixel circuit according to claim 4 , wherein the control terminal of the reset module is electrically connected to the reset control signal terminal, the first terminal of the reset module is used for accessing the second voltage signal, and the The second end of the reset module is electrically connected to the input end of the inverter;优选的，所述第二电压信号由所述第一电源电压输入端提供。Preferably, the second voltage signal is provided by the first power supply voltage input terminal.7.根据权利要求1-6任一项所述的像素电路，其特征在于，所述存储模块包括锁存器，所述锁存器的输入端与所述数据写入模块电连接，所述锁存器的输出端与所述电压选择模块电连接；7. The pixel circuit according to any one of claims 1-6, wherein the storage module comprises a latch, and an input end of the latch is electrically connected to the data writing module, and the latch is electrically connected to the data writing module. The output end of the latch is electrically connected with the voltage selection module;所述锁存器包括第五晶体管、第六晶体管、第七晶体管和第八晶体管，所述第五晶体管的栅极与所述第六晶体管的栅极电连接，所述第五晶体管的第一极与第三电源电压输入端电连接，所述第五晶体管的第二极与所述第六晶体管的第一极电连接，所述第六晶体管的第二极与第四电源电压输入端电连接；The latch includes a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor, the gate of the fifth transistor is electrically connected to the gate of the sixth transistor, and the first transistor of the fifth transistor is electrically connected to the gate of the sixth transistor. The pole is electrically connected to the third power supply voltage input terminal, the second pole of the fifth transistor is electrically connected to the first pole of the sixth transistor, and the second pole of the sixth transistor is electrically connected to the fourth supply voltage input terminal connect;所述第七晶体管的栅极与所述第八晶体管的栅极电连接，所述第七晶体管的第一极与所述第三电源电压输入端电连接，所述第七晶体管的第二极与所述第八晶体管的第一极电连接，所述第八晶体管的第二极与所述第四电源电压输入端电连接；The gate of the seventh transistor is electrically connected to the gate of the eighth transistor, the first pole of the seventh transistor is electrically connected to the third power supply voltage input terminal, and the second pole of the seventh transistor is electrically connected is electrically connected to the first pole of the eighth transistor, and the second pole of the eighth transistor is electrically connected to the fourth power supply voltage input terminal;所述第五晶体管的栅极和所述第六晶体管的栅极的公共端与所述第七晶体管的第二极电连接，且所述第五晶体管的栅极和所述第六晶体管的栅极作为所述锁存器的输入端；The common terminal of the gate of the fifth transistor and the gate of the sixth transistor is electrically connected to the second electrode of the seventh transistor, and the gate of the fifth transistor and the gate of the sixth transistor are pole as the input of the latch;所述第七晶体管的栅极和所述第八晶体管的栅极的公共端与所述第五晶体管的第二极电连接；所述第五晶体管的第二极与所述第六晶体管的第一极作为所述锁存器的输出端；The common terminal of the gate of the seventh transistor and the gate of the eighth transistor is electrically connected to the second pole of the fifth transistor; the second pole of the fifth transistor is connected to the second pole of the sixth transistor. One pole is used as the output terminal of the latch;所述第五晶体管和所述第七晶体管的沟道类型相同，所述第六晶体管和所述第八晶体管的沟道类型相同，所述第五晶体管和所述第六晶体管的沟道类型不同；The fifth transistor and the seventh transistor have the same channel type, the sixth transistor and the eighth transistor have the same channel type, and the fifth transistor and the sixth transistor have different channel types ;优选的，所述第三电源电压输入端和所述第一电源电压输入端为同一输入端；Preferably, the third power supply voltage input terminal and the first power supply voltage input terminal are the same input terminal;优选的，所述第四电源电压输入端和所述第二电源电压输入端为同一输入端。Preferably, the fourth power supply voltage input terminal and the second power supply voltage input terminal are the same input terminal.8.根据权利要求1-6任一项所述的像素电路，其特征在于，所述第一传输门和所述第二传输门均与所述发光模块的第一端电连接，所述发光模块的第二端与第五电源电压输入端电连接；优选的，所述第五电源电压输入端和所述第二电源电压输入端为同一输入端。8. The pixel circuit according to any one of claims 1-6, wherein the first transmission gate and the second transmission gate are both electrically connected to the first end of the light-emitting module, and the light-emitting The second terminal of the module is electrically connected to the fifth power supply voltage input terminal; preferably, the fifth power supply voltage input terminal and the second power supply voltage input terminal are the same input terminal.9.根据权利要求1-6任一项所述的像素电路，其特征在于，所述数据写入模块包括第九晶体管，用于在所述第九晶体管栅极接入的第一扫描信号的控制下，将数据电压输入端的数据电压传输至所述存储模块；9 . The pixel circuit according to claim 1 , wherein the data writing module comprises a ninth transistor, which is used for the output of the first scan signal connected to the gate of the ninth transistor. 10 . Under control, the data voltage of the data voltage input terminal is transmitted to the storage module;优选的，所述数据写入模块还包括第十晶体管，所述第十晶体管和所述第九晶体管并联连接，且所述第十晶体管与所述第九晶体管的沟道类型相反；所述第十晶体管的栅极用于接入第二扫描信号，所述第二扫描信号和所述第一扫描信号的电平相反。Preferably, the data writing module further comprises a tenth transistor, the tenth transistor and the ninth transistor are connected in parallel, and the channel type of the tenth transistor and the ninth transistor is opposite; The gates of the ten transistors are used to access a second scan signal, and the second scan signal and the first scan signal have opposite levels.10.一种显示面板，其特征在于，包括权利要求1-9任一项所述的像素电路。10. A display panel, comprising the pixel circuit according to any one of claims 1-9.

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