[ Invention ]
The embodiment of the application provides an interrupt balancing method, an interrupt balancing device, electronic equipment and a computer readable storage medium, which eliminate the influence of interrupt statistical information lag on interrupt balancing and realize the real-time performance of interrupt balancing by taking a predicted load of an interrupt in one period in the future as the basis of interrupt balancing.
In a first aspect, an embodiment of the present application provides an interrupt balancing method, applied to an electronic device that adopts a multi-core processor, where the multi-core processor includes at least 2 online cores, the method includes:
Determining a first online core and a second online core with unbalanced interrupt load, wherein the first online core is an online core to be moved out of an interrupt, and the second online core is an online core to be moved in the interrupt;
determining interrupt loads to be migrated according to the interrupt loads of the first online core and the second online core;
calculating predicted loads of all interrupts on the first online core in a future period;
determining an interrupt to be removed from the first online core according to the predicted load, wherein the predicted load of the interrupt to be removed is similar to or equal to the interrupt load to be migrated;
And migrating the interrupt to be removed to the second online core.
In the interrupt balancing method, the predicted load of each interrupt on the first online core in one future period is calculated and used as the basis for determining the interrupt to be migrated, so that the influence caused by information hysteresis in interrupt balancing is eliminated, and the real-time performance of interrupt balancing is improved.
In one possible implementation, determining that there is an interrupt load imbalance of the first and second online cores includes:
counting the interrupt load of each online core in the past period;
a first online core and a second online core with a difference value of interrupt loads are selected.
In one possible implementation manner, the determining that there is an interrupt load imbalance of the first online core and the second online core further includes:
And calculating the ratio of the interrupt load of the second online core to the interrupt load of the first online core, and if the ratio is smaller than a preset balance threshold, obtaining the first online core and the second online core with unbalanced load.
In one possible implementation manner, the determining the interrupt load to be migrated according to the interrupt loads of the first online core and the second online core includes:
by the formulaCalculating an interrupt load to be migrated, wherein Ld is the interrupt load to be migrated, irqloadmax is the interrupt load of the first online core, and irqloadmin is the interrupt load of the second online core.
In one possible implementation, the calculating the predicted load of each interrupt on the first online core in a future period includes:
Based on the periodically recorded triggering times of each interrupt on the first online core, calculating the predicted triggering times of each interrupt in one future period through an EMA algorithm;
for each interrupt on the first on-line core, passing through a formulaCalculating the predicted load of the first online core in the future, wherein Lp is the predicted load of the interrupt, EMA (Xn) is the predicted trigger times of the interrupt in the future in one period, Xall is the trigger times of all the interrupts on the first online core in the past one period, deltat is the time of one period, and Lall is the interrupt load of the first online core in the past one period.
In one possible implementation, the method is applied to a performance mode that interrupts equalization.
In one possible implementation, the method further includes calculating interrupt load data, comparing the interrupt load data to a preset first threshold, entering a performance mode of the interrupt balancing when the interrupt load data is greater than the preset first threshold, wherein the interrupt load data characterizes a ratio of an interrupt load to a total load processed by the multi-core processor.
In one possible implementation, when in a power saving mode of interrupt balancing, the method includes:
determining a third online core, wherein the third online core is an online core to be moved into an interrupt;
And migrating all interrupts on the online cores except the third online core to the third online core.
In one possible implementation, the determining the third online core includes:
counting the interrupt load of each online core in the past period;
and selecting a third online core with the maximum interrupt load.
In one possible implementation, the interrupt load data is less than a preset second threshold, and the power saving mode of interrupt balancing is entered.
In a second aspect, an embodiment of the present application further provides an interrupt balancing apparatus, applied to an electronic device adopting a multi-core processor, where the multi-core processor includes at least 2 online cores, where the apparatus includes:
The first determining module is used for determining a first online core and a second online core with unbalanced interrupt load, wherein the first online core is an online core to be moved out of an interrupt, and the second online core is an online core to be moved in the interrupt;
The load determining module is used for determining interrupt loads to be migrated according to the interrupt loads of the first online core and the second online core;
The load prediction module is used for calculating the predicted load of each interrupt on the first online core in one future period;
The interrupt determining module is used for determining an interrupt to be removed from the first online core according to the predicted load, and the predicted load of the interrupt to be removed is similar to or equal to the interrupt load to be migrated;
and the first migration module is used for migrating the interrupt to be removed to the second online core.
In one possible implementation manner, the first determining module includes:
a first statistics sub-module for counting interrupt load of each online core in a past period;
the first selecting sub-module is used for selecting a first online core and a second online core with a difference value of interrupt loads.
In one possible implementation manner, the first determining module further includes:
The first judging sub-module is used for calculating the ratio of the interrupt load of the second online core to the interrupt load of the first online core, and if the ratio is smaller than a preset balance threshold, the first online core and the second online core with unbalanced load are obtained.
In a possible implementation manner, the load determining module is further configured to determine, by a formulaCalculating an interrupt load to be migrated, wherein Ld is the interrupt load to be migrated, irqloadmax is the interrupt load of the first online core, and irqloadmin is the interrupt load of the second online core.
In one possible implementation, the load prediction module includes:
The triggering prediction sub-module is used for calculating the predicted triggering times of each interrupt in one future period through an EMA algorithm based on the periodically recorded triggering times of each interrupt on the first online core;
A load prediction sub-module for passing a formula for each interrupt on the first on-line coreCalculating the predicted load of the first online core in the future, wherein Lp is the predicted load of the interrupt, EMAN(xn) is the predicted trigger times of the interrupt in the future in one period, Xall is the trigger times of all interrupts on the first online core in the past one period, deltat is the time of one period, and Lall is the interrupt load of the first online core in the past one period.
In one possible implementation, the apparatus is applied to a performance mode that interrupts equalization.
In one possible implementation manner, the device further comprises a performance mode module, wherein the performance mode module is used for calculating interrupt load data, comparing the interrupt load data with a preset first threshold value, entering a performance mode of interrupt balancing when the interrupt load data is larger than the preset first threshold value, and the interrupt load data represents the ratio of the interrupt load processed by the multi-core processor to the total load.
In one possible implementation, when in a power saving mode of interrupt balancing, the apparatus includes:
The second determining module is used for determining a third online core, wherein the third online core is an online core to be moved into the interrupt;
And the second migration module is used for migrating all interrupts on the online cores except the third online core to the third online core.
In one possible implementation manner, the second determining module includes:
the second statistics sub-module is used for counting the interrupt load of each online core in the past period;
And the second selecting sub-module is used for selecting a third online core with the largest interrupt load.
In one possible implementation, the interrupt load data is less than a preset second threshold, and the power saving mode of interrupt balancing is entered.
In a third aspect, an embodiment of the present application provides an electronic device, including at least one multi-core processor, and at least one memory communicatively coupled to the multi-core processor, wherein:
the memory stores program instructions executable by the multi-core processor, and the multi-core processor invokes the program instructions to perform the interrupt balancing method provided in the first aspect.
The embodiment of the application also provides electronic equipment, which comprises at least one multi-core processor, wherein the multi-core processor is integrated with a memory, and the memory comprises:
the memory stores program instructions executable by the multi-core processor, and the multi-core processor invokes the program instructions to perform the interrupt balancing method provided in the first aspect.
In a fourth aspect, embodiments of the present application also provide a computer-readable storage medium storing computer instructions that cause the computer to perform the interrupt balancing method provided in the first aspect.
It should be understood that, the second to fourth aspects of the embodiment of the present invention are consistent with the technical solutions of the first aspect of the embodiment of the present invention, and the beneficial effects obtained by each aspect and the corresponding possible implementation manner are similar, and are not repeated.
[ Detailed description ] of the invention
For a better understanding of the technical solutions of the present specification, the following detailed description of the embodiments of the present application refers to the accompanying drawings.
It should be understood that the described embodiments are only some, but not all, of the embodiments of the present description. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present disclosure.
The terminology used in the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the description. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
Some interrupt balancing solutions exist in the prior art, such as irqbalance of open sources, but suffer from the disadvantage that there is hysteresis in the statistics of the interrupt load of irqbalance of open sources in terms of algorithm policy.
Based on the above problems, embodiments of the present application provide an interrupt balancing method, an interrupt balancing apparatus, an electronic device, and a computer-readable storage medium, to solve the above problems.
Fig. 1 is a schematic flow chart of an interrupt balancing method provided by an embodiment of the present application, which is applied to an electronic device adopting a multi-core processor, wherein the multi-core processor includes at least 2 online cores. As shown in fig. 1, the interrupt balancing method may include:
Step 101, determining a first online core and a second online core with unbalanced interrupt load, wherein the first online core is an online core to be moved out of an interrupt, and the second online core is an online core to be moved in the interrupt;
102, determining interrupt loads to be migrated according to the interrupt loads of the first online core and the second online core;
Step 103, calculating the predicted load of each interrupt on the first online core in a future period;
104, determining an interrupt to be removed from the first online core according to the predicted load, wherein the predicted load of the interrupt to be removed is similar to or equal to the interrupt load to be migrated;
and step 105, migrating the interrupt to be removed to the second online core.
It should be noted that, in this embodiment, the interrupt for balancing may be an SPI shared peripheral interrupt, and the SPI may respond on any processor core. The electronic devices mentioned in this embodiment may include, but are not limited to, PCs, cell phones, smart watches, base stations, VR devices, etc. The multi-core processor adopted in the embodiment may be an ARM or ARM64 architecture, and based on a Linux kernel, the multi-core processor includes a plurality of processor cores, and the processor cores are divided into an online core and an isolation core according to the working state of the processor cores, wherein the online core means that the core can be used by a process in a user space and can process an SPI, and the isolation core means that the core is not used by the process in the user space any more and cannot process the SPI. Therefore, the processor cores performing interrupt balancing in this embodiment are all online cores, and the isolation cores cannot participate in interrupt balancing.
For example, when interrupt balancing is performed, the interrupt balancing program may periodically read an interface file provided by Linux Kernel to obtain an on-line or isolated state of each processor Core CPU Core, so as to determine which cores are on-line cores, so as to avoid migrating an interrupt to an unsuitable Core. For example, reading interface files/systems/devices/systems/CPU/present may obtain all CPUcore available in the system, reading interface files/systems/devices/systems/CPU/core_ctl_ isolate, may obtain CPUcore Isolated isolation status, reading interface files/systems/devices/systems/CPU/Online, may obtain CPU core Online status. When only one CPU core is available in the system, no interrupt balancing is necessary, so the interrupt balancing scheme provided by the embodiment is suitable for the situation that the multi-core processor comprises at least 2 online cores.
In the interrupt balancing method, the first online core and the second online core with unbalanced interrupt loads are determined, wherein the first online core is the online core to be moved out of the interrupt, the second online core is the online core to be moved in the interrupt, the interrupt load to be moved is determined, the predicted load of each interrupt on the first online core in one period in the future is calculated, the interrupt to be moved out on the first online core is determined according to the predicted load, the method for moving the interrupt to be moved out onto the second online core takes the predicted load of the interrupt in one period in the future as the basis of interrupt balancing, the influence of interrupt statistical information lag on the interrupt balancing is eliminated, and the real-time property of interrupt balancing is realized.
In some embodiments, the method of determining that the interrupt load imbalance exists in the first online core and the second online core in step 101 may be that the determination result of other judging programs is directly received, or that the interrupt load imbalance exists in the first online core and the second online core is determined through calculation.
Fig. 2 is a flow chart of another interrupt balancing method provided in the embodiment of the present application, as shown in fig. 2, in the embodiment shown in fig. 1, step 101 may include:
step 201, counting interrupt load of each online core in the past period;
step 202, selecting a first online core and a second online core with differences in interrupt loads.
It should be noted that, the interrupt load of the online core in this embodiment may be represented by CPU cycles spent for executing the interrupt, and may be directly obtained by reading the interface file/proc/stat file provided by the Linux kernel. The CPU cycles spent by executing each interrupt at the current reading time point can be obtained by periodically reading and storing the/proc/stat files in the interface files provided by the Linux kernel, the CPU cycles spent by executing each interrupt at the last reading time point can also be obtained, for each interrupt, the CPU cycles at the current reading time point corresponding to each interrupt are subtracted by the CPU cycles at the last reading time point to obtain the interrupt load in the past period, wherein one period is the time difference between the current reading time point and the last reading time point, and the interrupt load of each online core in the past period can be obtained by calculating each interrupt by adopting the method. The above method is only one method that can be implemented to count the interrupt load of each online core in the past one period, but is not limited to only this method, and for example, other performance data may be counted as the interrupt load, and thus the method of counting the interrupt load of each online core in the past one period is not limited in this embodiment.
In addition, the method for selecting the first on-line core and the second on-line core with the difference value of the interrupt load may be a method for setting a difference value threshold, selecting two on-line cores with the difference value of the interrupt load greater than the difference value threshold according to the difference value threshold, or sorting the obtained interrupt loads, and selecting the on-line core with the largest interrupt load and the on-line core with the smallest interrupt load as the first on-line core and the second on-line core with the difference value of the interrupt load. Therefore, the method of selecting the first online core and the second online core with the difference value of the interrupt load according to the present embodiment is not limited.
Fig. 3 is a schematic flow chart of another interrupt balancing method according to an embodiment of the present application, where in the interrupt balancing method shown in fig. 3, step 101 may further include step 203.
And 203, calculating the ratio of the interrupt load of the second online core to the interrupt load of the first online core, and if the ratio is smaller than a preset balance threshold, obtaining the first online core and the second online core with unbalanced load.
The method for determining the interrupt load unbalance degree of the two online cores by calculating the ratio of the interrupt loads of the two online cores is a more scientific determination method for judging whether interrupt balancing is needed or not by comparing the interrupt load unbalance degree with a preset balancing threshold value, so that interrupt balancing on some serious imbalance conditions can be avoided, waste of equipment power consumption is caused, and the effect of interrupt balancing is not obvious. For example, the calculation method is that interrupt loads of each online core in the past period are obtained statistically, the interrupt loads are core0:40000/S, core1:26000/S, core3:24000/S, core3:10000/S, and the preset balance threshold is 0.8. According to the statistics result, the interrupt load of the core0 is maximum, the interrupt load of the core3 is minimum, the interrupt load ratio of the core3 to the core0 is calculated to be 10000/40000=0.25, and since 0.25 is smaller than 0.8, it is determined that interrupt balancing is required for the core0 and the core 3.
In some embodiments, the method of determining the interrupt load to be migrated according to the interrupt loads of the first online core and the second online core in step 102 is various, for example, a half of the interrupt load difference between the two online cores may be set as the interrupt load to be migrated, 40 percent of the interrupt load difference may be set, or 60 percent may be set as the interrupt load to be migrated, and the method of determining the interrupt load to be migrated may be set according to the requirements of the application scenario.
Illustratively, the formula may beCalculating an interrupt load to be migrated, wherein Ld is the interrupt load to be migrated, irqloadmax is the interrupt load of the first online core, and irqloadmin is the interrupt load of the second online core. And taking half of the interrupt load difference of the two online cores as the interrupt load to be migrated, so that the interrupt load balance of the two online cores after migration can be ensured. For example, the interrupt load of core1 is 40000/S, the interrupt load of core2 is 10000/S, using the formulaAnd calculating to obtain the interrupt load to be migrated as (40000-10000)/2=15000.
In some embodiments, step 103 calculates the load of each interrupt on the online core to be moved out of the interrupt not by the prediction method, but by calculating the current load according to the current data, so that the calculated load has an error after the interrupt is moved, because the load of the interrupt is changed in real time and may become larger or smaller, if the interrupt is moved according to the current load, after we wait until we move the interrupt to the online core to be moved into the interrupt, the problem that the interrupts on the two online cores after the interrupt is moved are still unbalanced due to the fact that the load of the interrupt has been increased or decreased. Thus, this embodiment employs a method of calculating the predicted load of each interrupt on the first wire core in one period in the future. There are many methods for predicting the load, for example, the predicted load may be calculated by using an average algorithm according to the number of triggers of the interrupt, or the predicted load may be calculated by using an exponential moving average EMA algorithm according to the number of triggers of the interrupt.
Fig. 4 is a schematic flow chart of an interrupt balancing method according to another embodiment of the present application, as shown in fig. 4, in the embodiment shown in fig. 1, step 103 may include:
Step 301, calculating the predicted trigger times of each interrupt in one future period through an EMA algorithm based on the periodically recorded trigger times of each interrupt on a first online core;
step 302, for each interrupt on the first on-line core, passing through the formulaCalculating the predicted load of the first online core in the future, wherein Lp is the predicted load of the interrupt, EMAN(xn) is the predicted trigger times of the interrupt in the future in one period, Xall is the trigger times of all the interrupts on the first online core in the past one period, deltat is the time of one period, and Lall is the interrupt load of the first online core in the past one period.
It should be noted that, since Linux Kernel cannot accurately obtain the actual load value of each interrupt, in this embodiment, the number of interrupt triggers in a period is used as a basis for determining the load of the interrupt. When interrupt balancing is performed, the interrupt balancing program periodically reads interface files provided by Linux Kernel, counts the interrupt types and the current total trigger times of each interrupt on each CPU core, can obtain the average increment of each CPU core per second according to the current statistical data and the last statistical data, and predicts the load value of each interrupt through an EMA algorithm.
For example, assuming that the interface file provided by Linux Kernel is read every 5 seconds, the statistics of the number of times of triggering the interrupt a on core1 for the first 4 times are currently obtained, namely, 10s,1000 times of data at time point t1, 15.1s,1510 times of data at time point t2, 20s,2245 times of data at time point t3, 25s,2745 times of data at time point t4, wherein 15.1s is a delay of data reading due to an emergency, but the delay of data reading does not affect the calculation result because of the time difference and the number of times of triggering.
Calculating the average number of triggers per second for interrupt a in period t1-t 2: x1 = (1510-1000)/(15.1-10) =100 times, and similarly, the average number of triggers per second for interrupt a in period t2-t3 may be calculated to be x2 = (2245-1510)/(20-15.1) =150 times, and the average number of triggers per second for interrupt a in period t3-t 4: x3 = (2745-2245)/(25-20) =100 times.
According to the recursive formula of the index moving average EMA algorithm: EMAN(x1)＝x1, where N represents the number of cycles, n=3, there is EMA3(x1)＝x1 =100,Then in the next cycle a interrupt predicts a trigger number of 112.5 triggers per second on core 1. The total triggering times of the interrupt are periodically obtained, the triggering times of each second of the interrupt in each period are calculated, the predicted triggering times of each interrupt are calculated by adopting an EMA algorithm based on the recorded triggering times of each second of a plurality of periods, the triggering times of the interrupt in the next period can be predicted more accurately, and a foundation is laid for accurately calculating the interrupt load.
The predicted liability in one future period can be calculated according to the predicted triggering times, and the calculation formula is thatFor example, for interrupt a on the first online core, Lp is the predicted load of interrupt a, EMAN(xn) is the predicted trigger number of interrupt a in one period in the future, Xall is the trigger number of all interrupts on the first online core in the past one period, Δt is the time of one period, and Lall is the interrupt load of the first online core in the past one period. EMAN(xn) has been obtained in the above step, Xall is obtained by summing the number of triggers of all interrupts on core1 acquired in the above step over the last period, Δt being 5 seconds, Lall being represented using CPU cycles taken to execute the interrupts, the interrupt load of the first online core over the last period can be represented as: Wherein t 'represents the time point of the second data reading, t represents the time point of the first data reading, C'hardirq、C′softirq represents the CPU cycles spent by the hard interrupt and the soft interrupt since the system start of the second data reading, Chardirq、Csoftirq represents the CPU cycles spent by the hard interrupt and the soft interrupt since the system start of the first data reading, and the CPU cycles spent by the hard interrupt and the soft interrupt can be directly obtained by reading the/proc/stat file in the interface file provided by the Linux kernel.
The predicted liabilities for interrupts a on core1 are calculated by the method described above, and the predicted load for each interrupt on core1 is calculated as such. By adopting the EMA algorithm to calculate the predicted load of each interrupt on the first online core in one period in the future, accurate basic data can be provided for interrupt balancing, and the accuracy of interrupt balancing is ensured.
In some embodiments, step 104 determines, according to the predicted load, the interrupt to be removed from the interrupts on the first line core, and selects, according to the predicted load of each interrupt on the first line core calculated in step 103, the interrupt to be removed so that the predicted load of the interrupt to be removed is equal to the interrupt load to be migrated calculated in step 102, and if the interrupt to be removed is not completely equal, then the interrupt to be removed with the closest value is selected. The interrupt to be removed may be one or more, and if one or more interrupts are selected, the sum of the predicted loads of the selected one or more interrupts needs to be equal to or close to the load of the interrupt to be removed.
In some embodiments, step 105 migrates interrupts to be migrated on the first online core to the second online core, and the affinity of these interrupts may be set by the/proc/irq/smp_ affinity node, which binds the interrupts to be migrated to the second online core.
In some embodiments, the interrupt balancing includes a performance mode, and the interrupt balancing method described above is applied to the performance mode of the interrupt balancing. The performance mode of interrupt balancing mainly transmits interrupts to a plurality of CPU cores when the total interrupt load is high, so that interrupt processing capacity and system instantaneity are improved.
In some embodiments, a first threshold is preset, and when the interrupt load data is greater than the preset first threshold, the interrupt balancing performance mode is entered, and the content of the interrupt load data may be various, for example, the interrupt number, the interrupt load ratio, and the like.
Fig. 5 is a schematic flow chart of another interrupt balancing method according to an embodiment of the present application, as shown in fig. 5, and step 101 includes step 401. Step 401, calculating interrupt load data, and comparing the interrupt load data with a preset first threshold, wherein the interrupt load data represents the ratio of the interrupt load processed by the multi-core processor to the total load. And when the interrupt load data is larger than a preset first threshold value, entering a performance mode of interrupt balancing. The ratio of the interrupt load to the total load can be adopted to show the current interrupt load accounting for the total load of the processor, if the current interrupt load exceeds a preset first threshold value, the total amount of the current interrupt load reaches a certain degree, and the current interrupt load needs to be balanced, and then a performance mode of interrupt balancing is entered.
In some embodiments, interrupt balancing includes a power saving mode. In the performance mode, interrupt balancing can improve the possibility that a CPU goes out of a Standby/Power Down state, and has a certain influence on system Power consumption, so that in the Power saving mode of interrupt balancing, interrupt is mainly concentrated to 1 or more cores for processing when interrupt load is low, and Power consumption is reduced.
Fig. 6 is a schematic flow chart of another interrupt balancing method according to an embodiment of the present application, as shown in fig. 6, before step 101, step 501 includes step 501 of calculating interrupt load data, and comparing the interrupt load data with a preset first threshold value and a preset second threshold value, where the interrupt load data characterizes a ratio of an interrupt load processed by the multi-core processor to a total load. When the interrupt load data is larger than a preset first threshold value, the interrupt balancing performance mode is entered, and when the interrupt load data is smaller than a preset second threshold value, the interrupt balancing power saving mode is entered. When in the power saving mode of interrupt balancing, the interrupt balancing method comprises the following steps:
step 601, determining a third online core, wherein the third online core is an online core to be moved into an interrupt;
and step 602, migrating all interrupts on the online cores except the third online core to the third online core.
It should be noted that the third online core may be any online core, and after the third online core is determined, all interrupts on other cores may be migrated to the third online core, so as to achieve the purpose of reducing power consumption of the device.
Illustratively, determining the third online core may include counting an interrupt load of each online core during a past period, and selecting a third online core having a largest interrupt load. It can be appreciated that the third online core may be the online core with the largest interrupt load, so that when the interrupt of other cores is migrated to the third online core, the time spent is shorter, the power consumption loss is smaller, and the method is more suitable for the embedded platform.
It can be understood that some other parameters, such as equalization on which cores, equalization time interval, etc., may be set in the interrupt equalization method according to the application scenario, and in addition, some other steps may be added in the interrupt equalization method, such as starting interrupt equalization, checking the number of currently available CPU cores, exiting interrupt equalization if only one Core is available, controlling whether interrupt equalization is running in the background, controlling whether to output logs, etc., so that the interrupt equalization method more matches the application scenario and the needs of the user.
The interrupt balancing method provided in this embodiment is illustrated below, where the preset first threshold is 0.15, the preset second threshold is 0.11, and the balancing threshold is 0.8.
Counting the CPU Cycles spent on interrupt processing on the CPU in the past period to 100000, counting the CPU Cycles spent on processing all tasks to 500000, calculating the ratio of interrupt load to total load to 100000/500000=0.2, and entering a performance mode when the ratio is larger than a preset first threshold.
(2) The interrupt load (unit: CPU cycles/S) of each Core in the past one period is counted, and the result is that Core0:40000, core1:26000, core2:24000, core3:10000, and according to the counted result, the interrupt load of Core0 is maximum, irqloadmax =40000, the interrupt load of Core3 is minimum, irqloadmin＝10000,irqloadmin/irqloadmax =0.25 and is smaller than an equilibrium threshold value 0.8, so that interrupt equilibrium is needed for Core0 and Core 3.
(3) The interrupt load to be migrated is calculated as Ld＝(irqloadmax-irqloadmin)/2=15000.
(4) The predicted load (unit: CPU cycles/S) of each SPI interrupt is calculated by traversing all interrupts on Core0, and the result is interrupt number 40, predicted load 1000, interrupt number 43, predicted load 18000, interrupt number 52, predicted load 14000, interrupt number 63, predicted load 1000, interrupt number 74, predicted load 300, interrupt number 105, predicted load 2000.
(5) Traversing all SPI interrupts on Core0, the predicted load for interrupt number 52 is found to be closest to the interrupt load to be migrated, Ld =15000. Interrupt migration decision result-interrupt number 52 on Core0 is migrated to Core3.
(6) Interrupt migration for Core0 and Core3 is accomplished by setting/proc/irq/52/smp_ affinity file nodes to bind interrupt number 52 to Core 3.
(7) For the remaining Core1 and Core2 irqloadmin/irqloadmax =24000/26000=0.923, which is greater than the equalization threshold of 0.8, the migration need not be interrupted, and the equalization is all completed.
Counting the CPU Cycles spent on interrupt processing on the CPU in the past period to 100000, counting the CPU Cycles spent on processing all tasks to 1000000, calculating the ratio of the interrupt load to the total load to 100000/1000000=0.1, which is smaller than a preset second threshold value, and entering a power saving mode.
(2) Interrupt loads (units: CPU cycles/S) for each Core during the past one cycle were counted, with results of Core0:40000, core1:30000, core2:20000, core3:10000. And according to the statistical result, the interrupt load of Core0 is maximum, and the interrupt balancing decision result is that all SPI interrupts are migrated to Core0.
(3) All SPI interrupts are bound to Core0 through setting/proc/irq/smp_ affinity file nodes, and interrupt migration is completed.
The foregoing description of the preferred embodiments is provided for the purpose of illustration only, and is not intended to limit the scope of the disclosure, since any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the disclosure are intended to be included within the scope of the disclosure.
The interrupt balancing method provided by the embodiment has the beneficial effects that 1, the power consumption sensitive equipment, such as a smart watch, can reduce standby power consumption after the interrupt balancing method is adopted. 2. After the interrupt balancing scheme is adopted by the performance sensitive equipment, such as a base station, the interrupt processing capability of the equipment can be improved, and the IO throughput is further improved. 3. Devices with both power consumption and performance requirements, such as smartphones, use of the interrupt balancing scheme may reduce power consumption at low loads and improve performance at high loads.
Fig. 7 is a schematic structural diagram of an interrupt balancing apparatus provided in an embodiment of the present application, where the interrupt balancing apparatus is provided in an electronic device, as shown in fig. 7, the interrupt balancing apparatus may include a first determining module 71, a load determining module 72, a load predicting module 73, an interrupt determining module 74 and a first migration module 75, where,
A first determining module 71, configured to determine a first online core and a second online core with unbalanced interrupt load, where the first online core is an online core to be moved out of an interrupt, and the second online core is an online core to be moved in the interrupt;
a load determining module 72, configured to determine an interrupt load to be migrated according to interrupt loads of the first online core and the second online core;
A load prediction module 73 for calculating a predicted load of each interrupt on the first online core in a future period;
An interrupt determining module 74, configured to determine, according to the predicted load, an interrupt to be removed from the first online core, where the predicted load of the interrupt to be removed is similar to or equal to the interrupt load to be migrated;
a first migration module 75, configured to migrate the interrupt to be removed to the second online core.
Wherein the first determining module 71 includes:
a first statistics sub-module for counting interrupt load of each online core in a past period;
the first selecting sub-module is used for selecting a first online core and a second online core with a difference value of interrupt loads.
Wherein the first determining module 71 further comprises:
The first judging sub-module is used for calculating the ratio of the interrupt load of the second online core to the interrupt load of the first online core, and if the ratio is smaller than a preset balance threshold, the first online core and the second online core with unbalanced load are obtained.
Wherein the load determination module 72 is further configured to determine the load of the load by the formulaCalculating an interrupt load to be migrated, wherein Ld is the interrupt load to be migrated, irqloadmax is the interrupt load of the first online core, and irqloadmin is the interrupt load of the second online core.
Wherein the load prediction module 73 includes:
The triggering prediction sub-module is used for calculating the predicted triggering times of each interrupt in one future period through an EMA algorithm based on the periodically recorded triggering times of each interrupt on the first online core;
A load prediction sub-module for passing a formula for each interrupt on the first on-line coreCalculating the predicted load of the first online core in the future, wherein Lp is the predicted load of the interrupt, EMAN(xn) is the predicted trigger times of the interrupt in the future in one period, Xall is the trigger times of all interrupts on the first online core in the past one period, deltat is the time of one period, and Lall is the interrupt load of the first online core in the past one period.
The device is applied to a performance mode of interrupt equalization.
The device further comprises a performance mode module, wherein the performance mode module is used for calculating interrupt load data, comparing the interrupt load data with a preset first threshold value, enabling the interrupt load data to be larger than the preset first threshold value, entering the performance mode of interrupt balancing, and enabling the interrupt load data to represent the ratio of the interrupt load to the total load processed by the multi-core processor.
Wherein when in a power saving mode of interrupt balancing, the apparatus comprises:
The second determining module is used for determining a third online core, wherein the third online core is an online core to be moved into the interrupt;
And the second migration module is used for migrating all interrupts on the online cores except the third online core to the third online core.
Wherein the second determining module includes:
the second statistics sub-module is used for counting the interrupt load of each online core in the past period;
And the second selecting sub-module is used for selecting a third online core with the largest interrupt load.
And entering a power saving mode of interrupt balancing, wherein the interrupt load data is smaller than a preset second threshold value.
The interrupt balancing apparatus provided in the embodiment shown in fig. 7 may be used to implement the technical solution of the method embodiment shown in fig. 1 in this specification, and the implementation principle and technical effects may be further referred to in the related description of the method embodiment.
Fig. 8 is a schematic structural diagram of an electronic device according to an embodiment of the present application, where, as shown in fig. 8, the electronic device may include at least one multi-core processor and at least one memory communicatively connected to the multi-core processor, where the memory stores program instructions executable by the multi-core processor, and the multi-core processor invokes the program instructions to execute the interrupt balancing method provided in the embodiments shown in fig. 1 to 6 of the present specification.
In some embodiments, the electronic device may include at least one multi-core processor integrated with a memory, where the memory stores program instructions executable by the multi-core processor, and the multi-core processor invokes the program instructions to perform the interrupt balancing method provided by the embodiments shown in fig. 1-6.
The electronic device may be an intelligent electronic device such as a smart phone, a tablet computer or a notebook computer, and the form of the electronic device is not limited in this embodiment.
For example, fig. 8 illustrates a schematic structural diagram of an electronic device by taking a smart phone as an example, and as shown in fig. 8, the electronic device 100 may include a multi-core processor 110, an external memory interface 120, an internal memory 121, an antenna 1, an antenna 2, a mobile communication module 130, a wireless communication module 140, a camera 150, a display 160, a key 170, and the like.
It should be understood that the illustrated structure of the embodiment of the present application does not constitute a specific limitation on the electronic device 100. In other embodiments of the application, electronic device 100 may include more or fewer components than shown, or certain components may be combined, or certain components may be split, or different arrangements of components. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.
The multi-core processor 110 includes two or more processor cores and may also include one or more processing units, for example, the multi-core processor 110 may include an application processor (application processor, AP), a modem processor, a graphics processor (graphics processing unit, GPU), an image signal processor (IMAGE SIGNAL processor, ISP), a controller, a video codec, a digital signal processor (DIGITAL SIGNAL processor, DSP), a baseband processor, and/or a neural network processor (neural-network processing unit, NPU), etc. Wherein the different processing units may be separate devices or may be integrated in one or more processors.
The controller can generate operation control signals according to the instruction operation codes and the time sequence signals to finish the control of instruction fetching and instruction execution.
Memory may also be provided in the multi-core processor 110 for storing instructions and data. In some embodiments, the memory in the multi-core processor 110 is a cache memory. The memory may hold instructions or data that has just been used or recycled by the multi-core processor 110. If the multi-core processor 110 needs to reuse the instruction or data, it may be called directly from the memory. Repeated accesses are avoided and the latency of the multi-core processor 110 is reduced, thereby improving the efficiency of the system.
The electronic device 100 includes a plurality of external devices, such as a camera 150, a display 160, and a key 170, where the plurality of external devices are respectively communicatively connected to the multi-core processor 110, each external device has its own interrupt request IRQ, and based on the IRQ, the multi-core processor 110 can distribute a corresponding request to a corresponding hardware driver, where the driver for processing the interrupt is required to run on the multi-core processor 110, so that when the interrupt occurs, the multi-core processor 110 temporarily stops the program of the current program and executes the interrupt request. When a plurality of interrupt requests are bound to a certain processor core at the same time, the limited resources on the processor core cannot meet the interrupt request that needs to be processed in a centralized manner, and the multi-core processor 110 executes programs stored in the internal memory 121 to perform various function applications and data processing, for example, execute the interrupt balancing method provided in the embodiments of fig. 1 to 6 of the present application to perform interrupt balancing on the interrupt request that needs to be processed in a centralized manner.
In some embodiments, the multi-core processor 110 may include one or more interfaces. The interfaces may include an integrated circuit (inter-INTEGRATED CIRCUIT, I2C) interface, an integrated circuit built-in audio (inter-INTEGRATED CIRCUIT SOUND, I2S) interface, a pulse code modulation (pulse code modulation, PCM) interface, a universal asynchronous receiver transmitter (universal asynchronous receiver/transmitter, UART) interface, a mobile industry processor interface (mobile industry processor interface, MIPI), a general-purpose input/output (GPIO) interface, a subscriber identity module (subscriber identity module, SIM) interface, and/or a universal serial bus (universal serial bus, USB) interface, among others.
The wireless communication function of the electronic device 100 may be implemented by the antenna 1, the antenna 2, the mobile communication module 130, the wireless communication module 140, a modem processor, a baseband processor, and the like.
The antennas 1 and 2 are used for transmitting and receiving electromagnetic wave signals. Each antenna in the electronic device 100 may be used to cover a single or multiple communication bands. Different antennas may also be multiplexed to improve the utilization of the antennas. For example, the antenna 1 may be multiplexed into a diversity antenna of a wireless local area network. In other embodiments, the antenna may be used in conjunction with a tuning switch.
The mobile communication module 130 may provide a solution for wireless communication including 2G/3G/4G/5G, etc., applied on the electronic device 100. The mobile communication module 130 may include at least one filter, switch, power amplifier, low noise amplifier (low noise amplifier, LNA), etc. The mobile communication module 130 may receive electromagnetic waves from the antenna 1, perform processes such as filtering, amplifying, and the like on the received electromagnetic waves, and transmit the processed electromagnetic waves to the modem processor for demodulation. The mobile communication module 130 can amplify the signal modulated by the modem processor, and convert the signal into electromagnetic waves through the antenna 1 to radiate. In some embodiments, at least some of the functional modules of the mobile communication module 130 may be disposed in the multi-core processor 110. In some embodiments, at least some of the functional modules of the mobile communication module 130 may be disposed in the same device as at least some of the modules of the multi-core processor 110.
The modem processor may include a modulator and a demodulator. The modulator is used for modulating the low-frequency baseband signal to be transmitted into a medium-high frequency signal. The demodulator is used for demodulating the received electromagnetic wave signal into a low-frequency baseband signal. The demodulator then transmits the demodulated low frequency baseband signal to the baseband processor for processing. The low frequency baseband signal is processed by the baseband processor and then transferred to the application processor. The application processor outputs sound signals through an audio device (not limited to the speaker 170A, the receiver 170B, etc.), or displays images or video through the display screen 160. In some embodiments, the modem processor may be a stand-alone device. In other embodiments, the modem processor may be separate from the multi-core processor 110 and disposed in the same device as the mobile communication module 130 or other functional modules.
The wireless communication module 140 may provide solutions for wireless communication including wireless local area network (wireless local area networks, WLAN) (e.g., wireless fidelity (WIRELESS FIDELITY, wi-Fi) network), bluetooth (BT), global navigation satellite system (global navigation SATELLITE SYSTEM, GNSS), frequency modulation (frequency modulation, FM), near field communication (NEAR FIELD communication, NFC), infrared (IR), etc., applied to the electronic device 100. The wireless communication module 140 may be one or more devices integrating at least one communication processing module. The wireless communication module 140 receives electromagnetic waves via the antenna 2, frequency-modulates and filters the electromagnetic wave signals, and transmits the processed signals to the multi-core processor 110. The wireless communication module 140 may also receive a signal to be transmitted from the multi-core processor 110, frequency modulate the signal, amplify the signal, and convert the signal into electromagnetic waves to radiate the electromagnetic waves through the antenna 2.
In some embodiments, antenna 1 and mobile communication module 130 of electronic device 100 are coupled, and antenna 2 and wireless communication module 140 are coupled, such that electronic device 100 may communicate with a network and other devices through wireless communication techniques. The wireless communication techniques can include the Global System for Mobile communications (global system for mobile communications, GSM), general packet radio service (GENERAL PACKET radio service, GPRS), code division multiple access (code division multiple access, CDMA), wideband code division multiple access (wideband code division multiple access, WCDMA), time division code division multiple access (time-division code division multiple access, TD-SCDMA), long term evolution (long term evolution, LTE), BT, GNSS, WLAN, NFC, FM, and/or IR techniques, among others. The GNSS may include a global satellite positioning system (global positioning system, GPS), a global navigation satellite system (global navigation SATELLITE SYSTEM, GLONASS), a beidou satellite navigation system (beidou navigation SATELLITE SYSTEM, BDS), a quasi zenith satellite system (quasi-zenith SATELLITE SYSTEM, QZSS) and/or a satellite based augmentation system (SATELLITE BASED AUGMENTATION SYSTEMS, SBAS).
The electronic device 100 implements display functions through a GPU, a display screen 160, an application processor, and the like. The GPU is a microprocessor for image processing, and is connected to the display 160 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. The multi-core processor 110 may include one or more GPUs that execute program instructions to generate or change display information.
The display screen 160 is used to display images, videos, and the like. The display screen 160 includes a display panel. The display panel may employ a Liquid Crystal Display (LCD) CRYSTAL DISPLAY, an organic light-emitting diode (OLED), an active-matrix organic LIGHT EMITTING diode (AMOLED), a flexible light-emitting diode (FLED), miniled, microLed, micro-oLed, a quantum dot LIGHT EMITTING diode (QLED), or the like. In some embodiments, the electronic device 100 may include 1 or N display screens 160, N being a positive integer greater than 1.
The electronic device 100 may implement photographing functions through an ISP, a camera 150, a video codec, a GPU, a display screen 160, an application processor, and the like.
The ISP is used to process the data fed back by the camera 150. For example, when photographing, the shutter is opened, light is transmitted to the camera photosensitive element through the lens, the optical signal is converted into an electric signal, and the camera photosensitive element transmits the electric signal to the ISP for processing and is converted into an image visible to naked eyes. ISP can also optimize the noise, brightness and skin color of the image. The ISP can also optimize parameters such as exposure, color temperature and the like of a shooting scene. In some embodiments, the ISP may be provided in the camera 150.
The camera 150 is used to capture still images or video. The object generates an optical image through the lens and projects the optical image onto the photosensitive element. The photosensitive element may be a charge coupled device (charge coupled device, CCD) or a Complementary Metal Oxide Semiconductor (CMOS) phototransistor. The photosensitive element converts the optical signal into an electrical signal, which is then transferred to the ISP to be converted into a digital image signal. The ISP outputs the digital image signal to the DSP for processing. The DSP converts the digital image signal into an image signal in a standard RGB, YUV, or the like format. In some embodiments, the electronic device 100 may include 1 or N cameras 150, N being a positive integer greater than 1.
The digital signal processor is used for processing digital signals, and can process other digital signals besides digital image signals. For example, when the electronic device 100 selects a frequency bin, the digital signal processor is used to fourier transform the frequency bin energy, or the like.
Video codecs are used to compress or decompress digital video. The electronic device 100 may support one or more video codecs. Thus, the electronic device 100 may play or record video in a variety of encoding formats, such as moving picture experts group (moving picture experts group, MPEG) 1, MPEG2, MPEG3, MPEG4, and the like.
The NPU is a neural-network (NN) computing processor, and can rapidly process input information by referencing a biological neural network structure, for example, referencing a transmission mode between human brain neurons, and can also continuously perform self-learning. Applications such as intelligent recognition of the electronic device 100, for example, image recognition, face recognition, voice recognition, text understanding, etc., can be realized through the NPU.
The external memory interface 120 may be used to connect an external memory card, such as a Micro SD card, to enable expansion of the memory capabilities of the electronic device 100. The external memory card communicates with the multi-core processor 110 through the external memory interface 120 to implement data storage functions. For example, files such as music, video, etc. are stored in an external memory card.
The internal memory 121 may be used to store computer executable program code including instructions. The internal memory 121 may include a storage program area and a storage data area. The storage program area may store an application program (such as a sound playing function, an image playing function, etc.) required for at least one function of the operating system, etc. The storage data area may store data created during use of the electronic device 100 (e.g., audio data, phonebook, etc.), and so on. In addition, the internal memory 121 may include a high-speed random access memory, and may also include a nonvolatile memory.
The keys 170 include a power on key, a volume key, etc. The keys 170 may be mechanical keys. Or may be a touch key. The electronic device 100 may receive key inputs, generating key signal inputs related to user settings and function controls of the electronic device 100.
The embodiment of the application provides a computer readable storage medium, which stores computer instructions for causing a computer to execute an interrupt balancing method provided in the embodiments shown in fig. 1 to 6 of the specification.
Any combination of one or more computer readable media may be utilized as the above-described computer readable storage media. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium include an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a Read Only Memory (ROM), an erasable programmable read only memory (erasable programmable read only memory, EPROM) or flash memory, an optical fiber, a portable compact disc read only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
The computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, either in baseband or as part of a carrier wave. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, radio Frequency (RF), etc., or any suitable combination of the foregoing.
Computer program code for carrying out operations for the present specification may be written in one or more programming languages, including an object oriented programming language such as Java, smalltalk, C ++ and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a local area network (local area network, LAN) or a wide area network (wide area network, WAN), or may be connected to an external computer (e.g., through the internet using an internet service provider).
The foregoing describes specific embodiments of the present disclosure. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
In the description of embodiments of the present invention, a description of reference to the terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present specification. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present specification, the meaning of "plurality" means at least two, for example, two, three, etc., unless explicitly defined otherwise.
Any process or method descriptions in flow diagrams or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing logical functions or steps of the process, and additional implementations are included within the scope of the preferred embodiments of the present specification in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order from that shown or discussed, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the embodiments of the present specification.
The term "if" as used herein may be interpreted as "at" or "when" depending on the context "or" in response to a determination "or" in response to a detection. Similarly, the phrase "if determined" or "if detected (stated condition or event)" may be interpreted as "when determined" or "in response to determination" or "when detected (stated condition or event)" or "in response to detection (stated condition or event), depending on the context.
It should be noted that, the terminal according to the embodiment of the present application may include, but is not limited to, a personal computer (personal computer, PC), a Personal Digital Assistant (PDA), a wireless handheld device, a tablet computer (tablet computer), a mobile phone, an MP3 player, an MP4 player, and the like.
In the several embodiments provided in this specification, it should be understood that the disclosed systems, apparatuses, and methods may be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the elements is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple elements or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
In addition, each functional unit in each embodiment of the present specification may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in hardware plus software functional units.
The integrated units implemented in the form of software functional units described above may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium, and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) to perform part of the steps of the methods described in the embodiments of the present specification. The storage medium includes a U disk, a removable hard disk, a Read Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The foregoing description of the preferred embodiments is provided for the purpose of illustration only, and is not intended to limit the scope of the disclosure, since any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the disclosure are intended to be included within the scope of the disclosure.