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CN113851383A - Fan-out substrate and method of forming the same - Google Patents

Fan-out substrate and method of forming the same
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Publication number
CN113851383A
CN113851383ACN202110925745.9ACN202110925745ACN113851383ACN 113851383 ACN113851383 ACN 113851383ACN 202110925745 ACN202110925745 ACN 202110925745ACN 113851383 ACN113851383 ACN 113851383A
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substrate
fan
adhesive layer
passive element
passive
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黄文宏
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

Translated fromChinese

本发明的实施例提供了一种扇出式基板,包括:叠置的第一基板和第二基板;粘合层,位于第一基板和第二基板之间;被动元件,设置于粘合层中,并且电连接至第一基板和第二基板。本发明的目的在于提供一种扇出式基板及其形成方法,以优化扇出式基板的良率。

Figure 202110925745

An embodiment of the present invention provides a fan-out substrate, including: a first substrate and a second substrate that are stacked; an adhesive layer, located between the first substrate and the second substrate; a passive element, disposed on the adhesive layer , and is electrically connected to the first substrate and the second substrate. The purpose of the present invention is to provide a fan-out substrate and a method for forming the same, so as to optimize the yield of the fan-out substrate.

Figure 202110925745

Description

Fan-out substrate and method of forming the same
Technical Field
Embodiments of the present application relate to a fan-out substrate and a method of forming the same.
Background
The embedded passive component of the substrate comprises a capacitance element and an inductance element. Under the trend of larger substrate size and more layers, if the passive devices are embedded, many passive devices will fail due to the low yield of the process, thereby increasing the manufacturing cost. Embedded passive components are a necessary technology to save Package (PKG) thickness and planar area, and the defect density is limited by the inherent environment and process, so the process yield is lower when the number of layers is larger or the size is larger, and the enhanced environmental and process control can reduce the yield loss, but there is no fundamental solution.
If the number of layers of large-sized substrates is large and the passive devices are embedded, the process yield is not more than 90%, economic benefits are not obtained, too many failed passive devices are produced, and environmental pollution is also caused.
Disclosure of Invention
In view of the problems in the related art, an object of the present invention is to provide a fan-out substrate and a method for forming the same, so as to optimize the yield of the fan-out substrate.
To achieve the above object, an embodiment of the present invention provides a fan-out substrate, including: a first substrate and a second substrate stacked; an adhesive layer between the first substrate and the second substrate; and the passive element is arranged in the bonding layer and is electrically connected to the first substrate and the second substrate.
In some embodiments, the first substrate and the second substrate have or have not been provided with circuitry.
In some embodiments, the passive component is directly connected to the first substrate.
In some embodiments, the passive component is directly connected to the second substrate.
In some embodiments, further comprising: and an interconnection between the first substrate and the second substrate and connecting the first substrate and the second substrate.
In some embodiments, a first side of the passive component is connected to the first substrate, and a second side of the passive component, which is disposed opposite to the first side, is in contact with the second substrate.
In some embodiments, a first surface of the passive component is connected to the first substrate, and a second surface of the passive component, which is opposite to the first surface, is covered by the adhesive layer.
In some embodiments, further comprising: and the filling material is positioned between the first surface and the first substrate and covers the connecting piece positioned between the passive element and the first substrate.
In some embodiments, the filler material also covers portions of the sides of the passive element.
In some embodiments, the second substrate has a size smaller than the first substrate.
In some embodiments, a ratio of the volume of the passive element to the volume of the second substrate is between 5% and 20%.
Embodiments of the present application also provide a method of forming a fan-out substrate, comprising: stacking a passive element between the first substrate and the second substrate; an adhesive layer is formed between the first substrate and the second substrate and surrounding the passive element.
In some embodiments, the method specifically comprises: connecting the passive element to the second substrate; disposing an adhesive layer on a first substrate; the second substrate is disposed on the adhesive layer, and the passive element is disposed in the adhesive layer.
In some embodiments, further comprising: an interconnection is formed through the second substrate and the adhesive layer to be connected to the first substrate.
In some embodiments, the passive component also contacts the first substrate.
In some embodiments, the method specifically comprises: connecting the passive component and the interconnection component on the second substrate, wherein the interconnection component is positioned around the passive component; disposing the second substrate and the passive component on the first substrate, the interconnect engaging the first substrate; an adhesive layer is formed between the first substrate and the second substrate, the adhesive layer also encapsulating the interconnects.
In some embodiments, the method specifically comprises: connecting the passive element to the first substrate; connecting the interconnection to the second substrate; disposing a second substrate on the first substrate, the interconnects engaging the first substrate; an adhesive layer is formed between the first substrate and the second substrate, the adhesive layer also encapsulating the interconnects.
In some embodiments, the method specifically comprises: connecting the passive element to the first substrate; disposing an interconnect on a first substrate; forming an adhesive layer encapsulating the interconnect and the passive component; a second substrate is formed on the adhesive layer, and the interconnects engage the second substrate.
In some embodiments, the adhesive layer is a molding compound.
In some embodiments, the method specifically comprises: connecting the passive element to the first substrate; forming an adhesive layer encapsulating the passive element; forming a second substrate on the adhesive layer; an interconnection is formed through the second substrate and the adhesive layer to connect the first substrate.
Drawings
Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.
Fig. 1A-5C illustrate a process of forming a fan-out substrate according to various embodiments of the present application.
Fig. 6 and 7 show schematic structural views of different embodiments of the fan-out substrate of the present application.
Detailed Description
In order to better understand the spirit of the embodiments of the present application, the following further description is given in conjunction with some preferred embodiments of the present application.
Embodiments of the present application will be described in detail below. Throughout the specification, the same or similar components and components having the same or similar functions are denoted by like reference numerals. The embodiments described herein with respect to the figures are illustrative in nature, are diagrammatic in nature, and are used to provide a basic understanding of the present application. The embodiments of the present application should not be construed as limiting the present application.
As used herein, the terms "substantially", "substantially" and "about" are used to describe and illustrate minor variations. When used in conjunction with an event or circumstance, the terms can refer to instances where the event or circumstance occurs precisely as well as instances where the event or circumstance occurs in close proximity. For example, when used in conjunction with numerical values, the term can refer to a range of variation that is less than or equal to ± 10% of the stated numerical value, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%. For example, two numerical values are considered to be "substantially" identical if the difference between the two numerical values is less than or equal to ± 10% (e.g., less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%) of the mean of the values.
In this specification, unless specified or limited otherwise, relative terms such as: terms of "central," "longitudinal," "lateral," "front," "rear," "right," "left," "inner," "outer," "lower," "upper," "horizontal," "vertical," "above," "below," "top," "bottom," and derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," etc.) should be construed to refer to the orientation as then described in the discussion or as shown in the drawing figures. These relative terms are for convenience of description only and do not require that the present application be constructed or operated in a particular orientation.
Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such range format is used for convenience and brevity, and should be interpreted flexibly to include not only the numerical values explicitly recited as the limits of the range, but also to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited.
Moreover, for convenience in description, "first," "second," "third," etc. may be used herein to distinguish between different elements of a figure or series of figures. "first," "second," "third," etc. are not intended to describe corresponding components.
The fan-out substrate and the method of forming the same of the present application will be described in detail below with reference to the accompanying drawings.
Referring to fig. 1A, apassive component 10 is attached to asecond substrate 12. Thefilling material 14 is located between thepassive component 10 and thesecond substrate 12, and thefilling material 14 covers a portion of the sidewall of thepassive component 10. This prevents the formation of air bubbles during subsequent bonding with theadhesive layer 22. In some embodiments, the height of the portion of the sidewall of thepassive component 10 covered by thefilling material 14 is 0.1 μm to 5 μm. In some embodiments, the upper surface of the portion of thefiller material 14 not covered by thepassive element 10 is configured in a downwardly concave circular arc shape. Thefilling material 14 covers the connection 19 between thepassive component 10 and thefirst substrate 20. In some embodiments, thepassive element 10 includes a connector 19. In some embodiments, the thickness of thepassive element 10 is 25 μm to 125 μm. In some embodiments, the connectors 19 are solder balls, the maximum thickness of thefiller material 14 is greater than the diameter of the connectors 19, and the difference between the maximum thickness of thefiller material 14 and the diameter of the connectors 19 is less than 1/5 of the thickness of thepassive element 10, the diameter of the connectors 19 being 5 μm to 20 μm.
Referring to fig. 1B, anadhesive layer 22 is disposed on thefirst substrate 20. In some embodiments, the adhesive layer is a molding compound.
Referring to fig. 1C, thesecond substrate 12 and thepassive component 10 are disposed upside down over thefirst substrate 20, theadhesive layer 22 is located between thefirst substrate 12 and thesecond substrate 20, and thepassive component 10 is located in theadhesive layer 22.
Referring to fig. 1D, aninterconnection 40 is formed through thesecond substrate 12 and theadhesive layer 22 to be electrically connected to thefirst substrate 20. In some embodiments, theinterconnects 40 are through vias. In some embodiments, theinterconnects 40 are formed by laser drilling holes through thesecond substrate 12, theadhesion layer 22, and filling the holes with a metal material (e.g., Cu). Thus, the fan-out substrate 50 of the present application is formed. In some embodiments, the interconnect of embodiments of the present invention has a diameter of 10 μm to 50 μm, a ratio of a horizontal dimension of thesecond substrate 12 to thefirst substrate 20 is between 3/4 and 1, and a horizontal dimension of thefirst substrate 20 is 20mm to 200 mm. In some embodiments, theinterconnect 40 as a through hole of the embodiments of the present application has an aspect ratio of 1 to 10, and the diameter of theinterconnect 40 is 5 μm to 100 μm. In some embodiments, the ratio of the thickness of thepassive component 10 to the thickness of theadhesive layer 22 is between 0.2 and 1, and the thickness of theadhesive layer 22 is between 20 μm and 100 μm.
Fig. 2A to 2C show a process of forming a fan-out substrate according to a second embodiment of the present application. Referring to fig. 2A, when thepassive component 10 is attached to thesecond substrate 12, theinterconnect 40 is also attached to thesecond substrate 12, theinterconnect 40 being located around thepassive component 10. Embodiments of the present invention create a space between thefirst substrate 20 and thesecond substrate 12 through theinterconnection 40 in which passive components can be embedded.
In some embodiments, theinterconnects 40 are conductive pillars. In some embodiments, the top surface ofinterconnect 40 is not lower than the top surface ofpassive component 10. In some embodiments, unlike the embodiment shown in FIG. 1A, thefiller material 14 does not have a downwardly concave upper surface.
Referring to fig. 2B, thesecond substrate 12 is placed upside down on thefirst substrate 20, and theinterconnection 40 contacts and electrically connects thefirst substrate 20.
Referring to fig. 2C, anadhesive layer 22 is filled between thefirst substrate 20 and thesecond substrate 12. To this end, the fan-out substrate 50 of the second embodiment of the present application is formed.
Fig. 3A to 3D show a process of forming a fan-out substrate according to a third embodiment of the present application. Referring to fig. 3A, theinterconnects 40 are attached to thesecond substrate 12. In some embodiments, theinterconnects 40 are conductive pillars.
Referring to fig. 3B, thepassive element 10 is attached to thefirst substrate 20. In some embodiments, the height of theinterconnect 40 is not less than the height of thepassive element 10. A fillingmaterial 14 is formed between thepassive element 10 and thefirst substrate 20.
Referring to fig. 3C, thesecond substrate 12 is placed upside down on thefirst substrate 20, and theinterconnection 40 contacts and electrically connects thefirst substrate 20.
Referring to fig. 3D, anadhesive layer 22 is filled between thefirst substrate 20 and thesecond substrate 12. Thus, the fan-out substrate 50 of the third embodiment of the present application is formed.
Fig. 4A to 4C show a process of forming a fan-out substrate according to a fourth embodiment of the present application. Referring to fig. 4A, when thepassive element 10 is attached to thefirst substrate 20, theinterconnection 40 is also attached to thefirst substrate 20. In some embodiments, theinterconnects 40 are conductive pillars. In some embodiments, the top surface ofinterconnect 40 is not lower than the top surface ofpassive component 10. A fillingmaterial 14 is formed between thepassive element 10 and thefirst substrate 20.
Referring to fig. 4B, anadhesive layer 22 encapsulating thepassive elements 10 and theinterconnection 40 is formed. A planarization process is performed such that the top surfaces ofinterconnects 40 are flush with the top surface ofadhesion layer 22.
Referring to fig. 4C, thesecond substrate 12 is placed on theadhesive layer 22, and theinterconnection 40 contacts and electrically connects thesecond substrate 12. Thus, the fan-out substrate 50 of the fourth embodiment of the present application is formed.
Fig. 5A to 5C show a process of forming a fan-out substrate according to a fifth embodiment of the present application. Referring to fig. 5A, when thepassive element 10 is attached to thefirst substrate 20. A fillingmaterial 14 is formed between thepassive element 10 and thefirst substrate 20. Anadhesive layer 22 is formed encapsulating thepassive component 10.
Referring to fig. 5B, thesecond substrate 12 is placed on theadhesive layer 22.
Referring to fig. 5C, aninterconnection 40 passing through thesecond substrate 12 and theadhesive layer 22 to be electrically connected to thefirst substrate 20 is formed. In some embodiments, theinterconnects 40 are through vias. Thus, the fan-out substrate 50 of the fifth embodiment of the present application is formed.
Fig. 6 shows an embodiment different from fig. 1D, in which theadhesive layer 22, thesecond substrate 12, has a smaller horizontal dimension than thefirst substrate 20, so that the upper surface of thefirst substrate 20 is exposed. In some embodiments, a first side (upper surface) of thepassive component 10 is connected to thesecond substrate 12, and a second side (lower surface) of thepassive component 10 opposite to the first side is covered by theadhesive layer 22.
Fig. 7 shows a different embodiment from fig. 6, in some embodiments thepassive element 10 has the same thickness as theadhesive layer 22. The first surface (upper surface) of thepassive element 10 is connected to thesecond substrate 12, and the second surface (lower surface) of thepassive element 10, which is opposite to the first surface, is in contact with thefirst substrate 20.
An embodiment of the present invention provides a fan-outsubstrate 10, including: afirst substrate 20 and asecond substrate 12 stacked; anadhesive layer 22 between thefirst substrate 20 and thesecond substrate 12; and apassive element 10 disposed in theadhesive layer 22 and electrically connected to thefirst substrate 20 and thesecond substrate 12. In some embodiments, thefirst substrate 20 and thesecond substrate 12 are wired or not wired.
Embodiments of the present application utilize the concept of fan-out substrate (FOSub) to combine a known good first substrate and a known good second substrate (which may be a fan-out wiring layer, for example) to maintain high yield. Compared with the traditional embedded substrate, the FOsub can reduce the thickness of the packaging piece, reduce the layer number and reduce the cycle number. The passive element of the present application is disposed in an adhesive layer (adhesive layer), and in various embodiments of the present application, the passive element can be abutted against the first substrate and the second substrate to define a height or assist positioning. In some embodiments, the present application defines the distance and positioning between thefirst substrate 20 and thesecond substrate 12 byinterconnects 40, such as conductive pillars (Piilar).
Embodiments of the present invention address the yield issue of multi-layer and large-sized substrates through the concept of fan-out substrates. Thepassive device 10 of the embodiment of the invention may be an integrated passive device, such as an Integrated Passive Device (IPD) die, which can reduce the number of devices and thus increase the process yield, and can solve the problem of large footprint of multiple devices and minimize the size of the entire package. And the embodiment of the invention can save the thickness by embedding the IPD element in theadhesive layer 22 in the FOsub. In some embodiments, the embodiments of the present disclosure can reduce the occupied area by 1/5-1/4 and reduce the thickness by 25 μm to 50 μm compared to the conventional design. Further, the embodiment of the present invention may reduce the amount of the adhesive material by embedding thepassive component 10 into theadhesive layer 22, and in some embodiments, the ratio of the volume of thepassive component 10 to the volume of thesecond substrate 12 is between 5% and 20%, and the warpage of the whole structure is reduced by about 10% to 20%. In some embodiments, warpage of the overall structure in the range of 0.5 μm to 1.5mm is improved.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

Translated fromChinese
1.一种扇出式基板,其特征在于,包括:1. A fan-out substrate, characterized in that, comprising:叠置的第一基板和第二基板;stacked first and second substrates;粘合层,位于所述第一基板和所述第二基板之间;an adhesive layer between the first substrate and the second substrate;被动元件,设置于所述粘合层中,并且电连接至所述第一基板和所述第二基板。A passive element is disposed in the adhesive layer and is electrically connected to the first substrate and the second substrate.2.根据权利要求1所述的扇出式基板,其特征在于,所述第一基板和所述第二基板有设置线路或未设置线路。2 . The fan-out substrate according to claim 1 , wherein the first substrate and the second substrate are provided with or without lines. 3 .3.根据权利要求1所述的扇出式基板,其特征在于,所述被动元件与所述第一基板直接连接。3 . The fan-out substrate of claim 1 , wherein the passive element is directly connected to the first substrate. 4 .4.根据权利要求1所述的扇出式基板,其特征在于,所述被动元件与所述第二基板直接连接。4 . The fan-out substrate of claim 1 , wherein the passive element is directly connected to the second substrate. 5 .5.根据权利要求1所述的扇出式基板,其特征在于,还包括:5. The fan-out substrate of claim 1, further comprising:互连件,位于所述第一基板和所述第二基板之间,并且连接所述第一基板和所述第二基板。An interconnect is located between the first substrate and the second substrate and connects the first substrate and the second substrate.6.根据权利要求1所述的扇出式基板,其特征在于,所述被动元件的第一面连接所述第一基板,所述被动元件的与所述第一面相对设置的第二面和所述第二基板接触。6 . The fan-out substrate according to claim 1 , wherein the first surface of the passive element is connected to the first substrate, and the second surface of the passive element is arranged opposite to the first surface. 7 . in contact with the second substrate.7.根据权利要求1所述的扇出式基板,其特征在于,所述被动元件的第一面连接所述第一基板,所述被动元件的与所述第一面相对设置的第二面由所述粘合层包覆。7 . The fan-out substrate according to claim 1 , wherein the first surface of the passive element is connected to the first substrate, and the second surface of the passive element is opposite to the first surface. 8 . covered by the adhesive layer.8.根据权利要求7所述的扇出式基板,其特征在于,还包括:填充材料,位于所述第一面和所述第一基板之间,所述填充材料包覆位于所述被动元件和所述第一基板之间的连接件。8 . The fan-out substrate according to claim 7 , further comprising: a filling material located between the first surface and the first substrate, the filling material covering the passive element. 9 . and the first substrate.9.根据权利要求8所述的扇出式基板,其特征在于,所述填充材料还包覆所述被动元件的侧面的部分。9 . The fan-out substrate according to claim 8 , wherein the filling material further coats part of the side surface of the passive element. 10 .10.根据权利要求1所述的扇出式基板,其特征在于,所述第二基板的尺寸小于所述第一基板的尺寸。10 . The fan-out substrate of claim 1 , wherein the size of the second substrate is smaller than that of the first substrate. 11 .
CN202110925745.9A2021-08-122021-08-12 Fan-out substrate and method of forming the samePendingCN113851383A (en)

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US20070056766A1 (en)*2005-09-132007-03-15Shinko Electric Industries Co., Ltd.Electronic component embedded board and its manufacturing method
KR20170034843A (en)*2017-03-202017-03-29앰코 테크놀로지 코리아 주식회사Semiconductor device and manufacturing method thereof
CN107481998A (en)*2017-07-052017-12-15华为技术有限公司 Package structure and electronic device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
US20040150118A1 (en)*2003-02-032004-08-05Nec Electronics CorporationWarp-suppressed semiconductor device
US20070056766A1 (en)*2005-09-132007-03-15Shinko Electric Industries Co., Ltd.Electronic component embedded board and its manufacturing method
KR20170034843A (en)*2017-03-202017-03-29앰코 테크놀로지 코리아 주식회사Semiconductor device and manufacturing method thereof
CN107481998A (en)*2017-07-052017-12-15华为技术有限公司 Package structure and electronic device

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