CN113810050A - DAC with concentric parallelogram wiring and output impedance compensation - Google Patents

Abstract

The application discloses DAC with concentric parallelogram wiring and output impedance compensation belongs to integrated circuit technical field. The method mainly comprises the following steps: a digital signal input module; the device comprises a dynamic element matching decoder, a delay equalizer, a digital return-to-zero device, an output impedance compensation module and a current source integration module, wherein the current source integration module is used for respectively arranging all subunits of each unary high-order most significant bit and all subunits of each high-order middle significant bit into parallelograms which are uniformly distributed and concentric. The DAC has high output linearity, small mismatch error and time sequence skew error and can effectively reduce the integration area.

Description

DAC with concentric parallelogram wiring and output impedance compensation

Technical Field

The present application relates to the field of integrated circuit technology, and more particularly, to a DAC with concentric parallelogram routing and output impedance compensation.

Background

The traditional non-cascaded current unit DAC has the problems that the linearity of the DAC is influenced due to low output impedance, mismatch errors are large, and timing skew errors are large.

In the prior art, although there are many switching sequence methods that can determine the switching sequence of the current cell, thereby reducing the mismatch error, this solution has the phenomena of complicated wiring and non-uniform wiring, which can cause timing skew between different current cells and mismatch error caused by small transistors. Although the drive may be increased to mitigate timing skew, this increases the switching current and power consumption.

Disclosure of Invention

To address the problems with the prior art, the present application generally provides a DAC with concentric parallelogram wiring and output impedance compensation.

In order to achieve the above object, the present application adopts a technical solution that: there is provided a DAC with concentric parallelogram wiring and output impedance compensation, comprising: the digital signal input module is used for segmenting a digital signal input into the digital-to-analog converter to obtain a unary high-order most significant bit, an unary high-order middle significant bit, an unary high-order least significant bit and a binary low-order least significant bit; a dynamic element matching decoder for randomly selecting one bit of data from the unary high-order most significant bit, the unary high-order middle significant bit and the unary high-order least significant bit as the high-order significant bit of the analog signal; a delay equalizer for selecting one bit from the binary low-order least significant bits as the low-order significant bit of the analog signal; a digital nulling device for inserting a random number between a high significant bit and a low significant bit of the analog signal; the output impedance compensation module is used for controlling the current of the output port of the digital-to-analog converter so as to improve the output impedance of the digital-to-analog converter; the current source integration module is used for respectively arranging all the subunits of the high-order most significant bit of each unary and all the subunits of the high-order middle significant bit of each unary into parallelograms which are uniformly distributed and concentric; wherein concentric parallelograms are at least two parallelograms having the same geometric center.

The technical scheme of the application can reach the beneficial effects that: the present application designs a DAC with concentric parallelogram routing and output impedance compensation. The DAC uses the small-sized non-cascaded current unit to reduce the area of the current unit array and the wiring parasitic effect, so that the bandwidth can be enlarged, the driving is reduced, and the low power consumption is realized.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.

FIG. 1 is a schematic diagram of one embodiment of a DAC with concentric parallelogram routing and output impedance compensation according to the present application;

FIG. 2 is a schematic diagram of one embodiment of a DAC with concentric parallelogram routing and output impedance compensation according to the present application

Fig. 3 is a schematic diagram of another embodiment of a DAC with concentric parallelogram wiring and output impedance compensation according to the present application.

With the above figures, there are shown specific embodiments of the present application, which will be described in more detail below. These drawings and written description are not intended to limit the scope of the inventive concepts in any manner, but rather to illustrate the inventive concepts to those skilled in the art by reference to specific embodiments.

Detailed Description

The following detailed description of the preferred embodiments of the present application, taken in conjunction with the accompanying drawings, will provide those skilled in the art with a better understanding of the advantages and features of the present application, and will make the scope of the present application more clear and definite.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The following describes the technical solutions of the present application and how to solve the above technical problems with specific embodiments. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments. Embodiments of the present application will be described below with reference to the accompanying drawings.

Fig. 1 shows an embodiment of a DAC with concentric parallelogram wiring and output impedance compensation according to the present application.

In the embodiment shown in fig. 1, a DAC with concentric parallelogram wiring and output impedance compensation mainly includes a digital signal input module for segmenting a digital signal input to a digital-to-analog converter to obtain a unary upper most significant bit, an unary upper middle significant bit, and an unary upper least significant bit, and a binary lower least significant bit;

a dynamic element matching decoder for randomly selecting one bit of data from the unary high-order most significant bit, the unary high-order middle significant bit and the unary high-order least significant bit as the high-order significant bit of the analog signal;

a delay equalizer for selecting one bit from the binary low-order least significant bits as the low-order significant bit of the analog signal;

a digital nulling device for inserting a random number between a high significant bit and a low significant bit of the analog signal;

the output impedance compensation module is used for controlling the current of the output port of the digital-to-analog converter so as to improve the output impedance of the digital-to-analog converter;

the current source integration module is used for respectively arranging all the subunits of the high-order most significant bit of each unary and all the subunits of the high-order middle significant bit of each unary into parallelograms which are uniformly distributed and concentric; wherein concentric parallelograms are at least two parallelograms having the same geometric center.

In the specific embodiment, the area and the wiring parasitic effect of the current cell array are reduced by using the small-sized non-cascaded current cells, the purposes of expanding the bandwidth, reducing the driving and realizing low power consumption are achieved, mismatch errors caused by small transistors and timing sequence skew errors caused by a large number of cell wirings are reduced, and the linearity of the DAC is improved by using the output impedance compensation module, the digital return-to-zero device and the dynamic element matching decoder.

In the embodiment shown in fig. 1, the DAC with concentric parallelogram wiring and output impedance compensation includes a digital signal input module for segmenting a digital signal input to the digital-to-analog converter to obtain a unary upper most significant bit, an unary upper middle significant bit, and an unary upper least significant bit, and a binary lower least significant bit.

In one embodiment of the present application, a 14-bit digital signal is divided into 3 unary most significant bits, 3 unary least significant bits, and 5 binary least significant bits using a digital signal input block, and the digital signal after the division is input into the corresponding block.

In the specific embodiment, the digital signal is segmented, so that the accuracy of the digital-to-analog converter is improved, and the area of the digital-to-analog converter is reduced.

In the embodiment shown in fig. 1, the DAC having concentric parallelogram wiring and output impedance compensation further comprises a dynamic element matching decoder for randomly selecting one bit of data from among the unary upper most significant bit, the unary upper middle significant bit, and the unary upper least significant bit as the upper significant bit of the analog signal.

In one embodiment of the present application, as shown in fig. 2, the digital signal input module inputs the segmented 3 unary most significant bits, and 3 unary least significant bits into the dynamic element matching decoder, and the dynamic element matching decoder randomly selects one significant bit among the input unary most significant bits, and unary least significant bits for sampling.

For example, the unary most significant bit is selected to be sampled, and since the unary most significant bit has 3, when 3 unary most significant bits are input in parallel to the digital signal input block, at most 3 feedback units of 2 may be output in parallel³The 8 subunits of the unit number of =8bit, therefore, the aim of equally dividing the most significant bit of the unitary into M1-M7 subunits for control can be achieved.

The embodiment breaks up the nonlinear error of the digital-to-analog converter unit module caused by process mismatch.

In the embodiment shown in fig. 1, the DAC with concentric parallelogram wiring and output impedance compensation further comprises a delay equalizer for selecting one bit from binary lower least significant bits as the lower significant bit of the analog signal.

In one embodiment of the present application, 5 binary low least significant bits are transmitted to a delay equalizer as shown in fig. 2, and the delay equalizer delays and outputs any one bit of the 5 binary low least significant bits. And taking the output data as a low-order effective bit of a conversion result of the Digital-to-analog converter, wherein Digital input refers to a Digital signal input module, DEM decoder represents a dynamic element matching decoder, delay equalizer represents a delay equalizer, DRZ circult represents a Digital nulling device, OIC represents an output impedance compensation module, and CPR represents a current source integration module.

The embodiment enables the linearity of the digital-to-analog converter to be better by cooperating with the dynamic element matching decoder.

In the embodiment shown in fig. 1, the DAC with concentric parallelogram wiring and output impedance compensation further comprises a digital nulling device for inserting a random number between the more significant bit and the less significant bit of the analog signal.

In one embodiment of the present application, the associated distortion present in the output results of the dynamic element matching decoder and the delay equalizer is randomized using the random number R of the digital nulling device.

This embodiment enables the digital-to-analog converter to suppress both current source mismatch and transient induced distortion induced non-linearities, thereby greatly improving spurious free dynamic range and intermodulation distortion.

In the embodiment shown in fig. 1, the DAC with the concentric parallelogram wiring and the output impedance compensation further includes an output impedance compensation module, which is used for controlling the current magnitude of the output port of the digital-to-analog converter so as to increase the output impedance of the digital-to-analog converter.

In an embodiment of the present application, the output impedance compensation module includes a Digital comparator, a bias voltage Generator, an auxiliary DAC and a P-type MOS transistor, where the Digital comparator in fig. 2 refers to the Digital comparator, the Self-bias Generator refers to the bias voltage Generator, the auxiliary DAC refers to the auxiliary DAC, and the POMS refers to the P-type MOS transistor.

In this embodiment, the output impedance compensation module increases the output impedance of the digital-to-analog converter, compensates for the nonlinearity, and increases the linearity.

In the embodiment shown in fig. 1, the DAC with concentric parallelogram wiring and output impedance compensation further comprises a current source integration module for arranging all sub-cells of the upper most significant bit of each unary and all sub-cells of the upper middle significant bit of each unary in uniformly distributed and concentric parallelograms, respectively.

In one embodiment of the present application, as shown in fig. 3, each sub-cell of the high-most significant bit of an element divided into M1-M7 sub-cells is further divided into 32 sub-cells, and the 32 sub-cells are uniformly distributed in the form of concentric parallelograms, wherein the concentric parallelograms are two or more parallelograms having the same geometric center, that is, the intersection of the diagonals of the two or more parallelograms is the same point.

For example, a rectangular coordinate system is established with the lower left corner of the integrated circuit board as the origin, and the 32 small cells of M1 are uniformly distributed on the x-axis and the y-axis in the form of parallelograms at the coordinate origin. On the integrated circuit board, 32 small units of M2 are uniformly distributed on the x axis and the y axis in the form of parallelograms at the positions adjacent to the arranged M1 small units, and the parallelogram formed by M1 has the same geometric center as the parallelogram formed by M2. In this way, the M1-M7 subunits are arranged, and the most significant bits of the M1-M7 subunits are arranged in concentric parallelograms.

This particular embodiment can reduce gradient mismatch errors between cells by arranging the sub-cells of the higher most significant bits of a unary in a concentric parallelogram.

In a specific example of the present application, the parallelogram formed by all sub-cells of the higher middle significant bit of a unary is perpendicular to said parallelogram formed by all sub-cells of the higher most significant bit of a unary.

In one embodiment of the present application, to mitigate mismatches between a unary high-most significant bit segment and an unary high-least significant bit segment, a unary high-least significant bit sub-cell is doped within a layout array of unary high-most significant bit sub-cells.

For example, as shown in fig. 3, the unitary high least significant bit divided into UL1-UL7 sub-units is further divided into four small units, and on the integrated circuit board, four small units of UL1 are inserted beside the parallelogram of M1 arranged, and a parallelogram of unitary high middle significant bit is formed perpendicular to the parallelogram of M1. Four small units of UL2 were inserted alongside the parallelogram of the arrangement M2 and formed into a parallelogram of the higher middle significant bits of the unary perpendicular to the parallelogram of M2. According to this method, up to the arrangement of the subunits of UL1-UL7, the subunits of UL1-UL7 are arranged in concentric parallelograms, and the parallelogram of the subunits of UL1-UL7 is perpendicular to the parallelogram formed by all the subunits of M1-M7.

This embodiment can reduce mismatch errors between the unary high most significant bit and the unary high least significant bit and timing skew errors caused by a large number of unit wirings.

In one embodiment of the present application, each of the more significant bit current cells has two wiring paths from the vertex to the diagonal vertex of the parallelogram in the current source integrated module that completes the process. As in fig. 3, the number of connected sub-cells in the routing path of each most significant bit current cell is always equal to 16. Furthermore, the routing length of any two adjacent sub-cells where the current cell of the most significant bit connects the same current cell of the least significant bit is always equal to the length of the diagonal of the sub-cell. Since the switch control signals pass through the same routing length and the same number of sub-cells, the delay of the switch control signal from the output of the switch driver to each high-most significant bit current small cell is equal. Thus, timing offset errors caused by routing between different high most significant bit cells are contained.

The specific embodiment uses small-sized non-cascaded current cells to reduce the area of a current cell array and parasitic capacitance generated by wiring, thereby enlarging bandwidth, reducing driving and realizing low power consumption, and simultaneously reducing mismatch error caused by small transistors and timing skew error caused by a large number of unit wirings.

In one embodiment of the present application, the unary upper least significant bit and the binary lower least significant bit are combined into one sub-unit in the output impedance compensation module, and the sub-unit formed by combining the unary upper least significant bit and the binary lower least significant bit is a dummy unit.

This embodiment can reduce mismatch errors caused by small transistors and timing skew errors caused by a large number of unit wirings.

In a specific embodiment of the present application, the functional blocks in a DAC with concentric parallelogram wiring and output impedance compensation of the present application may be directly in hardware, in a software module executed by a processor, or in a combination of both.

A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium.

The Processor may be a Central Processing Unit (CPU), other general-purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), other Programmable logic devices, discrete Gate or transistor logic, discrete hardware components, or any combination thereof. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.

In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and all equivalent structural changes made by using the contents of the specification and the drawings, which are directly or indirectly applied to other related technical fields, are included in the scope of the present application.

Claims (5)

1. A DAC with concentric parallelogram wiring and output impedance compensation, comprising:

the digital signal input module is used for segmenting a digital signal input into the digital-to-analog converter to obtain a unary high-order most significant bit, an unary high-order middle significant bit, an unary high-order least significant bit and a binary low-order least significant bit;

a dynamic element matching decoder for randomly selecting one bit of data from the upper most significant bit of the unary, the upper middle significant bit of the unary, and the upper least significant bit of the unary as the upper significant bit of the analog signal;

a delay equalizer for selecting one bit from the binary least significant bit as the lower significant bit of the analog signal;

a digital nulling device for inserting a random number between the more significant bit and the less significant bit of the analog signal;

the output impedance compensation module is used for controlling the current of the output port of the digital-to-analog converter so as to improve the output impedance of the digital-to-analog converter;

which is characterized by comprising the following steps of,

the current source integration module is used for respectively arranging all the subunits of the high-order most significant bit of each unary and all the subunits of the high-order middle significant bit of each unary into a parallelogram which is uniformly distributed and concentric;

wherein the concentric parallelograms are such that at least two parallelograms have the same geometric center.

2. The DAC with concentric parallelogram wiring and output impedance compensation of claim 1,

the parallelogram formed by all sub-elements of the higher-order middle significant bit of the unary is perpendicular to the parallelogram formed by all sub-elements of the higher-order most significant bit of the unary.

3. The DAC with concentric parallelogram wiring and output impedance compensation of claim 1,

the unary upper least significant bit and the binary lower least significant bit are combined into a subunit in the output impedance compensation module.

4. The DAC with concentric parallelogram wiring and output impedance compensation of claim 3,

the sub-unit synthesized by the upper least significant bit of the unary and the lower least significant bit of the binary is a dummy unit.

5. The DAC with concentric parallelogram wiring and output impedance compensation of claim 1,

the output impedance compensation module comprises a digital comparator, a bias voltage generator, an auxiliary digital-to-analog converter and a P-type MOS tube.

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