技术领域technical field
本发明涉及一种降压转换器，特别涉及一种高转换效率的降压转换器。The invention relates to a step-down converter, in particular to a step-down converter with high conversion efficiency.
背景技术Background technique
一般低瓦特数的电源供应器通常会使用降压转换器来提升其功率因数。然而，在传统降压转换器当中，若其输入(整流)电位低于其输出电位，则会发生“死区(Dead Zone)”的问题，造成整体电路无法运行且转换效率降低。有鉴于此，势必要提出一种全新的解决方案，以克服现有技术所面临的困境。Generally low wattage power supplies usually use a buck converter to improve their power factor. However, in a traditional buck converter, if its input (rectified) potential is lower than its output potential, a "dead zone" problem will occur, resulting in the failure of the entire circuit and lower conversion efficiency. In view of this, it is necessary to propose a new solution to overcome the difficulties faced by the existing technologies.
发明内容Contents of the invention
在优选实施例中，本发明提出一种降压转换器，包括：一桥式整流器，根据一第一输入电位和一第二输入电位来产生一整流电位；一功率切换器，根据一时钟电位来选择性地将该桥式整流器耦接至一接地电位；一输出级电路，产生一输出电位；一检测及补偿电路，监控并比较该整流电位和该输出电位；一第一电感器，耦接于该检测及补偿电路和该输出级电路之间；以及一第一二极管，耦接至该检测及补偿电路和该第一电感器；其中若检测到该整流电位低于该输出电位，则该检测及补偿电路即重新调整该整流电位，使得重新调整后的该整流电位高于或等于该输出电位。In a preferred embodiment, the present invention provides a step-down converter, comprising: a bridge rectifier, which generates a rectified potential according to a first input potential and a second input potential; a power switch, which selectively couples the bridge rectifier to a ground potential according to a clock potential; an output stage circuit, which generates an output potential; a detection and compensation circuit, which monitors and compares the rectified potential and the output potential; a first inductor, coupled between the detection and compensation circuit and the output stage circuit; A detection and compensation circuit and the first inductor; if it is detected that the rectified potential is lower than the output potential, the detection and compensation circuit readjusts the rectified potential so that the readjusted rectified potential is higher than or equal to the output potential.
附图说明Description of drawings
图1是显示根据本发明一实施例所述的降压转换器的示意图。FIG. 1 is a schematic diagram showing a buck converter according to an embodiment of the invention.
图2是显示根据本发明一实施例所述的降压转换器的示意图。FIG. 2 is a schematic diagram showing a buck converter according to an embodiment of the invention.
图3是显示传统降压转换器的整流电位的电位波形图。FIG. 3 is a potential waveform diagram showing a rectified potential of a conventional buck converter.
图4是显示根据本发明一实施例所述的降压转换器的整流电位的电位波形图。FIG. 4 is a potential waveform diagram showing a rectified potential of the buck converter according to an embodiment of the invention.
其中，附图标记说明如下：Wherein, the reference signs are explained as follows:
100，200：降压转换器100, 200: buck converter
110，210：桥式整流器110, 210: bridge rectifier
120，220：功率切换器120, 220: power switcher
130，230：输出级电路130, 230: output stage circuit
160，260：检测及补偿电路160, 260: detection and compensation circuit
265：比较器265: Comparator
311，312：死区311, 312: dead zone
C1：第一电容器C1: first capacitor
C2：第二电容器C2: second capacitor
D1：第一二极管D1: first diode
D2：第二二极管D2: second diode
D3：第三二极管D3: third diode
D4：第四二极管D4: fourth diode
D5：第五二极管D5: fifth diode
D6：第六二极管D6: sixth diode
D7：第七二极管D7: seventh diode
L1：第一电感器L1: first inductor
L2：第二电感器L2: Second inductor
M1：第一晶体管M1: first transistor
M2：第二晶体管M2: second transistor
N1：第一节点N1: the first node
N2：第二节点N2: second node
N3：第三节点N3: the third node
N4：第四节点N4: the fourth node
N5：第五节点N5: fifth node
N6：第五节点N6: fifth node
NIN1：第一输入节点NIN1: first input node
NIN2：第二输入节点NIN2: second input node
NOUT：输出节点NOUT: output node
R1：电阻器R1: Resistor
VA：时钟电位VA: clock potential
VC：控制电位VC: control potential
VIN1：第一输入电位VIN1: the first input potential
VIN2：第二输入电位VIN2: second input potential
VOUT：输出电位VOUT: output potential
VR：整流电位VR: rectified potential
VSS：接地电位VSS: ground potential
具体实施方式Detailed ways
为让本发明的目的、特征和优点能更明显易懂，下文特举出本发明的具体实施例，并配合附图，作详细说明如下。In order to make the purpose, features and advantages of the present invention more comprehensible, specific embodiments of the present invention are listed below and described in detail with accompanying drawings.
在说明书及权利要求当中使用了某些词汇来指称特定的元件。本领域技术人员应可理解，硬件制造商可能会用不同的名词来称呼同一个元件。本说明书及权利要求并不以名称的差异作为区分元件的方式，而是以元件在功能上的差异作为区分的准则。在通篇说明书及权利要求当中所提及的“包含”及“包括”一词为开放式的用语，故应解释成“包含但不仅限定于”。“大致”一词则是指在可接受的误差范围内，本领域技术人员能够在一定误差范围内解决所述技术问题，达到所述基本的技术效果。此外，“耦接”一词在本说明书中包含任何直接及间接的电性连接手段。因此，若文中描述一第一装置耦接至一第二装置，则代表该第一装置可直接电性连接至该第二装置，或经由其它装置或连接手段而间接地电性连接至该第二装置。Certain terms are used in the description and claims to refer to particular elements. Those skilled in the art should understand that hardware manufacturers may use different terms to refer to the same component. The specification and claims do not use the difference in name as a way to distinguish components, but use the difference in function of components as a criterion for distinguishing. The words "comprising" and "comprising" mentioned throughout the specification and claims are open-ended terms, so they should be interpreted as "including but not limited to". The term "approximately" means that within an acceptable error range, those skilled in the art can solve the technical problem within a certain error range and achieve the basic technical effect. In addition, the term "coupled" in this specification includes any direct and indirect electrical connection means. Therefore, if it is described that a first device is coupled to a second device, it means that the first device may be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connection means.
图1是显示根据本发明一实施例所述的降压转换器100的示意图。例如，降压转换器100可应用于一电源供应器，但亦不仅限于此。如图1所示，降压转换器100包括：一桥式整流器110、一功率切换器120、一输出级电路130、一第一二极管D1、一第一电感器L1，以及一检测及补偿电路160。必须注意的是，虽然未显示于图1中，但降压转换器100还可包括其他元件，例如：一稳压器或(且)一负反馈电路。FIG. 1 is a schematic diagram showing a buck converter 100 according to an embodiment of the invention. For example, the buck converter 100 can be applied to a power supply, but it is not limited thereto. As shown in FIG. 1 , the buck converter 100 includes: a bridge rectifier 110 , a power switch 120 , an output stage circuit 130 , a first diode D1 , a first inductor L1 , and a detection and compensation circuit 160 . It should be noted that although not shown in FIG. 1 , the buck converter 100 may also include other components, such as a voltage regulator and/or a negative feedback circuit.
桥式整流器110可根据一第一输入电位VIN1和一第二输入电位VIN2来产生一整流电位VR。第一输入电位VIN1和第二输入电位VIN2皆可来自一外部输入电源，其中第一输入电位VIN1和第二输入电位VIN2之间可形成具有任意频率和任意振幅的一交流电压。例如，交流电压的频率可约为50Hz或60Hz，而交流电压的方均根值可约由90V至264V，但亦不仅限于此。功率切换器120是根据一时钟电位VA来选择性地将桥式整流器110耦接至一接地电位VSS(例如：0V)。时钟电位VA于降压转换器100初始化时可维持于一固定电位，而在降压转换器100进入正常使用阶段后则可提供周期性的时钟波形。例如，若时钟电位VA为高逻辑电平(例如：逻辑“1”)，则功率切换器120即将桥式整流器110耦接至接地电位VSS(亦即，功率切换器120可近似于一短路路径)；反之，若时钟电位VA为低逻辑电平(例如：逻辑“0”)，则功率切换器120不会将桥式整流器110耦接至接地电位VSS(亦即，功率切换器120可近似于一开路路径)。输出级电路130可产生一输出电位VOUT，其可大致为一直流电位。第一电感器L1是耦接于检测及补偿电路160和输出级电路130之间。第一二极管D1是同时耦接至检测及补偿电路160和第一电感器L1。检测及补偿电路160是用于监控并比较整流电位VR和输出电位VOUT。详细而言，若检测到整流电位VR低于输出电位VOUT，则检测及补偿电路160即可重新调整前述的整流电位VR，使得重新调整后的整流电位VR高于或等于输出电位VOUT；反之，若检测到整流电位VR已高于或等于输出电位VOUT，则检测及补偿电路160不会再重新调整前述的整流电位VR。在此设计下，由于检测及补偿电路160可保证整流电位VR一定高于或等于输出电位VOUT，故降压转换器100的所有操作周期中皆不会出现任何死区，从而能大幅提升降压转换器100的转换效率。The bridge rectifier 110 can generate a rectified potential VR according to a first input potential VIN1 and a second input potential VIN2 . Both the first input potential VIN1 and the second input potential VIN2 can come from an external input power source, wherein an AC voltage with any frequency and any amplitude can be formed between the first input potential VIN1 and the second input potential VIN2 . For example, the frequency of the AC voltage can be about 50 Hz or 60 Hz, and the root mean square value of the AC voltage can be about 90V to 264V, but it is not limited thereto. The power switch 120 selectively couples the bridge rectifier 110 to a ground potential VSS (eg, 0V) according to a clock potential VA. The clock potential VA can be maintained at a fixed potential when the buck converter 100 is initialized, and a periodic clock waveform can be provided after the buck converter 100 enters a normal use stage. For example, if the clock potential VA is a high logic level (for example: logic “1”), the power switch 120 is about to couple the bridge rectifier 110 to the ground potential VSS (that is, the power switch 120 can be approximated as a short-circuit path); otherwise, if the clock potential VA is a low logic level (for example: logic “0”), the power switch 120 will not couple the bridge rectifier 110 to the ground potential VSS (that is, the power switch 120 can be approximated as an open path). . The output stage circuit 130 can generate an output potential VOUT, which can be approximately a DC potential. The first inductor L1 is coupled between the detection and compensation circuit 160 and the output stage circuit 130 . The first diode D1 is coupled to the detection and compensation circuit 160 and the first inductor L1 at the same time. The detection and compensation circuit 160 is used for monitoring and comparing the rectified potential VR and the output potential VOUT. In detail, if it is detected that the rectified potential VR is lower than the output potential VOUT, the detection and compensation circuit 160 can readjust the aforementioned rectified potential VR so that the readjusted rectified potential VR is higher than or equal to the output potential VOUT; otherwise, if it is detected that the rectified potential VR is higher than or equal to the output potential VOUT, the detection and compensation circuit 160 will not readjust the aforementioned rectified potential VR. Under this design, since the detection and compensation circuit 160 can ensure that the rectified potential VR must be higher than or equal to the output potential VOUT, there will be no dead zone in all operation cycles of the buck converter 100 , thereby greatly improving the conversion efficiency of the buck converter 100 .
以下实施例将介绍降压转换器100的详细结构及操作方式。必须理解的是，这些附图和叙述仅为举例，而非用于限制本发明的范围。The following embodiments will introduce the detailed structure and operation of the buck converter 100 . It must be understood that these drawings and descriptions are only examples and not intended to limit the scope of the present invention.
图2是显示根据本发明一实施例所述的降压转换器200的示意图。在图2的实施例中，降压转换器200具有一第一输入节点NIN1、一第二输入节点NIN2，以及一输出节点NOUT，并包括一桥式整流器210、一功率切换器220、一输出级电路230、一第一二极管D1、一第一电感器L1，以及一检测及补偿电路260。降压转换器200的第一输入节点NIN1和第二输入节点NIN2可由一外部输入电源处分别接收一第一输入电位VIN1和一第二输入电位VIN2，其中第一输入电位VIN1和第二输入电位VIN2之间可形成具有任意频率和任意振幅的一交流电压。降压转换器200的输出节点NOUT可输出一输出电位VOUT，其可大致为一直流电位。FIG. 2 is a schematic diagram showing a buck converter 200 according to an embodiment of the invention. In the embodiment of FIG. 2 , the buck converter 200 has a first input node NIN1, a second input node NIN2, and an output node NOUT, and includes a bridge rectifier 210, a power switch 220, an output stage circuit 230, a first diode D1, a first inductor L1, and a detection and compensation circuit 260. The first input node NIN1 and the second input node NIN2 of the step-down converter 200 can respectively receive a first input potential VIN1 and a second input potential VIN2 from an external input power source, wherein an AC voltage with any frequency and any amplitude can be formed between the first input potential VIN1 and the second input potential VIN2. The output node NOUT of the buck converter 200 can output an output potential VOUT, which can be approximately a DC potential.
桥式整流器210包括一一第二二极管D2、一第三二极管D3、一第四二极管D4，以及一第五二极管D5。第二二极管D2的阳极是耦接至第一输入节点NIN1，而第二二极管D2的阴极是耦接至一第一节点N1以输出一整流电位VR。第三二极管D3的阳极是耦接至第二输入节点NIN2，而第三二极管D3的阴极是耦接至第一节点N1。第四二极管D4具有一阳极和一阴极，其中第四二极管D4的阳极是耦接至一第二节点N2，而第四二极管D4的阴极是耦接至第一输入节点NIN1。第五二极管D5的阳极是耦接至第二节点N2，而第五二极管D5的阴极是耦接至第二输入节点NIN2。The bridge rectifier 210 includes a second diode D2, a third diode D3, a fourth diode D4, and a fifth diode D5. The anode of the second diode D2 is coupled to the first input node NIN1 , and the cathode of the second diode D2 is coupled to a first node N1 to output a rectified potential VR. The anode of the third diode D3 is coupled to the second input node NIN2, and the cathode of the third diode D3 is coupled to the first node N1. The fourth diode D4 has an anode and a cathode, wherein the anode of the fourth diode D4 is coupled to a second node N2, and the cathode of the fourth diode D4 is coupled to the first input node NIN1. The anode of the fifth diode D5 is coupled to the second node N2, and the cathode of the fifth diode D5 is coupled to the second input node NIN2.
功率切换器220包括一第一晶体管M1，其可视为降压转换器200的一主要切换器。第一晶体管M1可以是一N型金属氧化物半导体场效晶体管。第一晶体管M1的控制端是用于接收一时钟电位VA，第一晶体管M1的第一端是耦接至第二节点N2，而第一晶体管M1的第二端是耦接至一接地电位VSS(例如：0V)。例如，时钟电位VA于降压转换器200初始化时可维持于一固定电位(例如：接地电位VSS)，而在降压转换器200进入正常使用阶段后则可提供周期性的时钟波形。在一些实施例中，若时钟电位VA为高逻辑电平，则第一晶体管M1将被使能；反之，若时钟电位VA为低逻辑电平，则第一晶体管M1将被禁能。The power switch 220 includes a first transistor M1, which can be regarded as a main switch of the buck converter 200 . The first transistor M1 may be an NMOS field effect transistor. The control terminal of the first transistor M1 is used to receive a clock potential VA, the first terminal of the first transistor M1 is coupled to the second node N2, and the second terminal of the first transistor M1 is coupled to a ground potential VSS (for example: 0V). For example, the clock potential VA can be maintained at a fixed potential (such as the ground potential VSS) when the buck converter 200 is initialized, and a periodic clock waveform can be provided after the buck converter 200 enters a normal use stage. In some embodiments, if the clock potential VA is at a high logic level, the first transistor M1 will be enabled; otherwise, if the clock potential VA is at a low logic level, the first transistor M1 will be disabled.
第一二极管D1的阳极是耦接至接地电位VSS，而第一二极管D1的阴极是耦接至一第三节点N3。The anode of the first diode D1 is coupled to the ground potential VSS, and the cathode of the first diode D1 is coupled to a third node N3.
输出级电路230包括一第一电容器C1。第一电容器C1的第一端是耦接至输出节点NOUT，而第一电容器C1的第二端是耦接至接地电位VSS。The output stage circuit 230 includes a first capacitor C1. A first terminal of the first capacitor C1 is coupled to the output node NOUT, and a second terminal of the first capacitor C1 is coupled to the ground potential VSS.
第一电感器L1可视为降压转换器200的一降压电感器。第一电感器L1的第一端是耦接至第三节点N3，而第一电感器L1的第二端是耦接至输出节点NOUT。The first inductor L1 can be regarded as a buck inductor of the buck converter 200 . A first terminal of the first inductor L1 is coupled to the third node N3, and a second terminal of the first inductor L1 is coupled to the output node NOUT.
检测及补偿电路260包括：一比较器265、一第二晶体管M2、一第六二极管D6、一第七二极管D7、一电阻器R1、一第二电感器L2，以及一第二电容器C2。比较器265可以用一运算放大器来实施。详细而言，比较器265的正输入端是用于接收输出电位VOUT，比较器265的负输入端是用于接收整流电位VR，而比较器265的输出端是用于输出一控制电位VC。例如，若整流电位VR低于输出电位VOUT，则比较器265将输出具有高逻辑电平的控制电位VC；反之，若整流电位VR高于或等于输出电位VOUT，则比较器265将输出具有低逻辑电平的控制电位VC。The detection and compensation circuit 260 includes: a comparator 265, a second transistor M2, a sixth diode D6, a seventh diode D7, a resistor R1, a second inductor L2, and a second capacitor C2. Comparator 265 can be implemented with an operational amplifier. In detail, the positive input terminal of the comparator 265 is used to receive the output potential VOUT, the negative input terminal of the comparator 265 is used to receive the rectified potential VR, and the output terminal of the comparator 265 is used to output a control potential VC. For example, if the rectified potential VR is lower than the output potential VOUT, the comparator 265 will output the control potential VC with a high logic level; otherwise, if the rectified potential VR is higher than or equal to the output potential VOUT, the comparator 265 will output the control potential VC with a low logic level.
第二晶体管M2可以是一N型金属氧化物半导体场效晶体管。第二晶体管M2的控制端是用于接收控制电位VC，第二晶体管M2的第一端是耦接至一第四节点N4，而第二晶体管M2的第二端是耦接至一第五节点N5。在一些实施例中，若控制电位VC为高逻辑电平，则第二晶体管M2将被使能；反之，若控制电位VC为低逻辑电平，则第二晶体管M2将被禁能。The second transistor M2 may be an NMOS field effect transistor. The control terminal of the second transistor M2 is used to receive the control potential VC, the first terminal of the second transistor M2 is coupled to a fourth node N4, and the second terminal of the second transistor M2 is coupled to a fifth node N5. In some embodiments, if the control potential VC is at a high logic level, the second transistor M2 will be enabled; otherwise, if the control potential VC is at a low logic level, the second transistor M2 will be disabled.
第六二极管D6的阳极是耦接至第四节点N4，而第六二极管D6的阴极是耦接至第一节点N1。电阻器R1的第一端是耦接至第一节点N1，而电阻器R1的第二端是耦接至第五节点N5。The anode of the sixth diode D6 is coupled to the fourth node N4, and the cathode of the sixth diode D6 is coupled to the first node N1. A first end of the resistor R1 is coupled to the first node N1, and a second end of the resistor R1 is coupled to the fifth node N5.
第二电感器L2的第一端是耦接至第五节点N5，而第二电感器L2的第二端是耦接至第三节点N3。第二电容器C2的第一端是耦接至第五节点N5，而第二电容器C2的第二端是耦接至一第六节点N6。第七二极管D7的阳极是耦接至第六节点N6，而第七二极管D7的阴极是耦接至第三节点N3。在一些实施例中，第二电感器L2是与第一电感器L1形成于同一铁芯上，使得第二电感器L2和第一电感器L1可以互相耦合。A first terminal of the second inductor L2 is coupled to the fifth node N5, and a second terminal of the second inductor L2 is coupled to the third node N3. A first terminal of the second capacitor C2 is coupled to the fifth node N5, and a second terminal of the second capacitor C2 is coupled to a sixth node N6. The anode of the seventh diode D7 is coupled to the sixth node N6, and the cathode of the seventh diode D7 is coupled to the third node N3. In some embodiments, the second inductor L2 is formed on the same core as the first inductor L1, so that the second inductor L2 and the first inductor L1 can be coupled to each other.
在一些实施例中，降压转换器200的操作原理可如下列所述。在一初始模式中，降压转换器200尚未接收到第一输入电位VIN1和第二输入电位VIN2，且时钟电位VA维持于低逻辑电平，故第一晶体管M1和第二晶体管M2皆为禁能状态，而第一二极管D1和第七二极管D7皆为断路状态。接着，在降压转换器200已接收到第一输入电位VIN1和第二输入电位VIN2之后，降压转换器200可交替地操作于一第一模式、一第二模式，以及一第三模式。In some embodiments, the operation principle of the buck converter 200 can be as follows. In an initial mode, the step-down converter 200 has not received the first input potential VIN1 and the second input potential VIN2, and the clock potential VA is maintained at a low logic level, so both the first transistor M1 and the second transistor M2 are in a disabled state, and both the first diode D1 and the seventh diode D7 are in a disconnected state. Then, after the buck converter 200 has received the first input potential VIN1 and the second input potential VIN2 , the buck converter 200 can alternately operate in a first mode, a second mode, and a third mode.
在第一模式中，时钟电位VA处于高逻辑电平以使能第一晶体管M1，而整流电位VR是高于或等于输出电位VOUT，故控制电位VC为低逻辑电平以禁能第二晶体管M2。此时，第一二极管D1和第七二极管D7皆为断路状态，而第一电感器L1、第二电感器L2，以及第二电容器C2皆逐渐存储能量。必须注意的是，由于第七二极管D7为断路状态，故第二电容器C2不会与第二电感器L2发生谐振，也不会有任何谐振电压或谐振能量影响降压转换器200的操作。In the first mode, the clock potential VA is at a high logic level to enable the first transistor M1, and the rectification potential VR is higher than or equal to the output potential VOUT, so the control potential VC is at a low logic level to disable the second transistor M2. At this time, both the first diode D1 and the seventh diode D7 are in an off state, and the first inductor L1, the second inductor L2, and the second capacitor C2 gradually store energy. It should be noted that since the seventh diode D7 is in the off state, the second capacitor C2 will not resonate with the second inductor L2, and there will be no resonant voltage or resonant energy affecting the operation of the buck converter 200 .
在第二模式中，时钟电位VA处于低逻辑电平以禁能第一晶体管M1，而整流电位VR是高于或等于输出电位VOUT，故控制电位VC为低逻辑电平以禁能第二晶体管M2。此时，第一二极管D1为通路状态，第七二极管D7为断路状态，第二电感器L2和第二电容器C2皆逐渐存储能量，而第一电感器L1则逐渐释放能量给第一电容器C1。In the second mode, the clock potential VA is at a low logic level to disable the first transistor M1, and the rectification potential VR is higher than or equal to the output potential VOUT, so the control potential VC is at a low logic level to disable the second transistor M2. At this time, the first diode D1 is in the on state, the seventh diode D7 is in the off state, the second inductor L2 and the second capacitor C2 gradually store energy, and the first inductor L1 gradually releases energy to the first capacitor C1.
在第四模式中，无论时钟电位VA为高逻辑电平或低逻辑电平，整流电位VR皆低于输出电位VOUT，故控制电位VC为高逻辑电平以使能第二晶体管M2。此时，降压转换器200是处于异常操作状态，而检测及补偿电路260将自动重新调整前述的整流电位VR。详细而言，先前存储于第二电容器C2的能量可经由使能的第二晶体管M2和导通的第六二极管D6传送至第一节点N1，以拉升整流电位VR的电平至输出电位VOUT之上。另外，第二电感器L2则可补充能量给第二电容器C2，以维持整流电位VR于一稳定电平。最终，降压转换器200会自动回复至正常操作状态。In the fourth mode, regardless of whether the clock potential VA is a high logic level or a low logic level, the rectification potential VR is lower than the output potential VOUT, so the control potential VC is a high logic level to enable the second transistor M2. At this time, the buck converter 200 is in an abnormal operation state, and the detection and compensation circuit 260 will automatically readjust the aforementioned rectification potential VR. In detail, the energy previously stored in the second capacitor C2 can be transferred to the first node N1 through the enabled second transistor M2 and the turned-on sixth diode D6 to pull up the level of the rectified potential VR above the output potential VOUT. In addition, the second inductor L2 can supplement energy to the second capacitor C2 to maintain the rectification potential VR at a stable level. Eventually, the buck converter 200 will automatically return to the normal operation state.
图3是显示传统降压转换器的整流电位VR的电位波形图。若未使用检测及补偿电路260，则传统降压转换器将于每一操作周期中出现至少两个死区311、312(亦即，当整流电位VR低于输出电位VOUT时)，此将对传统降压转换器的转换效率造成负面影响。FIG. 3 is a potential waveform diagram showing a rectified potential VR of a conventional step-down converter. If the detection and compensation circuit 260 is not used, the conventional buck converter will have at least two dead zones 311, 312 in each operation cycle (ie, when the rectified potential VR is lower than the output potential VOUT), which will negatively affect the conversion efficiency of the conventional buck converter.
图4是显示根据本发明一实施例所述的降压转换器200的整流电位VR的电位波形图。若已在降压转换器200中加入检测及补偿电路260，则因整流电位VR恒高于输出电位VOUT，故降压转换器200于所有操作周期中均不会出现任何死区。根据实际测量结果，使用检测及补偿电路260的降压转换器200的转换效率将可大幅提升。FIG. 4 is a potential waveform diagram showing the rectified potential VR of the buck converter 200 according to an embodiment of the invention. If the detection and compensation circuit 260 is added to the buck converter 200, since the rectified voltage VR is always higher than the output voltage VOUT, the buck converter 200 will not have any dead zone in all operation cycles. According to actual measurement results, the conversion efficiency of the buck converter 200 using the detection and compensation circuit 260 can be greatly improved.
在一些实施例中，降压转换器200的元件参数可如下列所述。第一电容器C1的电容值可介于646μF至714μF之间，优选为680μF。第二电容器C2的电容值可介于108μF至132μF之间，优选为120μF。第一电感器L1的电感值可介于90.25μH至99.75μH之间，优选为95μH。第二电感器L2的电感值可介于36μH至44μH之间，优选为40μH。电阻器R1的电阻值可介于0.9KΩ至1.1KΩ之间，优选为1KΩ。时钟电位VA的切换频率可约为65kHz。以上参数范围是根据多次实验结果而得出，其有助于最佳化降压转换器200的转换效率。In some embodiments, the component parameters of the buck converter 200 may be as follows. The capacitance of the first capacitor C1 can be between 646 μF to 714 μF, preferably 680 μF. The capacitance of the second capacitor C2 can be between 108 μF and 132 μF, preferably 120 μF. The inductance of the first inductor L1 can be between 90.25 μH to 99.75 μH, preferably 95 μH. The inductance of the second inductor L2 can be between 36 μH to 44 μH, preferably 40 μH. The resistance value of the resistor R1 can be between 0.9KΩ and 1.1KΩ, preferably 1KΩ. The switching frequency of the clock potential VA may be about 65 kHz. The above parameter ranges are obtained according to the results of multiple experiments, which help to optimize the conversion efficiency of the buck converter 200 .
本发明提出一种新颖的降压转换器，其包括检测及补偿电路。根据实际测量结果，使用前述设计的降压转换器可完全消除其每一操作周期中的死区。大致而言，本发明可有效改善降压转换器的整体转换效率，故其很适合应用于各种各式的电子装置当中。The present invention proposes a novel buck converter including a detection and compensation circuit. According to actual measurement results, the dead zone in each operating cycle of the buck converter can be completely eliminated using the aforementioned design. Generally speaking, the present invention can effectively improve the overall conversion efficiency of the buck converter, so it is very suitable for application in various electronic devices.
值得注意的是，以上所述的电位、电流、电阻值、电感值、电容值，以及其余元件参数均非为本发明的限制条件。设计者可以根据不同需要调整这些设定值。本发明的降压转换器并不仅限于图1-图4所示的状态。本发明可以仅包括图1-图4的任何一或多个实施例的任何一或多项特征。换言之，并非所有图示的特征均须同时实施于本发明的降压转换器当中。虽然本发明的实施例是使用金属氧化物半导体场效晶体管为例，但本发明并不仅限于此，本技术领域人士可改用其他种类的晶体管，例如：接面场效晶体管，或是鳍式场效晶体管等等，而不致于影响本发明的效果。It should be noted that the potential, current, resistance value, inductance value, capacitance value, and other component parameters mentioned above are not limiting conditions of the present invention. Designers can adjust these settings according to different needs. The buck converter of the present invention is not limited to the states shown in FIGS. 1-4 . The present invention may only include any one or more features of any one or more of the embodiments of FIGS. 1-4 . In other words, not all the illustrated features must be implemented in the buck converter of the present invention at the same time. Although the embodiment of the present invention uses metal-oxide-semiconductor field effect transistors as an example, the present invention is not limited thereto. Those skilled in the art can use other types of transistors, such as junction field effect transistors or fin field effect transistors, etc., without affecting the effect of the present invention.
本发明虽以优选实施例公开如上，然其并非用以限定本发明的范围，任何熟习此项技艺者，在不脱离本发明的精神和范围内，当可做些许的变动与润饰，因此本发明的保护范围当视后附的权利要求所界定者为准。Although the present invention is disclosed as above with preferred embodiments, it is not intended to limit the scope of the present invention. Any person skilled in this art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as defined by the appended claims.
| Application Number | Priority Date | Filing Date | Title |
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| CN202010493366.2ACN113765415B (en) | 2020-06-03 | 2020-06-03 | buck converter |
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| CN202010493366.2ACN113765415B (en) | 2020-06-03 | 2020-06-03 | buck converter |
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| CN202010493366.2AActiveCN113765415B (en) | 2020-06-03 | 2020-06-03 | buck converter |
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