技术领域Technical field
本发明涉及生物传感器的微机电系统(MEMS)微加工领域、电刺激调控领域和神经细胞区室化培养领域，是一种集成微流控、微电极阵列的神经元非门逻辑功能芯片及其制备方法。The invention relates to the field of micro-electromechanical system (MEMS) microprocessing of biosensors, the field of electrical stimulation regulation and the field of compartmentalized culture of nerve cells. It is a neuron NOT gate logic functional chip integrating microfluidics and microelectrode arrays and its Preparation.
背景技术Background technique
人类具有世界上最复杂、最精密的物质结构——具有思维能力的大脑。通过大脑的日常运作，让人类能够很轻易的完成现在人工智能难以完成的高级且复杂的工作。揭示大脑高级功能的奥秘不仅是自然科学的顶尖谜题之一，更是当前神经科学面临的重大挑战，也是突破当前人工智能发展的重大阻碍。Human beings have the most complex and sophisticated physical structure in the world - the brain with the ability to think. Through the daily operation of the brain, humans can easily complete advanced and complex tasks that are currently difficult for artificial intelligence to complete. Revealing the mysteries of the brain's advanced functions is not only one of the top mysteries of natural science, but also a major challenge facing current neuroscience and a major obstacle to breaking through the current development of artificial intelligence.
脑的所有高级功能的实现都离不开信息的传递、处理和存储。脑具有感知、意识、行为、记忆以及学习等多种高级功能。而脑之所以有如此复杂的功能是因为脑内有数以千亿计的神经，这些神经元通过突触连接形成错综复杂的神经网络，不同神经网络相互交错相互连接，进而形成处理能力比现代计算机还强的人体大脑。不论是简单的膝跳反应还是人类复杂的记忆能力，都与大脑中的不同脑区的信息传递息息相关，而大脑中神经网络的信息传导是通过神经细胞脉冲放电和神经递质传递完成的。The realization of all advanced functions of the brain is inseparable from the transmission, processing and storage of information. The brain has multiple advanced functions such as perception, consciousness, behavior, memory, and learning. The reason why the brain has such complex functions is that there are hundreds of billions of nerves in the brain. These neurons are connected through synapses to form intricate neural networks. Different neural networks are intertwined and connected with each other, thus forming a processing power greater than that of modern computers. Strong human brain. Whether it is a simple knee-jerk reaction or the complex memory ability of humans, they are closely related to the transmission of information in different brain areas. The information transmission of neural networks in the brain is completed through the impulse discharge of nerve cells and the transmission of neurotransmitters.
微电极阵列(MEA)作为神经网络与电子系统之间的接口工具，有助于科学家们深入了解神经网络的动力学以及对生物物质的反应，进而为科学家们揭示神经网络的功能提供可能。而微流控技术因为其精准化控制、微尺度操控等特点被广泛用于定制化体外培养特定的神经网络。通过结合微电极阵列技术与微流控技术使得体外开发神经网络的高级功能成为了可能。As an interface tool between neural networks and electronic systems, microelectrode arrays (MEAs) help scientists gain an in-depth understanding of the dynamics of neural networks and their responses to biological substances, thereby making it possible for scientists to reveal the functions of neural networks. Microfluidic technology is widely used to customize specific neural networks in vitro because of its precise control and micro-scale manipulation. Combining microelectrode array technology with microfluidic technology makes it possible to develop advanced functions of neural networks in vitro.
许多研究表明，外部电刺激能够激发神经元网络的学习、记忆等功能。通过外部电刺激能够更好地在体外开发神经元网络的功能。Many studies have shown that external electrical stimulation can stimulate learning, memory and other functions of neuronal networks. The function of neuronal networks can be better developed in vitro through external electrical stimulation.
发明内容Contents of the invention
本发明的目的是提供一种集成微流控、微电极阵列的神经元非门逻辑功能芯片及其制备方法。该芯片通过集成了微电极阵列与微流控芯片实现两个神经元网络在设计的微沟道中形成多组一对一的神经元互连。使用电刺激技术对微沟道输入端进行电刺激，影响输入端神经元的放电情况，由于两端神经元在微沟道中产生突触连接，输入端神经元的信号会传递到输出端神经元，输出端的神经元随着传递信息的不同产生不同的相应。因此，我们在神经元层面上构建一对一有一定逻辑功能的控制单元，通过电刺激参数的改变和培养细胞类型的不同，我们能在体外使得该控制的单元具有类似电子非门逻辑器件的功能。该发明使得体外开发神经元网络高级功能成为可能，从而促进大脑高级功能体外开发等相关研究工作。The purpose of the present invention is to provide a neuron NOT gate logic functional chip integrating microfluidics and microelectrode arrays and a preparation method thereof. The chip integrates a microelectrode array and a microfluidic chip to realize two neuronal networks forming multiple sets of one-to-one neuron interconnections in the designed microchannels. Electrical stimulation technology is used to electrically stimulate the input end of the microchannel, which affects the discharge of the neurons at the input end. Since the neurons at both ends create synaptic connections in the microchannel, the signals from the input end neurons will be transmitted to the output end neurons. , the neurons at the output end produce different responses according to the different information transmitted. Therefore, we construct a one-to-one control unit with certain logical functions at the neuronal level. By changing the electrical stimulation parameters and culturing cell types, we can make the controlled unit have functions similar to electronic NOT gate logic devices in vitro. Function. This invention makes it possible to develop advanced functions of neuron networks in vitro, thereby promoting related research work such as in vitro development of advanced brain functions.
为实现这一目的，本发明采用如下技术方案：To achieve this goal, the present invention adopts the following technical solutions:
一种集成微流控、微电极阵列的神经元非门逻辑功能芯片，所述芯片包括两层，第一层微电极阵列芯片包括：绝缘基底、检测电极阵列、刺激电极、对电极、电极引线、触点及表面绝缘层；第二层微流控芯片包括：细胞培养槽、微流道以及一组用于控制神经元定向生长的微沟道。所述微电极阵列芯片与微流控芯片通过离子体键合进行封装。细胞培养槽的数量为4个。A chip with integrated microfluidic and microelectrode array neuron NOT gate logic functions. The chip includes two layers. The first layer of the microelectrode array chip includes: an insulating substrate, a detection electrode array, a stimulation electrode, a counter electrode, and an electrode lead. , contacts and surface insulation layer; the second layer of microfluidic chip includes: cell culture tank, microfluidic channel and a set of microchannels used to control the directional growth of neurons. The microelectrode array chip and the microfluidic chip are packaged through plasma bonding. The number of cell culture tanks is 4.
所述绝缘基底是整个微电极阵列芯片的载体；检测电极阵列分三组，分别位于微沟道的输入端、输出端和中央；刺激电极位于输入端检测电极的周围；并且检测电极阵列周围设有对电极；对电极、刺激电极与检测电极阵列均通过引线延伸并连接到绝缘基底外围的触点；所有引线表面均覆盖有绝缘层。微流控芯片中的细胞培养槽用于培养细胞；微流道连接细胞培养槽和微沟道；微沟道限制神经细胞的胞体通过并引导轴突定向生长。微电极阵列芯片与微流控芯片通过键合的方式固定封装，形成一个能引导神经细胞定向生长并实现一定逻辑功能的新型芯片。The insulating substrate is the carrier of the entire microelectrode array chip; the detection electrode array is divided into three groups, respectively located at the input end, output end and center of the microchannel; the stimulation electrode is located around the input end detection electrode; and the detection electrode array is surrounded by There is a counter electrode; the counter electrode, stimulation electrode and detection electrode array are all extended through leads and connected to contacts on the periphery of the insulating base; the surfaces of all leads are covered with an insulating layer. The cell culture tank in the microfluidic chip is used to culture cells; the microfluidic channel connects the cell culture tank and the microchannel; the microchannel restricts the passage of the cell bodies of nerve cells and guides the directional growth of axons. The microelectrode array chip and the microfluidic chip are fixed and packaged through bonding to form a new chip that can guide the directional growth of nerve cells and achieve certain logical functions.
所述的一种集成微流控、微电极阵列的神经元非门逻辑功能芯片，所述绝缘基底的材料选用石英玻璃、聚氯乙烯或聚碳酸酯其中之一；绝缘基底边长为20-50mm,厚度为1-5mm。In the neuron NOT gate logic chip integrating microfluidics and microelectrode arrays, the material of the insulating substrate is selected from one of quartz glass, polyvinyl chloride or polycarbonate; the side length of the insulating substrate is 20- 50mm, thickness 1-5mm.
所述的一种集成微流控、微电极阵列的神经元非门逻辑功能芯片，所述检测电极阵列中的检测电极由45-108个圆形微电极构成，直径为10-30μm，微电极的间距为100-500μm可用于神经电生理信号；微电极阵列芯片有15-36对弧形刺激电极，环绕在输入端的检测电极上，可用于电刺激细胞实现神经元放电的兴奋或者抑制。The described neuron NOT gate logic chip integrates microfluidics and microelectrode arrays. The detection electrodes in the detection electrode array are composed of 45-108 circular microelectrodes with a diameter of 10-30 μm. The microelectrodes The spacing is 100-500 μm and can be used for neuroelectrophysiological signals; the microelectrode array chip has 15-36 pairs of arc-shaped stimulation electrodes, surrounding the detection electrodes at the input end, and can be used to electrically stimulate cells to excite or inhibit neuron discharge.
所述的一种集成微流控、微电极阵列的神经元非门逻辑功能芯片，所述对电极的数量为2-4个，用于提供参考电位并保持电位稳定。In the neuron NOT gate logic chip integrating microfluidics and microelectrode arrays, the number of counter electrodes is 2-4, which are used to provide a reference potential and maintain potential stability.
所述的一种集成微流控、微电极阵列的神经元非门逻辑功能芯片，所述微电极阵列芯片选用的导电薄膜材料是金、铂、氮化钛或铟锡氧化物其中之一；绝缘层所使用材料为生物兼容性好的有机或无机绝缘材料，为二氧化硅、氮化硅、氮氧硅、SU8、聚酰亚胺或聚对二甲苯其中之一。The neuron NOT gate logic chip integrating microfluidics and microelectrode array, the conductive film material selected for the microelectrode array chip is one of gold, platinum, titanium nitride or indium tin oxide; The material used in the insulating layer is an organic or inorganic insulating material with good biocompatibility, which is one of silicon dioxide, silicon nitride, silicon oxynitride, SU8, polyimide or parylene.
如上任一所述的一种集成微流控、微电极阵列的神经元非门逻辑功能芯片的制备方法，其包括：制备第一层微电极阵列芯片和制备第二层微流控芯片；制备第一层微电极阵列芯片的方法，包括如下步骤：A method for preparing a neuron NOT gate logic functional chip integrating microfluidics and microelectrode arrays as described in any one of the above, which includes: preparing a first layer of microelectrode array chip and preparing a second layer of microfluidic chip; preparing The method for the first layer of microelectrode array chip includes the following steps:
1)在经过清洗过的绝缘基底上旋涂一层光刻胶，厚度大于拟溅射导电薄膜的三倍，光刻显影后形成检测电极阵列、刺激电极、对电极、引线和触点的图案；1) Spin-coat a layer of photoresist on the cleaned insulating substrate with a thickness greater than three times that of the conductive film to be sputtered. After photolithography and development, a pattern of detection electrode array, stimulation electrode, counter electrode, leads and contacts is formed. ;
2)在光刻胶图案表面溅射一层厚度250nm-500nm的导电薄膜，可选地在所述在光刻胶图案表面溅射一层厚度250nm-500nm的导电薄膜之前预先溅射10nm-50nm的Cr或Ti种子层，以增加导电薄膜层与基底的粘附性；2) Sputter a layer of conductive film with a thickness of 250nm-500nm on the surface of the photoresist pattern. Optionally, pre-sputter 10nm-50nm before sputtering a layer of conductive film with a thickness of 250nm-500nm on the surface of the photoresist pattern. Cr or Ti seed layer to increase the adhesion between the conductive film layer and the substrate;
3)采用剥离工艺去除多余导薄膜层，留下所需电极、引线及触点；3) Use a stripping process to remove the excess conductive film layer, leaving the required electrodes, leads and contacts;
4)通过等离子体增强化学气相沉积氧化硅和/或氮化硅，或旋涂SU8、聚酰亚胺、聚对二甲苯的方法，在制备好导电薄膜层的绝缘基底表面覆盖绝缘层，通过光刻或等离子束刻蚀的方法，暴露出检测电极阵列、电刺激电极、对电极及触点，保留所有引线表面覆盖的绝缘层；4) Cover the surface of the insulating substrate with the prepared conductive film layer with an insulating layer through plasma-enhanced chemical vapor deposition of silicon oxide and/or silicon nitride, or spin coating of SU8, polyimide, or parylene. Photolithography or plasma beam etching is used to expose the detection electrode array, electrical stimulation electrode, counter electrode and contacts, while retaining the insulating layer covering the surface of all leads;
5)在所述对电极表面，采用光刻、溅射、剥离的工艺，制备厚度200-500nm的铂金属薄膜层，若步骤2)中微电极导电薄膜已选用铂，则可以省略本步骤；5) On the surface of the counter electrode, use photolithography, sputtering, and peeling processes to prepare a platinum metal film layer with a thickness of 200-500 nm. If platinum has been selected for the microelectrode conductive film in step 2), this step can be omitted;
6)通过电化学沉积或物理滴涂、吸附的方法，在设定不同功能的微电极表面修饰纳米金颗粒、纳米铂黑和碳纳米管等纳米材料。6) Modify nanomaterials such as gold nanoparticles, nanoplatinum black, and carbon nanotubes on the surface of microelectrodes with different functions through electrochemical deposition or physical drop coating and adsorption.
所述的一种集成微流控、微电极阵列的神经元非门逻辑功能芯片，所述第二层微流控芯片由PDMS(聚二甲基硅氧烷)或PMMA(聚甲基丙烯酸甲酯)倒入SU8光刻胶制作的母模中制成。Described is a neuron NOT gate logic chip integrating microfluidics and microelectrode arrays. The second layer of the microfluidic chip is made of PDMS (polydimethylsiloxane) or PMMA (polymethacrylate). ester) is poured into a master mold made of SU8 photoresist.
所述制备第二层微流控芯片的方法，包括如下步骤：The method for preparing a second layer microfluidic chip includes the following steps:
1)母模制作1) Master mold production
A.在经过清洗过的硅片上旋涂光刻胶，厚度为5-10μm，长度为400-900μm，光刻显影后露出用于细胞定向生长微沟道；A. Spin-coat photoresist on the cleaned silicon wafer with a thickness of 5-10 μm and a length of 400-900 μm. After photolithography and development, micro-channels for directional cell growth are exposed;
B.在之前工艺后的硅片上旋涂光刻胶，厚度为50-100μm，光刻显影后露出用于神经细胞生长流动的微流道；B. Spin-coat photoresist on the silicon wafer after the previous process, with a thickness of 50-100 μm. After photolithography and development, the microfluidic channels for the growth and flow of nerve cells are exposed;
2)制造微流控器件2) Fabrication of microfluidic devices
C.将PDMS预聚物和催化剂混合5-10分钟，并将其倒入母模中；C. Mix the PDMS prepolymer and catalyst for 5-10 minutes and pour it into the master mold;
D.去除残留在母模中图案周围的气泡；D. Remove the bubbles remaining around the pattern in the master mold;
E.将PDMS进行固化；E. Curing PDMS;
F.将微流控器件从母模中分离，并用打孔器在微流控器件中制作出细胞培养槽。F. Separate the microfluidic device from the master mold, and use a hole punch to create a cell culture tank in the microfluidic device.
如上所述的一种集成微流控、微电极阵列的神经元非门逻辑功能芯片的制备方法，还包括如下步骤：将制得的微电极阵列芯片与制得的微流控芯片通过离子体键合进行封装。The above-mentioned method for preparing a neuron NOT gate logic chip integrating microfluidics and microelectrode arrays also includes the following steps: passing the prepared microelectrode array chip and the prepared microfluidic chip through ion plasma Bonding for encapsulation.
所述的一种集成微流控、微电极阵列的神经元非门逻辑功能芯片，所述芯片可以通过电刺激电极组刺激微沟道一端的神经元，使得另一端神经元产生与之相应的电生理信号的相应。The neuron NOT gate logic chip integrated with microfluidics and microelectrode array can stimulate the neurons at one end of the microchannel through the electrical stimulation electrode group, causing the neurons at the other end to generate corresponding signals. Correspondence of electrophysiological signals.
所述的一种集成微流控、微电极阵列的神经元非门逻辑功能芯片，刺激神经元的电脉冲有兴奋性刺激与抑制性刺激两种，兴奋性刺激采用频率低于5Hz、幅度小于0.2V的低频双极性脉冲波，抑制性刺激采用频率20-100Hz、幅度小于0.2V的高频双极性脉冲波。The described neuron NOT gate logic chip integrating microfluidics and microelectrode arrays has two types of electrical pulses to stimulate neurons: excitatory stimulation and inhibitory stimulation. The excitatory stimulation adopts a frequency lower than 5Hz and an amplitude less than A low-frequency bipolar pulse wave of 0.2V, and a high-frequency bipolar pulse wave with a frequency of 20-100Hz and an amplitude less than 0.2V are used for inhibitory stimulation.
所述的一种集成微流控、微电极阵列的神经元非门逻辑功能芯片，在微沟道输入端培养兴奋性神经元，在微沟道的输出端培养抑制性神经元。对输入端施加兴奋性电刺激，输出端抑制性神经元接受上级电信号激发神经元的抑制性信号；同理，在输入端施加抑制性电刺激，输出端会产生兴奋性信号。我们将兴奋性电刺激看作“1”，抑制性电刺激看作“0”；兴奋性输出看作“1”，抑制性输出看作“0”。由此我们用神经元上构建了一个类似非门的基础单元。The neuron NOT gate logic chip integrated with microfluidics and microelectrode arrays cultivates excitatory neurons at the input end of the microchannel and cultivates inhibitory neurons at the output end of the microchannel. Applying excitatory electrical stimulation to the input end, the inhibitory neurons at the output end receive inhibitory signals from superior electrical signals to excite the neurons; similarly, applying inhibitory electrical stimulation to the input end will produce excitatory signals at the output end. We regard excitatory electrical stimulation as "1" and inhibitory electrical stimulation as "0"; excitatory output as "1" and inhibitory output as "0". From this, we built a basic unit similar to the NOT gate using neurons.
本发明的目的是提供一种集成微流控、微电极阵列的神经元非门逻辑功能芯片与制备方法，通过集成了微电极阵列与微流控芯片实现两个不同神经元网络在设计的微沟道中形成多组一对一的神经元互连，使用电刺激技术刺激一端神经元网络，让另一端随着输入产生类似非门的输出。该芯片与现有的离体细胞电生理检测芯片相比，该芯片具有可控制、精准化、高通量、使用方便等优点，并且能够实现神经网络的高级功能的初步开发。The purpose of the present invention is to provide a neuron NOT gate logic functional chip integrating microfluidics and microelectrode arrays and a preparation method. By integrating the microelectrode array and the microfluidic chip, two different neuron networks can be realized in the designed microstructure. Multiple sets of one-to-one neuron interconnections are formed in the channel, and electrical stimulation technology is used to stimulate the neuron network at one end, allowing the other end to produce an output similar to a NOT gate in response to the input. Compared with existing in vitro cell electrophysiological detection chips, this chip has the advantages of controllability, precision, high-throughput, and ease of use, and can realize the preliminary development of advanced functions of neural networks.
附图说明Description of drawings
图1为一种集成微流控、微电极阵列的神经元非门逻辑功能芯片结构示意图；Figure 1 is a schematic structural diagram of a neuron NOT gate logic chip integrating microfluidics and microelectrode arrays;
图2为本发明第一层芯片微电极阵列部分的结构示意图；Figure 2 is a schematic structural diagram of the microelectrode array part of the first layer chip of the present invention;
图3为本发明第二层芯片微流控芯片部分的结构示意图；Figure 3 is a schematic structural diagram of the microfluidic chip part of the second layer chip of the present invention;
图4为本发明微电极阵列芯片制备工艺的流程图；Figure 4 is a flow chart of the microelectrode array chip preparation process of the present invention;
图4a为在玻璃基底表面旋涂光刻胶并曝光；Figure 4a shows photoresist spin-coated on the surface of a glass substrate and exposed;
图4b为光刻胶显影形成溅射掩膜；Figure 4b shows the development of photoresist to form a sputtering mask;
图4c为溅射Cr/Pt导电薄膜层；Figure 4c shows the sputtered Cr/Pt conductive film layer;
图4d为采用lift-off工艺形成导电层图形留下所需微电极、引线及触点；Figure 4d shows the use of lift-off process to form the conductive layer pattern leaving the required microelectrodes, leads and contacts;
图4e为PECVD沉积SiO2(300nm)/Si3N4(500nm)绝缘层Figure 4e shows the SiO2 (300nm)/Si3N4 (500nm) insulation layer deposited by PECVD.
图4f为再次用光刻工艺暴露出微电极和触点上方的绝缘层；Figure 4f shows the photolithography process again exposing the insulating layer above the microelectrodes and contacts;
图4g为通过CHF3反应离子刻蚀(RIE)选择性地去除微电极和触点上的绝缘层；Figure 4g shows the selective removal of the insulating layer on the microelectrodes and contacts through CHF3 reactive ion etching (RIE);
图5为本发明微流控器件部分制备工艺的流程图；Figure 5 is a flow chart of part of the preparation process of the microfluidic device of the present invention;
图5a为在洁净硅片上旋涂SU8 5光刻胶并进行曝光；Figure 5a shows SU8 5 photoresist being spin-coated on a clean silicon wafer and exposed;
图5b为对曝光后的SU 8 5光刻胶进行显影；Figure 5b shows the development of the exposed SU 8 5 photoresist;
图5c为在第一次光刻后的硅片上旋涂SU8 50光刻胶并进行曝光；Figure 5c shows the SU8 50 photoresist spin-coated on the silicon wafer after the first photolithography and exposed;
图5d为对曝光后的SU 8 50光刻胶进行显影；Figure 5d shows the development of the exposed SU 8 50 photoresist;
图5e为把PDMS倒入母模中进行塑模；Figure 5e shows pouring PDMS into the master mold for molding;
图5f为PDMS微流控器件从母模中剥离；Figure 5f shows the PDMS microfluidic device peeled off from the master mold;
图6为两级神经元实现非门逻辑功能原理图。Figure 6 is a schematic diagram of a two-level neuron implementing the NOT gate logic function.
附图标号说明：Explanation of reference numbers:
a-微电极阵列芯片，b-微流控芯片；a-microelectrode array chip, b-microfluidic chip;
1-绝缘基底、2-检测电极阵列、3-刺激电极、4-对电极、5-引线、6-触点和7-绝缘层；1-insulating base, 2-detection electrode array, 3-stimulation electrode, 4-counter electrode, 5-lead, 6-contact and 7-insulation layer;
8-细胞培养槽、9-微流道和10-微沟道。8-cell culture tank, 9-microfluidic channel and 10-microchannel.
具体实施方式Detailed ways
以下结合附图和具体的实施实例对本发明的技术方案做进一步描述。以下实施实例不构成对本发明的限定。The technical solution of the present invention will be further described below with reference to the accompanying drawings and specific implementation examples. The following implementation examples do not constitute limitations to the present invention.
图1为所示本发明提供的一种集成微流控、微电极阵列的神经元非门逻辑功能芯片。该芯片由两层芯片构成微电极阵列芯片a与微流控芯片b；Figure 1 shows a neuron NOT gate logic chip integrated with microfluidics and microelectrode arrays provided by the present invention. The chip consists of two layers of chips: microelectrode array chip a and microfluidic chip b;
图2为本发明微电极阵列芯片由绝缘基底1、检测电极阵列2、刺激电极3，对电极4、引线5、触点6和绝缘层7构成。Figure 2 shows the microelectrode array chip of the present invention, which is composed of an insulating substrate 1, a detection electrode array 2, a stimulation electrode 3, a counter electrode 4, a lead 5, a contact 6 and an insulating layer 7.
图3为所示的本发明微流控器件部分，它由细胞培养槽8、微流道9和微沟道10构成。Figure 3 shows the microfluidic device part of the present invention, which is composed of a cell culture tank 8, a microfluidic channel 9 and a microchannel 10.
如图1-3所示，一种集成微流控、微电极阵列的神经元非门逻辑功能芯片，所述芯片包括两层，第一层微电极阵列芯片a包括：绝缘基底1、检测电极阵列2、刺激电极3、对电极4、电极引线5、触点6及表面绝缘层7；第二层微流控芯片b包括：4个细胞培养槽8、微流道9以及一组用于控制神经元定向生长的微沟道10。所述微电极阵列芯片a与微流控芯片b通过离子体键合进行封装。所述微电极阵列芯片a选用的导电薄膜材料是金、铂、氮化钛或铟锡氧化物其中之一。绝缘层7所使用材料为生物兼容性好的有机或无机绝缘材料，为二氧化硅、氮化硅、氮氧硅、SU8、聚酰亚胺或聚对二甲苯其中之一。As shown in Figure 1-3, a neuron NOT gate logic chip integrating microfluidics and microelectrode array. The chip includes two layers. The first layer of microelectrode array chip a includes: insulating substrate 1, detection electrode Array 2, stimulation electrode 3, counter electrode 4, electrode leads 5, contacts 6 and surface insulation layer 7; the second layer of microfluidic chip b includes: 4 cell culture tanks 8, microfluidic channels 9 and a set of Microchannels that control the directional growth of neurons10. The microelectrode array chip a and the microfluidic chip b are packaged through plasma bonding. The conductive film material selected for the microelectrode array chip a is one of gold, platinum, titanium nitride or indium tin oxide. The material used in the insulating layer 7 is an organic or inorganic insulating material with good biocompatibility, which is one of silicon dioxide, silicon nitride, silicon oxynitride, SU8, polyimide or parylene.
绝缘基底1为整个芯片的载体，基底的材料采用的是石英玻璃，绝缘基底的长×宽为50mm×50mm，厚度约为1mm。The insulating substrate 1 is the carrier of the entire chip. The material of the substrate is quartz glass. The length × width of the insulating substrate is 50 mm × 50 mm, and the thickness is about 1 mm.
所述的一种集成微流控、微电极阵列的神经元非门逻辑功能芯片，其微电极阵列部分的检测电极位点沿着基底的中心展开分布；检测电极一共有3组，分别位于微沟道10的输入端、输出端和中央，每组15个，其直径为10μm，间距为200μm，可用于神经电生理信号；刺激电极环绕在输入端一组检测电极左右，其间隔为200μm。刺激电极组中的刺激电极3由15对弧形构成，环绕在输入端的检测电极上，可用于电刺激细胞实现神经元放电的兴奋或者抑制。检测电极阵列2周围设有一对对电极4，用于提供参考电位并保持电位稳定。对电极4、刺激电极3与检测电极阵列2均通过引线5延伸并连接到绝缘基底外围的触点6；所有引线5表面均覆盖有绝缘层7。In the described neuron NOT gate logic chip integrated with microfluidics and microelectrode array, the detection electrode sites of the microelectrode array part are distributed along the center of the substrate; there are three groups of detection electrodes, each located on the microelectrode array. The input end, output end and center of the channel 10 are 15 in each group, with a diameter of 10 μm and a spacing of 200 μm, which can be used for neuroelectrophysiological signals; the stimulation electrodes surround a group of detection electrodes at the input end, and the spacing is 200 μm. The stimulation electrode 3 in the stimulation electrode group is composed of 15 pairs of arcs, surrounding the detection electrode at the input end, and can be used to electrically stimulate cells to excite or inhibit neuron discharge. A pair of counter electrodes 4 are provided around the detection electrode array 2 for providing a reference potential and maintaining potential stability. The counter electrode 4, the stimulation electrode 3 and the detection electrode array 2 are all extended through leads 5 and connected to the contacts 6 on the periphery of the insulating base; the surfaces of all leads 5 are covered with an insulating layer 7.
微流控芯片b中的4个细胞培养槽8用于培养细胞；微流道9连接细胞培养槽8和微沟道10；微沟道10限制神经细胞的胞体通过并引导轴突定向生长。微电极阵列芯片a与微流控芯片b通过键合的方式固定封装，形成一个能引导神经细胞定向生长并实现一定逻辑功能的新型芯片。The four cell culture tanks 8 in the microfluidic chip b are used to culture cells; the microfluidic channels 9 connect the cell culture tanks 8 and the microchannels 10; the microchannels 10 limit the passage of the cell bodies of nerve cells and guide the directional growth of axons. The microelectrode array chip a and the microfluidic chip b are fixed and packaged by bonding to form a new chip that can guide the directional growth of nerve cells and achieve certain logical functions.
所述的一种集成微流控、微电极阵列的神经元非门逻辑功能芯片的第一层微电极阵列部分的制备方法包括以下步骤(如图4)：The method for preparing the first layer of the microelectrode array part of a neuron NOT gate logic functional chip integrating microfluidics and microelectrode arrays includes the following steps (as shown in Figure 4):
a)采用煮沸的浓硫酸溶液清洗玻璃片10-20分钟，利用其强氧化性去除基底上残留的有机杂质或无机杂质；a) Use boiled concentrated sulfuric acid solution to clean the glass piece for 10-20 minutes, and use its strong oxidizing properties to remove residual organic or inorganic impurities on the substrate;
b)在经过清洗过的玻璃片上旋涂一层光刻胶，厚度大于拟溅射导电薄膜的三倍，采用光刻工艺(正性光刻胶AZ1500)对检测电极，电刺激电极、对电极，引线和触点进行图案化；b) Spin-coat a layer of photoresist on the cleaned glass sheet, with a thickness greater than three times that of the conductive film to be sputtered, and use photolithography technology (positive photoresist AZ1500) to cover the detection electrode, electrical stimulation electrode, and counter electrode , leads and contacts are patterned;
c)在光刻胶图形表面先溅射50nm的Cr种子层，以增加导电薄膜层与基底的粘附性，再溅射一层250nm的Pt层；c) First sputter a 50nm Cr seed layer on the surface of the photoresist pattern to increase the adhesion between the conductive film layer and the substrate, and then sputter a 250nm Pt layer;
d)采用剥离工艺去除多余Pt层，留下所需的检测电极，电刺激电极、对电极，引线和触点；d) Use a stripping process to remove the excess Pt layer, leaving the required detection electrodes, electrical stimulation electrodes, counter electrodes, leads and contacts;
e)采用等离子体增强化学气相沉积(PECVD，300℃)沉积SiO2(300nm)/Si3N4(500nm)绝缘层；e) Use plasma enhanced chemical vapor deposition (PECVD, 300°C) to deposit SiO2 (300nm)/Si3 N4 (500nm) insulation layer;
f)再次用光刻工艺暴露出检测电极阵列、刺激电极、对电极和触点上方的绝缘层，通过CHF3反应离子刻蚀(RIE)选择性地去除微电极和触点上的绝缘层；保留所有引线5表面覆盖的绝缘层；f) Use the photolithography process again to expose the insulating layer above the detection electrode array, stimulation electrode, counter electrode and contacts, and selectively remove the insulating layer on the microelectrodes and contacts through CHF3 reactive ion etching (RIE); Keep the insulation layer covering the surface of all leads 5;
g)使用丙酮去除微电极阵列芯片上残留的光刻胶，并用去离子水冲洗干净。g) Use acetone to remove the remaining photoresist on the microelectrode array chip and rinse it with deionized water.
h)采用电化学计时电流法在微电极阵列检测电极上电镀上一层铂纳米颗粒，提升检测电极的电学特性。h) Use electrochemical chronoamperometry to electroplat a layer of platinum nanoparticles on the microelectrode array detection electrode to improve the electrical characteristics of the detection electrode.
所述的一种集成微流控、微电极阵列的神经元非门逻辑功能芯片的第二层微流控芯片的制备方法包括以下步骤(如图5)：The preparation method of the second layer microfluidic chip of the neuron NOT gate logic function chip integrating microfluidics and microelectrode arrays includes the following steps (as shown in Figure 5):
1)母模的制作1) Production of master mold
a)在经过清洗过硅片上旋涂上一层型号为SU85的负性光刻胶，厚度为5μm，长度为550μm；a) Spin-coat a layer of SU85 negative photoresist on the cleaned silicon wafer, with a thickness of 5 μm and a length of 550 μm;
b)对光刻胶显影后形成第一块掩模版上的图形，露出用于细胞定向生长微沟道10；b) Develop the photoresist to form a pattern on the first mask, exposing microchannels 10 for directional cell growth;
c)第一次光刻后的硅片上旋涂一层型号为SU850的光刻胶，厚度为100μm；c) After the first photolithography, a layer of SU850 photoresist is spin-coated on the silicon wafer with a thickness of 100 μm;
d)对光刻胶显影后形成第二块掩膜版上的图形，露出用于神经细胞生长流动的微流道9，通过光刻制作出为流控器件的母模。d) Develop the photoresist to form a pattern on the second mask, exposing the microfluidic channel 9 for the growth and flow of nerve cells, and create a master mold for the fluidic device through photolithography.
2)PDMS铸模2) PDMS mold
e)将道康宁公司的Sylgard 184型PDMS预聚物与催化剂按照重量比为10：1混合，并充分混合5-10分钟，加入承放母模的器皿中进行铸模。在真空干燥器中用氮气去除残留在母模中图案周围的气泡；在70℃烤箱中将PDMS进行固化。e) Mix Dow Corning's Sylgard 184 PDMS prepolymer and catalyst at a weight ratio of 10:1, mix thoroughly for 5-10 minutes, and add it to a container holding the master mold for casting. Use nitrogen in a vacuum desiccator to remove bubbles remaining around the pattern in the master mold; cure the PDMS in a 70°C oven.
f)当PDMS完全交联或固化时(PDMS混合物将变为透明)，用刀片将PDMS微流控器件从母模上脱离，并用打孔器在器件上打出用于培养细胞所用的培养槽。f) When the PDMS is completely cross-linked or cured (the PDMS mixture will become transparent), use a blade to separate the PDMS microfluidic device from the master mold, and use a hole punch to create a culture tank for culturing cells on the device.
一种集成微流控、微电极阵列的神经元非门逻辑功能芯片的微电极阵列层和微流控芯片层通过等离子体刻蚀活化表面，然后进行贴合，形成整个芯片。The microelectrode array layer and microfluidic chip layer of a neuron NOT gate logic functional chip integrating microfluidics and microelectrode arrays are activated by plasma etching on the surface, and then laminated to form the entire chip.
图6为所述的一种集成微流控、微电极阵列的神经元非门逻辑功能芯片的在神经元层面实现逻辑非门功能的原理图。Figure 6 is a schematic diagram of the neuron NOT gate logic function chip integrated with microfluidics and microelectrode arrays, which realizes the logic NOT gate function at the neuron level.
实施例1：Example 1:
采用上述集成微流控、微电极阵列的神经元非门逻辑功能芯片检测原代皮层神经元电生理信号The above-mentioned neuron NOT gate logic chip integrated with microfluidics and microelectrode array is used to detect electrophysiological signals of primary cortical neurons.
(1)芯片上培养原代皮层神经元的步骤如下：(1) The steps for culturing primary cortical neurons on the chip are as follows:
a)将微电极阵列芯片无菌化处理，采用层粘蛋白(laminin)包被芯片；a) Sterilize the microelectrode array chip and coat the chip with laminin;
b)每2-3天替换芯片上的细胞培养液，持续培养7—14天，并对培养的神经元进行荧光染色，培养5天以后能够看到神经元向微沟道定向生长。b) Replace the cell culture medium on the chip every 2-3 days, continue to culture for 7-14 days, and perform fluorescent staining on the cultured neurons. After 5 days of culture, you can see the directional growth of neurons toward the microchannel.
(2)检测神经细胞的电生理信号(2) Detect electrophysiological signals of nerve cells
a)将培养了原代神经元的芯片与接口电路相连并接入Cerebus公司的电生理信号检测仪器中；a) Connect the chip cultured with primary neurons to the interface circuit and connect it to the electrophysiological signal detection instrument of Cerebus;
b)向培养微电极阵列加入谷氨酸刺激神经细胞放电，并且记录神经细胞的放电状况。b) Add glutamate to the cultured microelectrode array to stimulate the discharge of nerve cells, and record the discharge status of the nerve cells.
(3)电刺激芯片一端的神经元检测另一端的神经元的响应(3) Electrically stimulate the neurons at one end of the chip to detect the response of the neurons at the other end.
a)将培养了原代神经元的芯片与接口电路相连并接入Cerebus公司的电生理信号检测仪器中；a) Connect the chip cultured with primary neurons to the interface circuit and connect it to the electrophysiological signal detection instrument of Cerebus;
b)将Multichannel公司的电刺激仪器与芯片输入端的电刺激电极连接，分别施加高频电刺激与低频电刺激，并记录输出端神经元的放电状况。b) Connect Multichannel's electrical stimulation instrument to the electrical stimulation electrode at the input end of the chip, apply high-frequency electrical stimulation and low-frequency electrical stimulation respectively, and record the discharge status of the neurons at the output end.
本发明未详细阐述部分属于本领域技术人员的公知技术。以上所述的实施例仅是对本发明的优选实施方式进行描述，优选实施例并没有详尽叙述所有的细节，也不限制该发明仅为所述的具体实施方式。在不脱离本发明设计精神的前提下，本领域普通技术人员对本发明的技术方案做出的各种变形和改进，均应落入本发明权利要求书确定的保护范围内。The present invention does not elaborate on some of the well-known technologies belonging to those skilled in the art. The above-described embodiments only describe the preferred embodiments of the present invention. The preferred embodiments do not describe all the details in detail, nor do they limit the invention to the specific implementations described. Without departing from the design spirit of the present invention, various modifications and improvements made by those of ordinary skill in the art to the technical solution of the present invention shall fall within the protection scope determined by the claims of the present invention.
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| CN202111055880.9ACN113684133B (en) | 2021-09-09 | 2021-09-09 | A neuron NOT gate logic functional chip integrating microfluidics and microelectrode array and its preparation method |
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| CN202111055880.9AActiveCN113684133B (en) | 2021-09-09 | 2021-09-09 | A neuron NOT gate logic functional chip integrating microfluidics and microelectrode array and its preparation method |
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