CN113684133A

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Info

Publication number: CN113684133A
Application number: CN202111055880.9A
Authority: CN
Inventors: 徐世弘; 蔡新霞; 罗金平; 何恩慧; 张奎; 徐声伟; 宋轶琳
Original assignee: Aerospace Information Research Institute of CAS
Current assignee: Aerospace Information Research Institute of CAS
Priority date: 2021-09-09
Filing date: 2021-09-09
Publication date: 2021-11-23
Anticipated expiration: 2041-09-09
Also published as: CN113684133B

Abstract

Translated fromChinese

本发明公开了一种集成微流控、微电极阵列的神经元非门逻辑功能芯片及其制备方法，涉及传感器技术与电刺激调控技术。该芯片系统由两层子芯片构成，二者均由MEMS工艺加工制备。第一层子芯片为用于神经元电生理调控检测的微电极阵列芯片，包括检测微电极阵列、刺激电极等元件；第二层子芯片为用于神经元定向培养的微流控芯片，包括细胞培养槽、微流道以及微沟道。该芯片以微沟道实现神经元之间定向互连，并通过刺激电极训练输入端神经元使其放电变化，从而实现微沟道输入端神经元对输出端神经元放电频率的控制，进而在神经元层面上构建一对一有一定逻辑功能的控制单元。本发明芯片功能集成化，具备定向培养神经元的功能和同时空调控检测的能力。

The invention discloses a neuron NOT gate logic function chip integrating microfluidics and microelectrode arrays and a preparation method thereof, and relates to sensor technology and electrical stimulation regulation technology. The chip system consists of two layers of sub-chips, both of which are fabricated by MEMS technology. The first layer of sub-chips is a microelectrode array chip used for neuron electrophysiological regulation and detection, including detection microelectrode arrays, stimulation electrodes and other components; the second layer of sub-chips is a microfluidic chip used for neuron directional culture, including Cell culture tanks, microfluidics and microchannels. The chip realizes directional interconnection between neurons with micro-channels, and trains the neurons at the input end to change their discharge by stimulating electrodes, so as to realize the control of the firing frequency of neurons at the input end of the micro-channel to the neurons at the output end, and then in At the neuron level, a one-to-one control unit with a certain logic function is constructed. The chip of the invention has integrated functions, and has the function of directionally cultivating neurons and the ability of air-conditioning control and detection at the same time.

Description

Neuron NOT-gate logic function chip integrating micro-fluidic and microelectrode array and preparation method thereof

Technical Field

The invention relates to the micro-machining field of a micro-electro-mechanical system (MEMS) of a biosensor, the electrical stimulation regulation field and the nerve cell compartmentalization culture field, in particular to a neuron NOT gate logic function chip integrating micro-flow control and a microelectrode array and a preparation method thereof.

Background

Human beings have the most complex and delicate material structure in the world-the brain with thinking ability. Through the daily operation of the brain, the human can easily complete the advanced and complex work which is difficult to complete by the artificial intelligence at present. The mysterious process for revealing the advanced functions of the brain is not only one of the top puzzles of natural science, but also is a significant challenge faced by the current neuroscience and is a significant barrier for breaking through the current artificial intelligence development.

All of the high-level functions of the brain are implemented without information transfer, processing, and storage. The brain has many advanced functions such as perception, consciousness, behavior, memory and learning. The brain has such a complicated function because there are hundreds of billions of nerves in the brain, these neurons form an intricate neural network through synaptic connections, and different neural networks are connected with each other in an interlaced manner, thereby forming a human brain with a processing capability stronger than that of a modern computer. Whether simple knee response or complex human memory, is closely related to information transmission in different brain areas in the brain, where information transmission by neural networks is accomplished through nerve cell impulse discharges and neurotransmitter transmission.

The microelectrode array (MEA) is used as an interface tool between a neural network and an electronic system, which is helpful for scientists to deeply understand the dynamics of the neural network and the reaction of biological substances, thereby providing possibility for the scientists to disclose the function of the neural network. The microfluidic technology is widely used for customized in vitro culture of specific neural networks due to the characteristics of precise control, microscale control and the like. The combination of microelectrode array technology and microfluidic technology makes it possible to develop advanced functions of neural networks in vitro.

Many studies have shown that external electrical stimulation can stimulate the learning, memory, etc. functions of neuronal networks. The function of the neuronal network can be better exploited in vitro by external electrical stimulation.

Disclosure of Invention

The invention aims to provide a neuron NOT gate logic function chip integrating micro-fluidic and microelectrode arrays and a preparation method thereof. The chip integrates a microelectrode array and a microfluidic chip to realize that two neuron networks form a plurality of groups of one-to-one neuron interconnection in a designed microchannel. The electrical stimulation technology is used for electrically stimulating the input end of the micro-channel to influence the discharge condition of the neuron at the input end, because the neurons at two ends generate synaptic connections in the micro-channel, the signal of the neuron at the input end can be transmitted to the neuron at the output end, and the neuron at the output end generates different correspondences along with different transmission information. Therefore, a control unit with certain logic function is constructed on a neuron level, and the control unit can have the function similar to an electronic NOT gate logic device in vitro through the change of electrical stimulation parameters and the difference of cultured cell types. The invention makes it possible to develop the advanced function of the neuron network in vitro, thereby promoting the research work related to the advanced function of the brain in vitro development and the like.

In order to realize the purpose, the invention adopts the following technical scheme:

a neuron NOT gate logic function chip integrating micro-fluidic and microelectrode array, the chip comprises two layers, and a first layer of microelectrode array chip comprises: the device comprises an insulating substrate, a detection electrode array, a stimulation electrode, a counter electrode, an electrode lead, a contact and a surface insulating layer; the second layer of microfluidic chips comprises: cell culture groove, micro-channel and a set of microchannel that is used for controlling neuron directional growth. And the microelectrode array chip and the microfluidic chip are packaged by plasma bonding. The number of cell culture chambers was 4.

The insulating substrate is a carrier of the whole microelectrode array chip; the detection electrode arrays are divided into three groups and are respectively positioned at the input end, the output end and the center of the microchannel; the stimulating electrode is positioned around the input end detection electrode; and a counter electrode is arranged around the detection electrode array; the counter electrode, the stimulating electrode and the detection electrode array extend through leads and are connected to contacts on the periphery of the insulating substrate; all lead surfaces are covered with an insulating layer. The cell culture groove in the microfluidic chip is used for culturing cells; the micro flow channel is connected with the cell culture tank and the micro channel; the microchannels restrict the passage of the soma of the nerve cell and guide the axon to grow directionally. The microelectrode array chip and the microfluidic chip are fixedly packaged in a bonding mode to form a novel chip which can guide the directional growth of nerve cells and realize certain logic functions.

According to the neuron NOT gate logic function chip integrating the microfluidic and microelectrode array, the insulating substrate is made of one of quartz glass, polyvinyl chloride or polycarbonate; the side length of the insulating substrate is 20-50mm, and the thickness is 1-5 mm.

The neuron NOT gate logic function chip integrating the micro-fluidic and microelectrode array is characterized in that a detection electrode in the detection electrode array is composed of 45-108 circular microelectrodes, the diameter of the detection electrode array is 10-30 mu m, and the distance between every two microelectrodes is 100-500 mu m, so that the detection electrode array can be used for neuroelectrophysiological signals; the microelectrode array chip has 15-36 pairs of arc stimulating electrodes surrounding the detecting electrodes at the input end, and can be used for electrically stimulating cells to realize excitation or inhibition of neuron discharge.

The number of the counter electrodes is 2-4, and the counter electrodes are used for providing reference potential and keeping the potential stable.

The neuron NOT gate logic function chip integrating micro-fluidic and microelectrode array is characterized in that the microelectrode array chip is made of one of gold, platinum, titanium nitride or indium tin oxide; the insulating layer is made of organic or inorganic insulating material with good biocompatibility, and is one of silicon dioxide, silicon nitride, silicon oxynitride, SU8, polyimide or parylene.

The preparation method of the neuron NOT gate logic function chip integrating the microfluidics and the microelectrode array comprises the following steps: preparing a first layer of microelectrode array chip and a second layer of microfluidic chip; the method for preparing the first layer microelectrode array chip comprises the following steps:

1) spin-coating a layer of photoresist on the cleaned insulating substrate, wherein the thickness of the photoresist is more than three times of that of the conductive film to be sputtered, and forming patterns of a detection electrode array, a stimulation electrode, a counter electrode, a lead and a contact after photoetching development;

2) sputtering a layer of conductive film with the thickness of 250nm-500nm on the surface of the photoresist pattern, optionally sputtering a Cr or Ti seed layer with the thickness of 10nm-50nm in advance before sputtering a layer of conductive film with the thickness of 250nm-500nm on the surface of the photoresist pattern so as to increase the adhesion of the conductive film layer and the substrate;

3) removing the redundant thin film layer by adopting a stripping process, and leaving the needed electrodes, leads and contacts;

4) covering an insulating layer on the surface of an insulating substrate with a prepared conductive film layer by using a method of plasma enhanced chemical vapor deposition of silicon oxide and/or silicon nitride or spin coating of SU8, polyimide and parylene, exposing a detection electrode array, an electrical stimulation electrode, a counter electrode and a contact by using a method of photoetching or plasma beam etching, and reserving the insulating layer covered on the surface of all leads;

5) preparing a platinum metal film layer with the thickness of 200-500nm on the surface of the counter electrode by adopting the processes of photoetching, sputtering and stripping, and if the microelectrode conductive film in the step 2) is made of platinum, the step can be omitted;

6) modifying nano materials such as nano gold particles, nano platinum black, carbon nano tubes and the like on the surface of a microelectrode with different functions by an electrochemical deposition or physical drop coating and adsorption method.

The second layer of micro-fluidic chip is made by pouring PDMS (polydimethylsiloxane) or PMMA (polymethyl methacrylate) into a master die made of SU8 photoresist.

The method for preparing the second layer of microfluidic chip comprises the following steps:

1) making female die

A. Spin-coating photoresist on the cleaned silicon wafer, wherein the thickness is 5-10 μm, the length is 400-900 μm, and the micro-channel for directional cell growth is exposed after photoetching development;

B. spin-coating photoresist on the silicon wafer after the previous process, wherein the thickness is 50-100 μm, and exposing a micro-channel for growth and flow of nerve cells after photoetching and development;

2) fabrication of microfluidic devices

C. Mixing the PDMS prepolymer and the catalyst for 5-10 minutes, and pouring the mixture into a master model;

D. removing bubbles remaining around the pattern in the master mold;

E. curing PDMS;

F. and separating the microfluidic device from the female die, and manufacturing a cell culture groove in the microfluidic device by using a puncher.

The preparation method of the neuron NOT gate logic function chip integrating the microfluidics and the microelectrode array further comprises the following steps: and packaging the prepared microelectrode array chip and the prepared microfluidic chip by plasma bonding.

The neuron NOT gate logic function chip integrating the microfluidic and microelectrode array can stimulate the neuron at one end of a microchannel through an electric stimulation electrode group, so that the neuron at the other end generates corresponding electrophysiological signals.

The neuron NOT gate logic function chip integrating the microfluidic and microelectrode array has two types of excitatory stimulation and inhibitory stimulation of electric pulses for stimulating neurons, wherein the excitatory stimulation adopts low-frequency bipolar pulse waves with the frequency lower than 5Hz and the amplitude lower than 0.2V, and the inhibitory stimulation adopts high-frequency bipolar pulse waves with the frequency of 20-100Hz and the amplitude lower than 0.2V.

The neuron NOT gate logic function chip integrating the microfluidic and microelectrode array is characterized in that excitatory neurons are cultured at the input end of a microchannel, and inhibitory neurons are cultured at the output end of the microchannel. Applying excitatory electrical stimulation to the input end, and receiving inhibitory signals of the upper electrical signal excitation neuron by the inhibitory neuron at the output end; similarly, an inhibitory electrical stimulus is applied to the input terminal, and an excitatory signal is generated at the output terminal. We consider excitatory electrical stimulation as a "1" and inhibitory electrical stimulation as a "0"; excitatory output is considered "1" and inhibitory output is considered "0". Therefore, a basic unit similar to a NOT gate is constructed on the neuron.

The invention aims to provide a neuron NOT gate logic function chip integrating micro-fluidic and micro-electrode arrays and a preparation method thereof. Compared with the existing in vitro cell electrophysiological detection chip, the chip has the advantages of controllability, accuracy, high flux, convenience in use and the like, and can realize the initial development of advanced functions of a neural network.

Drawings

FIG. 1 is a schematic diagram of a structure of a neuron NOT gate logic function chip integrating micro-fluidic and microelectrode array;

FIG. 2 is a schematic diagram showing the structure of a microelectrode array part of a first layer chip of the present invention;

FIG. 3 is a schematic structural diagram of a microfluidic chip portion of a second chip according to the present invention;

FIG. 4 is a flow chart showing a process for preparing a microelectrode array chip of the present invention;

FIG. 4a is a schematic view of spin-coating a photoresist on a glass substrate surface and exposing;

FIG. 4b illustrates photoresist development to form a sputter mask;

FIG. 4c is a sputtered Cr/Pt conductive film layer;

FIG. 4d illustrates patterning of the conductive layer using lift-off process to leave the desired microelectrodes, leads and contacts;

FIG. 4e is a PECVD deposition of SiO2(300nm)/Si3N4(500nm) insulating layer

FIG. 4f is a schematic view showing the exposure of the micro-electrodes and the insulating layer over the contacts again using a photolithography process;

FIG. 4g is a view showing the selective removal of insulating layers on micro-electrodes and contacts by CHF3 Reactive Ion Etching (RIE);

FIG. 5 is a flow chart of a partial fabrication process of a microfluidic device according to the present invention;

FIG. 5a is spin coating SU85 photoresist on a clean silicon wafer and exposing;

FIG. 5b is a development of the exposed SU85 photoresist;

FIG. 5c is the first time of photo-etching silicon wafer spin-coating SU850 photoresist and exposure;

FIG. 5d shows the exposed SU850 photoresist being developed;

FIG. 5e is a schematic view of PDMS being poured into the master for molding;

FIG. 5f shows the PDMS microfluidic device being peeled off from the master;

FIG. 6 is a functional diagram of two levels of neurons implementing the NOT gate logic.

The reference numbers illustrate:

a-microelectrode array chip, b-microfluidic chip;

1-an insulating substrate, 2-a detection electrode array, 3-a stimulation electrode, 4-a counter electrode, 5-a lead, 6-a contact and 7-an insulating layer;

8-cell culture tank, 9-micro channel and 10-micro channel.

Detailed Description

The technical solution of the present invention is further described below with reference to the accompanying drawings and specific embodiments. The following examples are not to be construed as limiting the invention.

FIG. 1 is a neuron NOT gate logic function chip integrating micro-fluidic and micro-electrode arrays provided by the invention. The chip comprises a microelectrode array chip a and a microfluidic chip b which are formed by two layers of chips;

FIG. 2 shows a microelectrode array chip of the present invention, which is composed of an insulatingsubstrate 1, a detectingelectrode array 2, a stimulatingelectrode 3, acounter electrode 4, alead 5, acontact 6 and an insulatinglayer 7.

FIG. 3 shows a part of a microfluidic device according to the present invention, which is composed of acell culture chamber 8, amicrochannel 9 and amicrochannel 10.

As shown in fig. 1-3, a micro-fluidic, micro-electrode array integrated neuron not gate logic function chip comprises two layers, wherein a first layer of micro-electrode array chip a comprises: the device comprises an insulatingsubstrate 1, adetection electrode array 2, astimulation electrode 3, acounter electrode 4, anelectrode lead 5, acontact 6 and asurface insulating layer 7; the second layer of microfluidic chip b comprises: 4cell culture tanks 8, amicro-channel 9 and a group ofmicro-channels 10 for controlling the directional growth of neurons. And the microelectrode array chip a and the microfluidic chip b are packaged by plasma bonding. The conductive film material selected by the microelectrode array chip a is one of gold, platinum, titanium nitride or indium tin oxide. The material used for the insulatinglayer 7 is an organic or inorganic insulating material with good biocompatibility, and is one of silicon dioxide, silicon nitride, silicon oxynitride, SU8, polyimide or parylene.

The insulatingsubstrate 1 is a carrier of the whole chip, the material of the substrate is quartz glass, the length x width of the insulating substrate is 50mm x 50mm, and the thickness of the insulating substrate is about 1 mm.

According to the neuron NOT gate logic function chip integrating the micro-fluidic and microelectrode array, detection electrode sites of a microelectrode array part are spread and distributed along the center of a substrate; the number of the detection electrodes is 3, the detection electrodes are respectively positioned at the input end, the output end and the center of themicrochannel 10, each group is 15, the diameter of each group is 10 micrometers, the distance between the detection electrodes is 200 micrometers, and the detection electrodes can be used for neuroelectrophysiological signals; the stimulating electrodes surround the left and right of the input end group of detection electrodes, and the interval between the stimulating electrodes is 200 mu m. The stimulatingelectrodes 3 in the stimulating electrode group are formed by 15 pairs of arcs and surround the detecting electrodes at the input end, and can be used for electrically stimulating cells to excite or inhibit the discharge of neurons. A pair ofcounter electrodes 4 is disposed around thedetection electrode array 2 for providing a reference potential and keeping the potential stable. Thecounter electrode 4, the stimulatingelectrode 3 and the detectingelectrode array 2 extend throughleads 5 and are connected to acontact 6 on the periphery of the insulating substrate; all lead 5 surfaces are covered with an insulatinglayer 7.

4cell culture grooves 8 in the microfluidic chip b are used for culturing cells; themicro-channel 9 is connected with thecell culture tank 8 and the micro-channel 10; themicrochannels 10 restrict the passage of the soma of the nerve cell and guide the directional growth of axons. The microelectrode array chip a and the microfluidic chip b are fixedly packaged in a bonding mode to form a novel chip which can guide the directional growth of nerve cells and realize certain logic functions.

The preparation method of the first layer microelectrode array part of the integrated microfluidic and microelectrode array neuron NOT-gate logic function chip comprises the following steps (as shown in figure 4):

a) cleaning the glass sheet for 10-20 minutes by using a boiled concentrated sulfuric acid solution, and removing residual organic impurities or inorganic impurities on the substrate by using the strong oxidizing property of the glass sheet;

b) spin-coating a layer of photoresist on the cleaned glass sheet, wherein the thickness of the photoresist is more than three times of that of a conductive film to be sputtered, and patterning a detection electrode, an electrical stimulation electrode, a counter electrode, a lead and a contact by adopting a photoetching process (positive photoresist AZ 1500);

c) firstly sputtering a 50nm Cr seed layer on the surface of the photoresist pattern to increase the adhesion of the conductive film layer and the substrate, and then sputtering a 250nm Pt layer;

d) removing the redundant Pt layer by adopting a stripping process, and leaving a required detection electrode, an electrical stimulation electrode, a counter electrode, a lead and a contact;

e) deposition of SiO by plasma enhanced chemical vapor deposition (PECVD, 300 ℃ C.)₂(300nm)/Si₃N₄(500nm) an insulating layer;

f) the detection electrode array, stimulation electrode, counter electrode and insulating layer over the contacts are again exposed by photolithography, through CHF₃Reactive Ion Etching (RIE) selectively removes the insulation layer on the micro-electrode and the contact; the insulating layer covering the surfaces of all theleads 5 is reserved;

g) and removing the residual photoresist on the microelectrode array chip by using acetone, and washing the microelectrode array chip by using deionized water.

h) A layer of platinum nano-particles is plated on the microelectrode array detection electrode by adopting an electrochemical timing current method, so that the electrical characteristics of the detection electrode are improved.

The preparation method of the second-layer microfluidic chip of the neuron NOT gate logic function chip integrated with the microfluidic and microelectrode array comprises the following steps (as shown in figure 5):

1) making of master model

a) Spin-coating a layer of negative photoresist with the model number of SU85 on a cleaned silicon wafer, wherein the thickness is 5 μm, and the length is 550 μm;

b) developing the photoresist to form a pattern on the first mask plate, and exposing themicrochannel 10 for the directional growth of cells;

c) spin-coating a layer of SU850 photoresist on the silicon wafer after the first photoetching, wherein the thickness of the photoresist is 100 mu m;

d) and developing the photoresist to form a pattern on a second mask plate, exposing themicro-channel 9 for growth and flow of nerve cells, and making a female die of the flow control device by photoetching.

2) PDMS mold

e) A PDMS prepolymer type Sylgard 184 from dow corning company was mixed with a catalyst in a weight ratio of 10: 1, mixing and fully mixing for 5-10 minutes, and adding into a vessel for holding the female die for casting. Removing bubbles remaining around the pattern in the master mold with nitrogen gas in a vacuum dryer; PDMS was cured in an oven at 70 ℃.

f) When the PDMS was fully crosslinked or cured (the PDMS mixture would become transparent), the PDMS microfluidic device was detached from the master using a blade and a culture well for culturing cells was punched out of the device using a punch.

A microelectrode array layer and a microfluidic chip layer of a neuron NOT gate logic function chip integrating microfluidics and microelectrode arrays activate the surface through plasma etching, and then are attached to form the whole chip.

FIG. 6 is a schematic diagram of a logic NOT gate function implemented on a neuron layer of the integrated microfluidic microelectrode array neuron NOT gate logic function chip.

Example 1:

the neuron NOT gate logic function chip integrating the microfluidic and microelectrode array is adopted to detect the electrophysiological signals of primary cortical neurons

(1) The procedure for culturing primary cortical neurons on a chip is as follows:

a) sterilizing the microelectrode array chip, and coating the chip with laminin (laminin);

b) the cell culture solution on the chip is replaced every 2 to 3 days, the culture is continued for 7 to 14 days, the cultured neurons are subjected to fluorescent staining, and the neurons can be seen to grow directionally to the microchannels after 5 days of culture.

(2) Detecting electrophysiological signals of nerve cells

a) Connecting the chip with the cultured primary neurons with an interface circuit and connecting the chip with an electrophysiological signal detection instrument of Cerebus corporation;

b) glutamic acid is added into the culture microelectrode array to stimulate the discharge of nerve cells, and the discharge condition of the nerve cells is recorded.

(3) The neuron at one end of the electrical stimulation chip detects the response of the neuron at the other end

b) an electrical stimulation instrument of a Multichannel company is connected with an electrical stimulation electrode at the input end of the chip, high-frequency electrical stimulation and low-frequency electrical stimulation are respectively applied, and the discharge condition of a neuron at the output end is recorded.

The invention has not been described in detail and is part of the common general knowledge of a person skilled in the art. The above-described embodiments are merely illustrative of the preferred embodiments of the present invention, and the preferred embodiments are not exhaustive and do not limit the invention to the precise embodiments described. Various modifications and improvements of the technical solution of the present invention may be made by those skilled in the art without departing from the spirit of the present invention, and the technical solution of the present invention is to be covered by the protection scope defined by the claims.

Claims

1. A neuron NOT gate logic function chip integrating micro-fluidic and microelectrode array is characterized by comprising two layers, wherein a first layer of microelectrode array chip (a) comprises: the device comprises an insulating substrate (1), a detection electrode array (2), a stimulation electrode (3), a counter electrode (4), an electrode lead (5), a contact (6) and a surface insulating layer (7); the second layer of microfluidic chip (b) comprises: a cell culture tank (8), a micro-channel (9) and a group of micro-channels (10) for controlling the directional growth of neurons; the microelectrode array chip and the microfluidic chip are packaged by plasma bonding;

the insulating substrate (1) is a carrier of the whole microelectrode array chip (a); the detection electrode arrays (2) are divided into three groups, and are respectively positioned at the input end, the output end and the center of the microchannel (10); the stimulating electrode (3) is positioned around the input end detection electrode; and a counter electrode (4) is arranged around the detection electrode array (2); the counter electrode (4), the stimulating electrode (3) and the detection electrode array (2) extend through leads (5) and are connected to a contact (6) on the periphery of the insulating substrate; the surfaces of all the leads (5) are covered with insulating layers (7); the cell culture groove (8) in the microfluidic chip (b) is used for culturing cells; the micro-channel (9) is connected with the cell culture tank (8) and the micro-channel (10); the microchannels (10) limit the passage of the soma of the nerve cell and guide the directional growth of the axon; the microelectrode array chip (a) and the microfluidic chip (b) are fixedly packaged in a bonding mode to form a chip which can guide the directional growth of nerve cells and realize logic functions.

2. The integrated microfluidic, microelectrode array, neuron NOT-gate logic function chip of claim 1, further comprising: the insulating substrate (1) is made of one of quartz glass, polyvinyl chloride or polycarbonate; the side length of the insulating substrate (1) is 20-50mm, and the thickness is 1-5 mm.

3. The integrated microfluidic, microelectrode array, neuron NOT-gate logic function chip of claim 1, further comprising: the detection electrode in the detection electrode array (2) is composed of 45-108 circular microelectrodes, the diameter is 10-30 μm, the distance between the microelectrodes is 100-500 μm, and the detection electrode can be used for neuroelectrophysiological signals; the microelectrode array chip has 15-36 pairs of arc stimulating electrodes surrounding the detecting electrodes at the input end, and can be used for electrically stimulating cells to realize excitation or inhibition of neuron discharge.

4. The integrated microfluidic, microelectrode array, neuron NOT-gate logic function chip of claim 1, further comprising: the number of the counter electrodes (4) is 2-4, and the counter electrodes are used for providing a reference potential and keeping the potential stable.

5. The integrated microfluidic, microelectrode array, neuron NOT-gate logic function chip of claim 1, further comprising: the microelectrode array chip (a) is made of one of gold, platinum, titanium nitride or indium tin oxide; the material used for the insulating layer (7) is one of silicon dioxide, silicon nitride, silicon oxynitride, SU8, polyimide or parylene.

6. The method for preparing a neuron NOT gate logic function chip integrating microfluidic and microelectrode arrays according to any one of claims 1 to 5, comprising: preparing a first layer of microelectrode array chip (a) and a second layer of microfluidic chip (b);

the method for preparing the first layer microelectrode array chip (a) comprises the following steps:

1) spin-coating a layer of photoresist on the cleaned insulating substrate (1), wherein the thickness of the photoresist is more than three times of that of a conductive film to be sputtered, and forming patterns of a detection electrode array (2), a stimulation electrode (3), a counter electrode (4), a lead (5) and a contact (6) after photoetching development;

3) removing the redundant conductive film layer by adopting a stripping process, and leaving the needed electrode, the lead (5) and the contact (6);

4) covering an insulating layer on the surface of an insulating substrate (1) with a prepared conductive film layer by using a method of plasma enhanced chemical vapor deposition of silicon oxide and/or silicon nitride or spin coating SU8, polyimide and parylene, exposing a detection electrode array (2), a stimulation electrode (3), a counter electrode (4) and a contact (6) by using a method of photoetching or plasma beam etching, and keeping the insulating layer covered on the surface of all leads (5);

5) preparing a platinum metal film layer with the thickness of 200-500nm on the surface of the counter electrode (4) by adopting the processes of photoetching, sputtering and stripping, and if the microelectrode conductive film in the step 2) is made of platinum, the step can be omitted;

6) modifying nano materials or sensitive film materials on the surfaces of microelectrodes with different functions by electrochemical deposition or physical drop coating and adsorption.

7. The integrated microfluidic, microelectrode array, neuron NOT-gate logic function chip of claim 1, further comprising: the second layer of microfluidic chip (b) is prepared by pouring PDMS (polydimethylsiloxane) or PMMA (polymethyl methacrylate) into a master mold made of SU8 photoresist.

8. The method of claim 6, wherein: a method of preparing a second layer of microfluidic chip (b), comprising the steps of:

1) making female die

A. Spin-coating photoresist on the cleaned silicon wafer, wherein the thickness is 5-10 μm, the length is 400-900 μm, and exposing the microchannel (10) for the directional growth of cells after photoetching development;

B. spin-coating photoresist on the silicon wafer after the previous process, wherein the thickness is 50-200 μm, and exposing a micro-channel (9) for growth and flow of nerve cells after photoetching development;

2) fabrication of microfluidic devices

D. removing bubbles remaining around the pattern in the master mold;

E. curing PDMS;

F. and separating the microfluidic device from the master mold, and manufacturing a cell culture groove (8) in the microfluidic device by using a puncher.

9. The integrated microfluidic, microelectrode array, neuron NOT-gate logic function chip of claim 1, further comprising: the chip can stimulate the neuron at one end of the micro channel (10) through the stimulating electrode, so that the neuron at the other end generates the corresponding electrophysiological signal.

10. The integrated microfluidic, microelectrode array, neuron not gate logic function chip of claim 9, wherein: the electrical pulse for stimulating the neuron has two types of excitatory stimulation and inhibitory stimulation, wherein the excitatory stimulation adopts low-frequency bipolar pulse waves with the frequency lower than 5Hz and the amplitude smaller than 0.2V, and the inhibitory stimulation adopts high-frequency bipolar pulse waves with the frequency of 20-100Hz and the amplitude smaller than 0.2V.